1244183 玖、發明說明 【發明所屬之技術領域】 制。本發明係關於-種具有高散熱性的構裝基板結構及其 製程’尤指一種提供晶片構裝的載體，作為 的媒介，並可對晶片工作時產生的高严 ^ ^ 幻回/皿以及高頻數位訊號 傳輸所造成的熱散失，提供快速且有 ^ β双的散熱途徑，並可 穩定傳輸訊號的基板結構及其製程設計。 【先前技術】 目前電子產品的研發’係朝向於輕薄短小的精密輕量 化之趨勢’該電子產品如高功能半導體元件等需具備高散 熱性之效能外，使用高頻數位傳輸訊號也是新世代電子訊 號傳輸的發展方向。 時下已知之半導體構裴載板元件（如：EBGA、SBGA、 LEBGA、··.等型式的元件）中，為使其具有良好的高散熱性 ，其構裝基板多係於背面上黏接金屬散熱片，提供晶片直 接黏著其中’藉以將晶片工作時產生的熱經由該散熱片予 以發散，以避免元件過熱而影響其性能或損壞。 惟，前述半導體元件藉由散熱片的設置，雖可將晶片 工作時產生的熱透過散熱片發散，但對於該元件訊號^輸 時所產生的熱散失，只能藉助熱傳導性不佳的基板介電層 發散，而無法快速地直接傳導至金屬散熱片後發散，導^ 其散熱功能不足，使元件在使用的過程中仍有溫度偏高之 問題。 又，時下高頻數位訊號傳輸模式之應用日益增加，對 1244183 於半導體元件高頻訊號的傳輪， ^ A 叛防制雜訊為通訊上一項, 要的課題，而如何達成雜訊防制， 員重 以改善之外，提供晶片外部 丁 ^ ^ _ 妾的構衣基板亦應具備減少 接地反弹之功用。唯時下已知 <構衣基板構造，並不且借 有效的接地線路設計，當晶η彳电 往 田日日片傳輪訊號時，易有接地訊號 雜訊的產生（接地反彈），導 ν致其汛號傳輸不穩定。 【發明内容】 本發明之主要目的在於拇也 《 在於k仏一種具有高散熱性的構裝 基板結構以及用以製造該基板姓 ^ 巷孜…構的製程，用以克服前揭 習用基板散熱性不佳，以及提供康田认> μ + 久捉仏應用於咼頻電路之晶片具 有較佳之接地性。 Λ 為達成前揭目的，本發明所提出之具有散熱功用的構 裝基板結構’主要係於-金屬散熱片上壓合-介電積層所 成構成，該介電積層可為單_介電層或多層介電層疊合而 成，其上設有延伸至散熱片的晶片容槽，讓散熱片上具有 顯露於晶片容槽底部的黏晶區間，提供晶片黏著於其上， 該介電積層上表面設有圖案化金屬線路，1自金屬線路預 疋接地訊號端設延伸至散熱片的雷射微孔，該雷射微孔中 设有金屬導體，以直接、或以金屬導體上下串接、或配合 設於介電層夾層間之金屬導熱體間接連接於金屬線路與散 熱片之間，該介電積層上表面另設覆蓋於金屬線路上的圖 案化防焊層，並使金屬線路形成複數個顯露於防焊層外的 焊墊，構成一可將晶片工作產生的熱及晶片高頻訊號傳輸 產生的熱散失經由直接傳導至散熱片發散，並可穩定訊號 1244183 傳輸之構裝基板。 本發明所提出之具有高散熱性的構裝基板製程，立少 驟主要係以熱壓合手段於金屬散熱片設導電金屬膜介電積 層’次卩雷射鑽孔手段於該介電積層上設延伸至散妖片的 雷射微孔’並於對該介電積層之雷射微孔施以鍍設導電金 屬化成金屬導體，之後，再於該介電積層上表面以影像移 轉手&形成圖案化金屬線路，塗覆防焊層並形成焊塾，蒋 對介電積層挖設深及散熱片並可容置晶片的晶片容槽，而 完成該構裝基板。 前述介電積層為二層（含）以上介電層之組合時，係 於散熱板上進行預定介電層數週期的介電層壓合、雷射鑽 孔i於雷射微孔中鐘設導電金屬形成金屬導體等步^，再 於取上層介電層之上表面以影像移轉手段形成圖案化金屬 線路’塗覆防焊層以及對介電積層挖設深及散熱片的晶片 容槽步驟。 本發明藉由前揭構裝基板之結構設計，其特點至少包 1、可增進散熱性：本發明所設計的構裝基板，可供 晶片直接黏著於金屬散熱片i，故晶片工作時產生的熱^ 直接傳V至i屬散熱片發散，另晶片於高頻訊號傳輸時所 產生的熱散失可經由介電積層上的金屬線路接地端經雷射 微孔中的金屬導體（及金屬導熱體等）快速且直接傳導至 散熱片發散’使其具極佳的散熱效能。 2、可穩定訊號傳輸、減少雜訊：本發明利用晶片沉 1244183 置於基板之晶片容槽中，縮短連接晶片與基板間之金屬線 長度，以減少訊號傳輸阻抗，另利用介電積層設雷射微孔 、’並於微孔中設金屬導體將金屬'線路中之接地線路端直接 連接至金屬散熱片接地，使其可降低接地電感量，減少接 地訊號雜訊的產生（接地反彈），更可利用雷射微孔中設 實心金屬導體（SQlldVia)導通之方式，進—步減少因導通 孔產生雜散訊號。 本發明所設計的基板構裝製程，則可將本發明之構裝 予以實現，藉此，使其在產業上可被據以實施， 並達成珂揭預期之功用。 【實施方式】 有關本發明具有高散熱性的構裝基板 例，請配人夫M笙一回仏- 舟心，、體只施 口多閱弟一圖所不，該構裝基板（ 散熱片（1 η)卜厭人人士社 丄」係於金屬 積層」):；積層（20)所構成，該介電 22)…）中設有延伸至散熱片（u)的晶片容槽（ 5亥散熱片（1 0 )具有顯露於晶片容槽 底部的黏晶γ M f Ί 〇、 ^2) ，占日^間（1 2 ) ’用以提供晶μ ( 散熱片（1 η、Ά者於該 片容槽（2 2 ) ’二二、積層（2 0 )上表面相對於晶 2 2 )外側设有圖案化金屬線路 了金屬線路（23)預定接地訊號端延伸至散==設 的雷射微孔（24)，該雷射微孔（24);、二(10 導體（…料於金屬線路（23)與中=金屬 之間，另該介電積層（20)上表面設有覆蓋 (23)上的圖案化防烊層（2…並使金屬:::： 1244183 3 )上具有複數個顯露於防焊層（2 6 ”卜的焊 )，其中鄰近晶片容槽（9 ( k 2 2 )之内側焊墊（2 7 )楹也 晶片（2 )電性連接之用、土雜 知供 安之用，m離晶片容槽（2 2 )外 焊墊（2 7 )則提供導電全屬 側之 _ 至屬凸塊（4)固設其上。 前述之介電積層（2())除第__示之單__ 之構造外，亦可如第三圖為_ 冤層 马一層（含）以上的介電層 1)組構而成之構造，复中 · 己 層（2 1 )組構而成之實你彳丨主 電 貫^例時，請配合參閱第三 ，該介電積層（20)Φμτα丄 η ^ u )中上下相鄰介電層（2丄）之1244183 发明, Description of the invention [Technical field to which the invention belongs] Manufacturing. The present invention relates to a mounting substrate structure having a high heat dissipation property and a manufacturing process thereof, and more particularly, to a carrier for providing wafer structure as a medium, and can be used for the high stringency generated during wafer operation. The heat dissipation caused by the transmission of high-frequency digital signals provides a fast and dual heat dissipation path, and can stably transmit the substrate structure and process design of the signal. [Previous technology] The current research and development of electronic products is "toward the trend of light weight, thinness, shortness, precision, and light weight." The electronic products such as high-performance semiconductor components need to have high heat dissipation performance. The use of high-frequency digital transmission signals is also a new generation of electronics. The development direction of signal transmission. Among the currently known semiconductor substrate components (such as EBGA, SBGA, LEBGA, ...), in order to make them have high heat dissipation, the structure substrates are mostly bonded on the back surface. The metal heat sink provides direct chip attachment, so that the heat generated during the chip's operation is dissipated through the heat sink to avoid overheating the component and affecting its performance or damage. However, the aforementioned semiconductor element can dissipate heat generated during chip operation through the heat sink through the arrangement of the heat sink. However, for the heat dissipation generated during the signal transmission of the element, only the substrate with poor thermal conductivity can be used. The electrical layer is divergent, and cannot be directly transmitted to the metal heat sink after it is quickly dissipated. Its heat dissipation function is insufficient, so that the component still has a problem of high temperature during use. In addition, the application of high-frequency digital signal transmission mode is increasing day by day. For the transmission of high-frequency signals from 1244183 to semiconductor components, ^ A rebellion noise is the last topic of communication, and how to achieve noise prevention In addition to improving the quality of the system and improving the staff, the fabric substrates that provide external chip ^ ^ _ 妾 should also have the function of reducing ground bounce. However, nowadays, the structure of the garment substrate is not known, and the effective ground circuit design is not used. When the crystal signal is transmitted to Tianri and Nippana, it is easy to generate ground signal noise (ground bounce). As a result, the transmission of its flood number was unstable. [Summary of the Invention] The main purpose of the present invention is to provide a substrate structure with high heat dissipation and a manufacturing process for manufacturing the substrate. The method is used to overcome the heat dissipation of the substrate used in previous studies. Poor, as well as providing Kang Tian recognition > μ + Jiu Jiu the chip used in audio frequency circuit has better grounding. Λ In order to achieve the purpose of the previous disclosure, the structure substrate structure with heat dissipation function proposed by the present invention is mainly composed of a metal heat-sink laminated with a dielectric build-up layer, which can be a single dielectric layer or The multilayer dielectric is laminated and laminated, and a chip container extending to the heat sink is provided thereon, so that the heat sink has a sticky crystal section exposed at the bottom of the chip container, and the wafer is adhered thereon. The upper surface of the dielectric buildup is provided with There are patterned metal lines. 1 A laser micro-hole extending from the pre-grounded signal end of the metal line to the heat sink is provided with a metal conductor in the laser micro-hole to directly or in series with the metal conductor, or cooperate A metal heat conductor provided between the dielectric layers is indirectly connected between the metal circuit and the heat sink. The upper surface of the dielectric build-up is additionally provided with a patterned solder mask layer covering the metal circuit, and a plurality of metal circuits are exposed. The pads outside the solder mask layer constitute a structure that can dissipate the heat generated by the wafer operation and the heat dissipation generated by the high-frequency signal transmission of the wafer through direct conduction to the heat sink, and can stabilize the transmission of the signal 1244183. Substrate. The process for mounting a substrate with high heat dissipation provided by the present invention is mainly based on a thermal compression bonding method in which a conductive metal film dielectric layer is formed on the metal heat sink, and a secondary laser drilling method is provided on the dielectric layer. A laser micro-hole extending to the scattered monster sheet is set, and the laser micro-hole of the dielectric multilayer is plated with a conductive metal to form a metal conductor, and then the image is transferred on the upper surface of the dielectric multilayer & A patterned metal circuit is formed, a solder resist is coated, and a solder pad is formed. Chiang Digs the dielectric build-up with deep and heat sinks and can accommodate wafer wafer pockets to complete the structured substrate. When the foregoing dielectric laminate is a combination of two or more dielectric layers, the dielectric lamination is performed on a heat sink with a predetermined number of dielectric layers, and laser drilling is performed on the laser micro-holes by conducting metal. Steps of forming a metal conductor, etc., and then taking the upper surface of the upper dielectric layer to form a patterned metal circuit by image transfer means, coating the solder resist layer, and digging the deep layer of the dielectric layer and the heat sink of the wafer. The structure of the present invention is based on the structure design of the front-loaded mounting substrate, which has at least the following features: 1. It can improve heat dissipation: The structured substrate designed by the present invention can directly attach the chip to the metal heat sink i. The heat ^ directly transmitted from V to i belongs to the heat sink, and the heat dissipation generated by the chip during high-frequency signal transmission can pass through the metal conductor in the laser micro-hole (and the metal heat conductor) through the metal circuit ground on the dielectric laminate. Etc.) Fast and direct conduction to the heat sink divergence 'makes it have excellent heat dissipation performance. 2. Stable signal transmission and reduced noise: The present invention uses the wafer sinker 1244183 to be placed in the wafer container of the substrate, shortening the length of the metal wire connecting the wafer and the substrate to reduce the signal transmission impedance, and the dielectric layer is used to set a mine. The micro-holes, and a metal conductor in the micro-holes, directly connect the grounding wire end of the metal 'line to the metal heat sink to ground, so that it can reduce the ground inductance and reduce the generation of ground signal noise (ground bounce). In addition, a solid metal conductor (SQlldVia) in the laser micro hole can be used to conduct electricity to further reduce the stray signal generated by the via hole. The substrate assembly process designed by the present invention can realize the structure of the present invention, thereby enabling it to be implemented in the industry and achieve the expected function. [Embodiment] For an example of a mounting substrate with high heat dissipation properties according to the present invention, please assign a husband M Sheng Yi Zhou-Zhou Xin, the body can only read more than one picture, the mounting substrate (heat sink ( 1 η) The disgusting person's community "is attached to the metal laminate") :; The laminate (20) is formed, and the dielectric 22) ...) is provided with a chip container (5H heat dissipation) extending to the heat sink (u) The wafer (1 0) has a sticky crystal γ M f Ί 〇, ^ 2) exposed at the bottom of the wafer cuvette, and occupies (1 2) 'to provide crystal μ (the heat sink (1 η, The chip container groove (2 2) '22. The upper surface of the multilayer (2 0) is opposite to the crystal 2 2) and a patterned metal line is provided on the outside of the metal line (23). The predetermined ground signal end extends to the diffused == set laser. Micro-holes (24), the laser micro-holes (24); two (10 conductors (... between the metal circuit (23) and the middle = metal), and the upper surface of the dielectric build-up (20) is provided with a covering ( 23) on the patterned anti-rust layer (2 ... and metal :::: 1244183 3) with a plurality of exposed solder resist layers (2 6 "solder), where the wafer receptacle (9 (k 2 2) the inner pad ( 2 7) The chip (2) is also used for electrical connection and soil for safety purpose, and the m pad (2 2) outer pad (2 7) is provided with conductive all-side side _ to the bump (4) It is fixed on it. In addition to the structure of the single __ shown in the above-mentioned dielectric multilayer (2 ()), it can also be as shown in the third figure. Layer 1) is composed of the structure, and the middle layer and the layer (2 1) are composed of the real one. 丨 丨 For the main electrical connection ^ example, please refer to the third, the dielectric multilayer (20) Φμτα 丄η ^ u) in the upper and lower adjacent dielectric layers (2 丄)
間設有圖案化的金屬導熱體（2 9 )，金屬線路（曰 設於最上層介電層（2l)i表面，且該最上層介電/ 2 1 )於其上表面金屬線路（2 3 )予員定處與下表面： 導熱體（2 9 )間之相對應處設有雷射微孔（2 4 )、，\ 雷射微孔（2 4 )中並設有連接金屬線路（2 3 )屬亥 導熱體（29)的金屬導體（25)，最下層介電：：： D則設有自上表面金屬導熱體（29)朝下方& Y 1〇)延伸的雷射微孔（24)，該雷射微孔（2:: 設有連接（29)與散熱片（1〇)之間的全 屬導體（25)，介於最上層介電層（21)與最下層介 電層（21)間之各中層介電層（21)進一步於上；々 金屬導熱體（2 9 )之間預定處設有雷射微孔（ ，曰 該雷射微1 (24)中另設有連接上、下層金屬導敎體（ 29)的金屬導體（25) ’若該介電積層（2〇)、、、為上 下二介電層（21)組構而成時，則無上述之中層介電層 1244183 構造。 前述設於介電積層（20)雷射微孔（24)中的金 屬導體（2 5 )可如第一、三圖所示之實心體，或為附著 於孔壁上的空心薄層。 前述之介電積|(2〇)為二層（含）以上的介電層 (2 1)組構而成之構造時，該上下介電層（2〇)之雷 射微孔可為上下不對應，並藉金屬導熱體（2 9 )連接田 或者，如第四、五圖所示，該上下介電層（20)之各雷 射微孔（2 4 )可為上下對應狀，且利用上下雷射微孔^ 2 4 )中的實心金料冑（2 5 )直接對應連接，或如第 五圖所示，於下層雷射微孔（2 4 )㈤空心金屬導 5)中設導電金屬凸塊（191)直接連接上層雷射微孔 (2 4 )的金屬導體（2 5 )。 前述設於介電積層^ 9 η彳+ 电積層頂面顯露於防焊層 二卜=(2”表面可鍍設一錄金合金(Ni/au)的： ^ " 以利金屬線（3 )、導電金屬凸塊（4 ) 焊接於該焊墊（2 7 )上。 ） 前述中，該金屬散熱片（i 〇 )為介電積層 之覆盍部份可形成圖案化的鰭片（1 , u ) ’如第二圖戶斤+ ，用以增加與介電層之接著性。 不 另’金屬散熱片（i 0 )於其黏晶 面可覆設一絕緣層（圖未示），或者， 一之表 ^ -5p ^ 、_ 一一 圖戶$ 丁 ，該金屬散熱片（i 〇 )於黏晶區 不 Q , 门^ 1 2 )處形成黏晶 凹槽（1 3 )，並於該黏晶凹槽（丄 夕衣面覆設一絕緣 1244183 層（1 zi、 、’ _ . _ ，刖述之絕緣層（1 4 )可為望色的气# © 该金屬散埶H ，n、 勺…、已的乳化層 欲熟片（1 0 )可為銅（Cu) #， 層可為銼f λτ •、上 八外表面鍍設 。‘、/、 1)或其他不易氧化的金屬抗氧化層 月’』述之介電層可因應不同之電性 電姑Μ，π &用不同的介 如 Gteck、FR 4、FR 5、BT、箄，斟认 > 時，則可撰田你八+ a …荨，對於咼頻需求 ，來達::：介電常數的材料，或改變該介電層的厚度 木運到阻抗匹配的需求。 ^心前揭之構裝基板結構料，於構裝時，係將 :;的二黏？於該基板（1)位於晶片容槽（22)底 片曰(1〇)黏晶…12)上，另以金屬線（ 連接於日日片（2)上各接點盘美杯^ H基板（1 )上對應的焊 U 了）之間，二欠將其晶片及接線區以灌膠封固，再於 基板（1)外圍焊塾（27)上設導電金屬凸塊（4)構 成-+導體元件’該半導體元件並以其導電金屬凸塊（4 )朝下焊接於電路板的線路上作外部電性連接，即可讓該 半導體元件受控於電路板工作。 本發明藉由前揭構裝基板結構設計，於使用時至少具 有以上優點，其中： 〃 1、可增進散熱性：本發明所設計的構裝基板，可供 晶片直接黏著於金屬散熱片上，故晶片工作時產生的熱可 直接傳導至金屬散熱片發散’另晶片於高頻訊號傳輸時所 產生的熱散失可經由介電積層上的金屬線路接地端經雷射 微孔中的金屬導體（及金屬導熱體等）快速傳導至散熱片 1244183 發散，使其具極佳的散熱效能。 2、可穩定訊號傳輸、減少雜訊：本發明所設計的構 裝基板利用晶片沉置於基板（1)之晶片容槽（22)中 ，可縮短接於晶片（2 )與基板（1 )間之金屬線（3 ) 長度’減少訊號傳輸阻抗，此外，本發明利用介電積層設 雷射微孔’並於其中設金屬導體將金屬線路中之接地線路 端直接連接至金屬散熱片接地’使其可降低接地電感量， 減少接地訊號雜訊的產生（接地反彈），更可利用雷射微 孔中設實心金屬導體（Solid Via)導通之方式，進一步減少 因導通孔產生雜散訊號。 為完成前揭構裝基板結構，本發明接續設計了實現該 構裝基板構造的創新製程，首以介電積層為單一介電層之 構裝基板為例，其製程包括以下步驟： 提供-如銅等具高導熱性的金屬散熱片，如第六入圖 所示’該金屬散熱4(1〇)上表面可利用影像移轉手段 沉積或㈣出圖案化㈣片（！1)，如第六B圖所示， 或者，該金屬散敎只Π") 月c1u)上亦不設該圖案化的鰭片； 以熱屋合手段於該金屬散熱片（丄〇)上覆咬 =導ΓΓ膜（210)(如銅⑷的介電積層： 2 第六C圖所示’其中散熱片（1〇)上設有韓 片（11)時’可藉‘鰭片（11)增 )間的接著性； 电檟層C 2 0 劣世、S S人显4 6 U )預定位置處形 成貝通至孟屬政熱片（丄〇 ) q田射被孔（2 4 )，如第 12 1244183 六D圖所示； 對介電積層（2 0 )之雷射微孔（2 4 )及置卜本 〆、工衣面 知以鍍設如銅等之導電金屬步驟，如第圖所示，使带 射微孔（2 4 )形成一可為空心或實心的金屬導體（2 ^ )，連接導電金屬膜與金屬散熱片（工〇 )之間，於本每 施例中，於雷射微孔（24)中係採取形成空心金屬導二 (2 5)之方式，此一步驟之後，再以介電材（2丄2 填平雷射微孔（2 4 )，如第六F圖所示；以影像移轉手 &於導電金屬膜（21〇)上形成圖案化的乾膜（2丄1鲁 )，如第六G圖所示； 對導電金屬膜（2 1 〇)顯露於圖案化乾膜（2丄工 )外之邛伤鍍设鎳金合金（N i /Au)之助焊層（2 8 )， 第六Η圖所示； 剝離覆設於導電金屬膜（2 1 0 )上的乾膜（2丄丄 )，如第六I圖所示； 以影像移轉手段於導電金屬^ ( 2 1 0 )上㈣出圖 案化的金屬線路（23)，如第六】圖所示，該金屬線路 (23)連接雷射微孔（24)内的金屬導體； 於介電積層（2 〇 )及金屬線路（2 3 )丨塗覆一圖 案化防*干層（2 6 )，如第六K圖所示，並使該金屬線路 (2 3 )形成顯露於防焊層（2 6 )外的焊墊（2 7 ); 對孟屬散熱片（1 〇 )外表面鍍設一可為鎳之抗氧化 曰（1 5 )，如第六L圖所示；以及 對；1電積層（2 〇 )預定位置處挖設深及散熱片（1 13 1244183 ο)並可容置晶片的晶片容丄 v 乙y 、μ圖所示 匕槽日寸’可進一步深入散熱片（ 使其形成黏 成该構裝基板之製造 曰曰軋（1 3 )，如第六Ν圖所示，該黏晶凹槽（i 3 ) 表面可再沉積一可為黑色氧化層之絕緣層（i 4 )，而完 ^前述之製程步驟中，亦可於介電積層（2 〇 )之雷射 U孔（2 4 )及其上表面完成鍍設導電金屬步驟之後，直 接以影像移轉手段於導電金屬膜上钮刻出圖案化的金屬線 路（圖未示），接續於介電積層及金屬線路上塗覆一圖案φ 化防焊層’對金屬線路顯露於防焊層外的焊墊上鍵設錄金 合金（Ni/Au)之助焊層，再對金屬散熱片外表面鍍設一可 為鎳之抗氧化層，以及對介電積層挖設晶片容槽等步驟。 有關本發明應用於製造多層介電層構成介電積層之構 裝基板製造，以三介電層構成之介電積層為例，其製程包 括以下步驟： 提供一具高導熱性的金屬散熱片，如第七八圖所示， 該金屬散熱片（1〇)上表面可利用影像移轉手段沉積或 融刻出圖案化的韓片（11) ’如第七B圖所示，或可不 設該圖案化的鰭片； 以熱壓合手段於該金屬散熱片（10)上覆設一上表 面具有導電金屬膜（21〇a)的第—介電層（2ia)， 如第七C圖所示； 以雷射鑽孔手段於該第—介電層（2 la)預定位置處 形成貫通至金屬散熱片（10)的雷射微孔（24a)，如 14 1244183 第七D圖所示； 對第一介電層（2 la)之雷射微孔（24a)及其上 表面施以鍍設導電金屬步驟，使雷射微孔（2 4 &)形成一 可為空心或實心的金屬導體（25a)，如第七£圖所示， 連接導電金屬膜（21〇a)與金屬散熱片（1〇)之間， 於本實施例中，於雷射微孔（2 4a)中係採取形成空心金 屬導體（2 5 a)之方式； 以影像移轉手段令第一介電層上的導電金屬膜（2工 〇a)形成圖案化的金屬導熱體（29a)，如第七f圖所 不，金屬導熱體（2 9a)連接雷射微孔（2 4a)内的金 屬導體（2 5 a)； 以熱壓合手段於該第一介電層（2 la)上覆設一上表 面具有導電金屬膜（21〇b)的第二介電層（2ib)， ^第七G圖所示，該第二介電層（2 lb)之介電材並填充 第-介電層（2 la)之空心金屬導體（2 5a)内部空間There are patterned metal heat conductors (2 9), and metal circuits (say on the surface of the uppermost dielectric layer (2l) i, and the uppermost dielectric / 2 1) on the upper surface of the metal circuit (2 3 ) Identified place and the lower surface: The laser micro holes (2 4), \ laser micro holes (2 4) are provided in the corresponding places between the heat conductors (2 9) and the connecting metal lines (2 3) The metal conductor (25) belonging to the heat conductor (29), the lowest dielectric :: D is provided with laser micro holes extending from the upper surface of the metal heat conductor (29) downwards & Y 1〇) (24), the laser micro-hole (2 :: is provided with a full-scale conductor (25) between the connection (29) and the heat sink (10), between the uppermost dielectric layer (21) and the lowermost dielectric layer Each intermediate dielectric layer (21) between the electrical layers (21) is further above; a predetermined position between the metal heat conductor (2 9) is provided with a laser microhole (, said laser micro 1 (24) in another A metal conductor (25) connected to the upper and lower metal conductors (29) is provided. If the dielectric laminate (20), and the upper and lower dielectric layers (21) are formed, there is no such thing. The structure of the middle dielectric layer 1244183. The metal conductor (2 5) in the multilayer (20) laser micro-hole (24) can be a solid body as shown in the first and third figures, or a hollow thin layer attached to the wall of the hole. (2) When the structure is composed of two or more dielectric layers (21), the laser micropores of the upper and lower dielectric layers (20) may not correspond to the upper and lower layers, and the metal The heat conducting body (2 9) is connected to the field or, as shown in the fourth and fifth figures, the laser micro holes (2 4) of the upper and lower dielectric layers (20) may be vertically corresponding, and the upper and lower laser micro holes are used. ^ 2 4) The solid gold material 胄 (2 5) is directly connected correspondingly, or as shown in the fifth figure, a conductive metal bump (191) is provided in the lower laser micro hole (2 4) ㈤ hollow metal guide 5). ) Is directly connected to the metal conductor (2 5) of the upper laser micro-hole (2 4). The foregoing is provided on the dielectric buildup ^ 9 η 彳 + The top surface of the electrical buildup is exposed on the solder resist layer == (2 "The surface can be plated with a gold alloy (Ni / au): ^ " Eli metal wire (3 ), The conductive metal bump (4) is soldered to the pad (2 7).) In the foregoing, the metal heat sink (i 〇) is a covering part of the dielectric build-up layer to form a patterned fin (1) , u) 'As shown in the second figure + +, it is used to increase the adhesion to the dielectric layer. No other' metal heat sink (i 0) can be covered with an insulating layer (not shown) on its crystal surface, Alternatively, a table ^ -5p ^, _ _ one picture d, the metal heat sink (i 〇) forms a sticky crystal groove (1 3) at the sticky crystal region (Q, gate ^ 1 2), and An insulative 1244183 layer (1 zi,, '_. _) Is provided on the sticky crystal groove (Yi Xi clothing surface, and the insulating layer (1 4) described above may be the color of the gas # © 该 金属 散 埶 H, n, spoon ..., the emulsified layer (1 0) can be copper (Cu) #, the layer can be file f λτ •, the outer surface of the upper eight plating. ', /, 1) or other non-oxidizable The dielectric layer described in "Metal Oxidation Resistant Layer" In the same way, when using different media such as Gteck, FR 4, FR 5, BT, 箄, and & >, you can compose Tian + a + a… net, for high frequency requirements, Laida ::: material with a dielectric constant, or change the thickness of the dielectric layer to meet the needs of impedance matching. ^ The structure of the substrate before the substrate is exposed, when the structure is assembled, it will be :; ? The substrate (1) is located on the wafer container (22) on the negative film (10) sticky crystal ... 12), and a metal wire (connected to each contact plate on the Japanese-Japanese film (2) is a beautiful cup ^ H substrate) (1) Between the corresponding soldering U), the wafer and the connection area are sealed with glue, and then a conductive metal bump (4) is formed on the outer welding pad (27) of the substrate (1). + Conductor element 'The semiconductor element is soldered down on the circuit board with its conductive metal bump (4) for external electrical connection, so that the semiconductor element can be controlled to work on the circuit board. The structure design of the mounting substrate has at least the above advantages during use, among which: 〃 1. Can improve heat dissipation: The mounting substrate designed by the present invention can be used for wafer direct Adhere to the metal heat sink, so the heat generated by the chip can be directly transmitted to the metal heat sink to dissipate the heat generated by the chip during high-frequency signal transmission. The metal conductor (and metal thermal conductor, etc.) in the hole is quickly conducted to the heat sink 1244183 to diverge, which makes it have excellent heat dissipation performance. 2. Stable signal transmission and reduced noise: the structured substrate designed by the present invention uses a wafer Settled in the wafer container (22) of the substrate (1), the length of the metal wire (3) connected between the wafer (2) and the substrate (1) can be shortened to reduce the signal transmission impedance. In addition, the present invention uses dielectric Laminated with laser micro-holes and metal conductors in them to directly connect the grounding wire end of the metal line to the metal heat sink to ground. This can reduce the amount of ground inductance, reduce the generation of ground signal noise (ground bounce), and more A solid metal conductor (Solid Via) in the laser micro-hole can be used for conduction to further reduce stray signals generated by the via. In order to complete the pre-exposure of the structured substrate structure, the present invention continues to design an innovative process for realizing the structure of the structured substrate. First, a structured substrate with a dielectric layer as a single dielectric layer is taken as an example. The manufacturing process includes the following steps: Provide-such as copper Such as a metal heat sink with high thermal conductivity, as shown in the sixth figure, 'the upper surface of the metal heat sink 4 (10) can use image transfer to deposit or extract a patterned fin (! 1), such as the sixth As shown in Fig. B, or the patterned fins are not provided on the metal plate 敎 ") month c1u); the metal heat sink (丄 〇) is covered with a bite = conductive film (210) (such as the dielectric layer of copper ⑷: 2 shown in Figure 6C, 'where the heat sink (10) is provided with a Korean film (11),' borrowable 'fins (11) can be added)) The electrical layer C 2 0 is inferior and the SS person is 4 6 U) A Beitong-Mengsi political heat film (丄 〇) is formed at a predetermined position. As shown in the figure, the laser micro-holes (2 4) of the dielectric build-up layer (20) and the surface of the conductive fabric, such as copper, are known. The strip micro-holes (2 4) form a hollow or solid metal conductor (2 ^), which is connected between the conductive metal film and the metal heat sink (work). In each embodiment, the laser micro-holes (24) The Chinese system adopts the method of forming a hollow metal guide two (2 5). After this step, the laser micro holes (2 4) are filled with a dielectric material (2 丄 2), as shown in the sixth F diagram. ; Use image transfer to & form a patterned dry film (2 丄 1 Lu) on the conductive metal film (21〇), as shown in Figure 6G; The conductive metal film (2 1〇) is exposed to the patterning Nickel-gold alloy (N i / Au) plating flux layer (2 8) is coated on the surface of the dry film (2 masonry), as shown in the sixth figure; the conductive metal film (2 1 0) is peeled and overlaid. The dry film (2 丄 丄) on the top is shown in the sixth figure I; a patterned metal circuit (23) is drawn on the conductive metal ^ (2 1 0) by means of image transfer, as shown in the sixth figure It is shown that the metal circuit (23) is connected to the metal conductor in the laser micro-hole (24); the dielectric multilayer (20) and the metal circuit (2 3) are coated with a patterned anti-drying layer (2 6) , As shown in the sixth K diagram, and make the metal line (2 3) forming a solder pad (2 7) exposed outside the solder resist layer (2 6); plating the outer surface of the Monsoon heat sink (10) with an anti-oxidation which can be nickel (1 5), such as The sixth L is shown in the figure; and right; the depth and heat sink (1 13 1244183 ο) of the electric lamination (20) at a predetermined position and the chip can be accommodated. The groove can be further penetrated into the heat sink (to make it form the bonding substrate), as shown in FIG. 6N, the surface of the sticky crystal groove (i 3) can be re-deposited. An insulating layer (i 4) that can be a black oxide layer, and in the process steps described above, the laser U hole (2 4) and the upper surface of the dielectric build-up layer (20) can be plated to conduct electricity. After the metal step, a patterned metal circuit (not shown) is directly etched on the conductive metal film by an image transfer method, and then a patterned φ-shaped solder resist layer is coated on the dielectric layer and the metal circuit to the metal circuit. A soldering layer of gold alloy (Ni / Au) is set on the bonding pad exposed outside the solder resist layer, and the outer surface of the metal heat sink is plated with an anti-oxidation which can be nickel. And a dielectric laminate dug wafer receiving groove step and the like. Regarding the application of the present invention to the manufacture of structural substrates with multiple dielectric layers constituting a dielectric build-up, taking a dielectric build-up consisting of three dielectric layers as an example, the manufacturing process includes the following steps: providing a metal heat sink with high thermal conductivity, As shown in Figure 78, the upper surface of the metal heat sink (10) can be deposited or fused with a patterned Korean film (11) by using image transfer means, as shown in Figure 7B, or it can be omitted. Patterned fins; a first dielectric layer (2ia) with a conductive metal film (21a) on its upper surface is overlaid on the metal heat sink (10) by means of thermocompression bonding, as shown in Figure 7C A laser micro-hole (24a) penetrating to the metal heat sink (10) is formed at a predetermined position of the first dielectric layer (2la) by means of laser drilling, as shown in FIG. 14 1244183, seventh D; The step of plating conductive metal is applied to the laser microhole (24a) of the first dielectric layer (2la) and the upper surface thereof, so that the laser microhole (2 4 &) forms a metal that can be hollow or solid The conductor (25a) is connected between the conductive metal film (21〇a) and the metal heat sink (10) as shown in the seventh figure. In this embodiment, In the example, a hollow metal conductor (2 5 a) is formed in the laser micro hole (24a); a conductive metal film (2a) is formed on the first dielectric layer by means of image transfer The patterned metal heat conductor (29a), as shown in the seventh f figure, the metal heat conductor (29a) is connected to the metal conductor (2 5a) in the laser micro hole (24a); A second dielectric layer (2ib) with a conductive metal film (21b) on the upper surface is overlaid on the first dielectric layer (2la). As shown in FIG. 7G, the second dielectric layer ( 2 lb) of dielectric material and filled the inner space of the hollow metal conductor (2 5a) of the first dielectric layer (2 la)
以雷射鑽孔手段於該第二介電層（2 lh、2 …丄 J預定位置處 形成貫通至金屬導熱體（2 9b)的雷射微 丄你 L ( 2 4 b), 如第七Η圖所示； 、。丄… ν ^ 4 b)及复卜 表面施以鍍設導電金屬步驟，如第七I圖所示， ，、 孔（2 4b)形成一可為空心（或實心）的金屬導：：射微 b)，連接導電金屬膜（2l〇C)與第一介 ' 2 5 之金屬導熱體（2 9a)之間，以上述之步帮、& 1 a) 乂驟違行第三層介 15 1244183 电运（21)(即最上層介電層）之屙八 對雷射# 土 Q、雷射鑽孔以及 二 （24C)中鍍設金屬導體（25c)等牛赞 如第七；、第七K、第七L、第七編5〇桃， (2 1 9 w* τ 弟Μ圖所不，並於介電材 再真平雷射微孔（24C)，如第七Ν圖所示； 再以影像移轉手段於最上層介 , 屬膜（2 1 nr、L 曰；ί玉層（2 1 c)之導電金 0圖所示； 开’成圖案化的乾膜…D，如第七 對導電金相（21Qe)㈣於 )外之部份鍍設鎳金（Ni/Au)入八…钇膜（211 第七p圖所示； /AU) s金的助谭層⑴），如 剝離覆設於導電金屬膜（ )，一 蜀腰C 2 1 0 C)上的乾膜（2 1 1 ) 如弟七Q圖所示； 宰二！移轉手段於導電金屬膜（21〇〇上姓刻出圖 案化的金屬線路（23)，如第七R圖所示； =電積層（20)及金屬線路（23)上塗 =㈣層（26) ’如第七S圖所示，並使該金屬線路 )形成顯露於防焊層（26)外的焊塾（27); “屬政熱片（1 0 )外表面鍍設-可為鎳或其他材 枓專之抗氧化層（15)，如第七T圖所示；以及 對介電積層（2η、 υ )預疋位置處挖設深及散熱片（] 0 )並可容置晶片（2 )的晶片容槽（2 2 )，如第七u 圖所示’於挖槽時，亦可進-步深人散熱片（1Q)内， 使其形成黏晶凹槽（1 3 ) ’該黏晶凹槽（1 3 )表面可 再儿積彳為黑色氧化層或其他絕緣材料之絕緣層（1 4 16 1244183 )9如第七v圖所示，而& + 。 而凡成邊多介電層構裝基板之製造 前述之製程步驟中，介π▲ ^ ^ # ^ 亦可於最上層介電層之雷射微孔 及^、上表面元成鑛設真 手#於l入s 至屬步驟之後，直接以影像移轉 ，接續於介電積声及人^ 的 路（圖未示） 全屬绫、曰”屬線路上塗覆-圖案化防焊層，對 金屬料顯㈣防焊層外的焊墊域設鎳金合金（隨u) 、干\再對金屬散熱片外表面鑛設-可為鎳之抗氧化 :一及對’丨電積層挖設晶片容槽等步驟。前揭介電積層 ::層二電：組構而成時，係刪除第二介電層之製程步驟 、曾; &成第介電層之雷射鑽孔、雷射微孔中錢設金屬 ¥:以及形成圖案化的金屬導熱體等製程步驟後，直接 ;第“"電層上壓合具導電金屬膜的第三介電層（即最上 層：電層）、雷射鑽孔、雷射微孔中鍍設金屬導體，接續 4電金屬膜上形成圖案化的乾膜、鍍設助焊層、剝離乾 膜、钱刻出圖案化的金屬線路、塗覆防焊層、於金屬散熱 片外表面鍍设抗氧化層，以及對介電積層挖設深及散熱片 的日日片奋槽等後續製程步驟，完成基板製造完成；若該介 '、θ為一層以上介電層組構而成時，則反復進行上述第 一介電層之製步驟，使其具有多層第二介電層，最後再進 行第三介電層之製程步驟。 刮述製程步驟中，亦可於介電積層（2 〇 )之雷射微 孔（2 4 )完成鍍設導電金屬步驟之後，直接以影像移轉 手段於導電金屬膜上蝕刻出圖案化的金屬線路（圖未示） 17 1244183 金％於介電積層及金屬線路上塗覆一圖案化防焊層，對 :且線路顯露於防焊層外的焊墊上鑛設錄金合金（^/如） 以助垾層，再接續對金屬散熱片外表面鍍設一抗氧化層， 及鮮介電積層挖設晶片容槽等步驟。 。、前揭具有多層介電層構成介電積層之構裝基板製造亦 可以下列製程步驟完成，該製程係包括： 提供一具高導熱性的金屬散熱片，如第八Α圖所示， 該金屬散熱片（工0 )上表面可利用影像移轉手段沉積或 姓刻出圖案化的韓片（i丄），如第A Β圖所示，或可不鲁 設該圖案化的鰭片·， 以熱壓合手段於該金屬散熱片（1〇)上覆設一第一 介電層（2 1 a )，如第八c圖所示； 以雷射鑽孔手段於該第一介電層（2丄a)預定位置處 形成貫通至金屬散熱片（1 〇 )的雷射微孔（2 4a)，如 八D圖所示； 對第一介電層（2 1 a)之雷射微孔（2 4 a )施以鍍 設導電金屬步驟，使雷射微孔（2 4a)形成一可為空心或 _ 實心的金屬導體（25a)連接金屬散熱片（1〇)，如第 八E圖所示； 以熱壓合手段於該第一介電層（2 ia)上覆設一第二 介電層（2 1b)，如第八f圖所示； 以雷射鑽孔手段於該第二介電層（2丄b )上設對應第 ，介電層（2 1 a )電射微孔（2 4 a )的雷射微孔（2 4 b)，如第八G圖所示； 18 1244183 對弟—介電層（2 lb)之雷射微孔（24b)鍍設導 电金屬，如第八Η % - 圖所不’使雷射微孔（2 4 b)形成一可 马空心或實心的金屬道 ”屬V體（25b)，並連接第一介電層（ 2 la)之金屬導體（2 5a); 介♦壓合一上表面具有導電金屬膜（2 1 〇 c)的第三層 )(即最上層介電層），並於其上施以雷射 孔對田射微孔（2 4 c)中鍍設連接第二介電層（2 1 #)金屬^體（25b)的金屬導體（25c)等步驟，如 第八1、第八J、第八K圖所示； +再以衫像移轉手段於最上層介電層（2 1 c〇之導電金 屬膜（21QG)上形成目案化的乾膜（211)，如第八 八L圖所示； 對導電金屬膜 1 Oc)顯路於圖案化乾膜（2工工 )外之部份鍍設鎳金（Ni/Au)合金的助悍層（2 8)，如 第八Μ圖所示； 剝離覆設於導電金屬膜（2 1 0。）上的乾膜（2 ! 1 )，如第八N圖所示； 以影像移轉手段於導電金屬膜（2 1 〇c)上蝕刻出圖 案化的金屬線路（23)，如第八〇圖所示； 於"電積層（2〇)上表面及金屬線路（23)上塗 覆一圖案化防焊層（26) ’如第八p圖所示，並使該金 屬線路（2 3 )形成顯露於防焊層（2 6 )外的焊塾（2 7 ); 對金屬散埶片f Α、μ ± …、（1 〇 )外表面鍍設一可為鎳等之抗氧 19 1244183 化層C 1 5 )，如第八Q圖所示；以及 對介電積層（2 0 )預定位置處挖設深及散熱片（工 0 )並可容置晶片（2 )的晶片容槽（2 2 )，如第八R 圖所示，於挖槽時，亦可進一步深入散熱片（丄〇 )内， 使其形成黏晶凹槽（1 3 )，該黏晶凹槽（1 3 )表面可 再沉積一可為黑色氧化層之絕緣層（丄4 )，如第八s圖 所不’而完成該多介電層構裝基板之製造。Laser drilling is performed on the second dielectric layer (2 lh, 2… 丄 J to a predetermined position to form a laser micro piercing through the metal heat conductor (2 9b). You L (2 4 b), such as the seventh As shown in the figure;,. 丄 ... ν ^ 4 b) and the step of applying conductive metal plating on the complex surface, as shown in the seventh figure I, the holes (2 4b) form a hollow (or solid) Metal guide :: micro-b), connect the conductive metal film (2l0C) and the first metal thermal conductor (2 9a), using the steps above, & 1 a) steps Violation of the third layer of dielectric 15 1244183 Electric transport (21) (ie, the uppermost dielectric layer) of eighteen pairs of lasers # soil Q, laser drilling, and two (24C) plated metal conductors (25c) and other cattle Like the seventh ;, the seventh K, the seventh L, the seventh series of 50 peaches, (2 1 9 w * τ Di M map not, and the dielectric material is really flat laser pores (24C), such as The seventh N is shown in the figure; the image is transferred to the uppermost layer, which is a film (2 1 nr, L); the conductive gold of the jade layer (2 1 c) is shown in the 0; it is turned into a patterned Dry film ... D, such as the seventh pair of conductive metallographic (21Qe) plating on) Gold (Ni / Au) into eight ... Yttrium film (shown in Figure 211, seventh p; / AU) s Au's helper layer), such as peeling and overlaying on the conductive metal film (), one waist C 2 1 0 The dry film (2 1 1) on C) is shown in the picture of Di Qi Q; The transfer means engraved the patterned metal circuit (23) on the conductive metal film (2100), as shown in the seventh R figure; = coating on the electrical layer (20) and the metal circuit (23) = hafnium layer (26 ) 'As shown in Figure 7S, and make the metal line) to form a welding pad (27) exposed outside the solder mask layer (26); "the outer surface of the political hot plate (1 0) is plated-may be nickel Or other material-specific anti-oxidation layer (15), as shown in the seventh T diagram; and deep and heat sinks (] 0) can be dug at the pre-position of the dielectric laminate (2η, υ) and can accommodate the chip (2) The chip receiving groove (2 2), as shown in the seventh u figure, when digging the groove, it can also enter the step-by-step human heat sink (1Q) to form a sticky crystal groove (1 3) 'The surface of the sticky crystal groove (1 3) can be further accumulated as a black oxide layer or an insulating layer (1 4 16 1244183) 9 of other insulating materials, as shown in the seventh v chart, and & +. In the manufacturing process of the substrate with a multi-dielectric layer structure, the dielectric π ▲ ^ ^ # ^ can also be used in the laser micro-holes of the upper dielectric layer and ^, and the upper surface element is mineralized. After entering the s subordinate step, directly transfer with the image Connected to the road of dielectric sound and people (not shown in the figure) All of them are coated-patterned solder masks on the lines of “绫” and “属”, and nickel-gold alloys are set on the pads outside the solder resist. (With u), dry, and then mine the outer surface of the metal heat sink-it can be the oxidation resistance of nickel: first, and the step of digging the chip tank for the electrodeposition layer. Pre-exposure dielectric layer :: Layer two electricity: When assembled, it is a process step of deleting the second dielectric layer, & forming laser drilling and laser micro holes in the second dielectric layer. Metal ¥: After the process steps such as forming a patterned metal heat conductor, directly press the third dielectric layer (ie, the uppermost layer: electrical layer) with a conductive metal film on the electrical layer, and laser drilling 、 Laser micro-holes are plated with metal conductors, then a patterned dry film is formed on the 4 electrical metal film, a soldering layer is plated, the dry film is peeled off, a patterned metal circuit is etched, a solder mask is applied, and The outer surface of the metal heat sink is plated with an anti-oxidation layer, and the subsequent process steps such as digging the dielectric build-up layer and the daily heat sink of the heat sink are completed to complete the manufacture of the substrate; if the dielectric 'and θ are more than one dielectric layer When it is structured, the manufacturing process of the first dielectric layer described above is repeated to make it have multiple second dielectric layers, and then the manufacturing process of the third dielectric layer is finally performed. After the laser micro-holes (2 4) of the dielectric multilayer (20) are finished with the step of plating the conductive metal, directly The patterned metal circuit is etched on the conductive metal film by means of image transfer (not shown). 17 1244183 Gold% Coat a patterned solder mask on the dielectric build-up layer and the metal circuit. To: The circuit is exposed to the solder mask. A gold alloy (^ / such) is deposited on the pads outside the layer to assist the layer, and then the outer surface of the metal heat sink is plated with an anti-oxidation layer, and the fresh dielectric layer is used to excavate the wafer tank. The fabrication of a structured substrate with a multi-layered dielectric layer and a dielectric build-up layer can also be completed by the following process steps, which include: Providing a metal heat sink with high thermal conductivity, as shown in Figure 8A, the metal heat sink On the top surface of the film (work 0), a patterned Korean film (i 丄) can be deposited or engraved using the image transfer method, as shown in Figures A and B, or the patterned fins may not be provided. A first dielectric layer (21a) is overlaid on the metal heat sink (10) by pressing, as shown in FIG. 8c; a laser drilling method is used on the first dielectric layer (2).丄 a) A laser micro-hole (24a) is formed at a predetermined position and penetrates to the metal heat sink (10), such as Shown in Figure 8D; the step of plating the conductive micro-holes (2 4 a) of the first dielectric layer (2 1 a) with a conductive metal is applied to form the laser micro-holes (2 4a) into a hollow or _ A solid metal conductor (25a) is connected to the metal heat sink (10), as shown in Figure 8E; a second dielectric layer is overlaid on the first dielectric layer (2ia) by means of thermocompression bonding. (2 1b), as shown in FIG. 8f; and a laser drilling method is provided on the second dielectric layer (2 丄 b) to correspond to the first and second dielectric layers (2 1 a) with radioactive micropores (2 4 a) Laser micro-holes (2 4 b), as shown in Figure 8G; 18 1244183 Laser micro-holes (24b) of the opposite-dielectric layer (2 lb) are plated with conductive metal, as in八 Η%-Figure does not 'make the laser micro-holes (2 4 b) form a comba hollow or solid metal track "belongs to the V body (25b), and is connected to the metal conductor of the first dielectric layer (2la) (2 5a); the first layer with a conductive metal film (2 10c) on the top surface (ie, the uppermost dielectric layer), and a laser hole is applied to the field micro-hole (2 4 c) metal plating (25c) connected to the second dielectric layer (2 1 #) metal body (25b) and so on , As shown in the eighth, eighth, eighth, and eighth K diagrams; + by the shirt image transfer means on the top dielectric layer (2 1 c0 conductive metal film (21QG) to form a targeted dry The film (211), as shown in the eighty-eighth L; the conductive metal film 1 Oc) is exposed outside the patterned dry film (2 workers) with a nickel-gold (Ni / Au) alloy plating aid Layer (2 8), as shown in the eighth M diagram; peeled and overlaid on the conductive metal film (2 10). ) On the dry film (2! 1), as shown in the eighth N diagram; the patterned metal circuit (23) is etched on the conductive metal film (21oc) by means of image transfer, such as the eighth. As shown in the figure; a patterned solder resist layer (26) is coated on the upper surface of the "electrodeposition layer (20)" and the metal circuit (23) 'as shown in the eighth p, and the metal circuit (2 3) Forming a welding pad (2 7) exposed outside the solder resist layer (2 6); plating the outer surface of the metal scatter sheet f Α, μ ±…, (1 0) with an anti-oxidant which can be nickel, etc. 19 1244183 Layer C 1 5), as shown in the eighth Q diagram; and a deep and heat sink (work 0) at a predetermined position of the dielectric build-up (20), and a wafer container (2) that can accommodate the wafer (2) 2), as shown in the eighth R diagram, when digging the groove, it can further penetrate into the heat sink (丄 〇) to form a sticky crystal groove (1 3), and the surface of the sticky crystal groove (1 3) An insulating layer (丄 4), which can be a black oxide layer, can be further deposited, as shown in the eighth s figure, to complete the manufacturing of the multi-dielectric layer structure substrate.
前述之製程步驟中，亦可於最上層介電層之雷射微孔 及其上表面完成鍍設導電金屬步驟之後，直接以影像移轉 手丰又於‘電金屬膜上钱刻出圖案化的金屬線路（圖未示） ，接續於介電積層及金屬線路上塗覆一圖案化防焊層，對 金屬線路顯露於防焊層外的焊墊上鍍設鎳金合金（MAu) 之助焊層，再對金屬散熱片外表面鍍設一可為鎳之抗氧化 層，以及對介電積層挖設晶片容槽等步驟。In the foregoing process steps, after the step of plating conductive metal is completed on the laser microholes on the uppermost dielectric layer and the upper surface thereof, the image is transferred directly to the mobile phone and the patterned pattern is engraved on the 'electric metal film'. A metal circuit (not shown) is coated with a patterned solder mask on the dielectric build-up layer and the metal circuit, and a nickel gold alloy (MAu) flux layer is plated on the pads of the metal circuit exposed outside the solder mask layer. Then, the outer surface of the metal heat sink is plated with an anti-oxidation layer that can be nickel, and the dielectric groove is used to dig a wafer container.
月询，丨电積層為二層介電層組構而成時，係刪除 介電層之製程步驟，並於完成第一介電層之雷射鑽孔 射微孔中鍍設金屬導體等製程步驟後，直接於第一介 ^壓合具導電金屬膜的第三介電層（即最上層介電層 雷射鑽孔、雷射微孔中鍍設金屬導體，接續於導電金 上形成圖案化的乾膜、鎮設助焊層、剝離乾膜、㈣ 案，的金屬線路、塗覆防焊層、於金屬散熱片外表面 抗氧化層，以及對介電積層挖設深及散熱片的曰片☆ 後續製程步驟，完成基板製編；若該介電：層： 以上介電層組構而成時，則反復進行上述第二介電層 20 1244183 步驟，使其具有多層 之製程步驟。 第二介電層，最後再進行第三介電層 ，前述製程步驟中，亦可於最上層介電積層（2 :雷射微( 2 4 )完成鍍設導電金屬步驟之後，直接以 〜像移轉手段於導電金屬膜上_出圖案化的金屬線路（ 圖未不），接績於介電積層及金屬線路上塗覆一圖案化 焊層，對金屬線路顯露於防焊層外的焊墊上㈣鎳金合金 JNl/AU)之助焊層，再接續對金屬散熱片外表面鍍設—抗 氧化層，以及對介電積層挖設晶片容槽等步驟。 ^別述用於製造具多層介電層之介電積層時，該第—、 第’丨電層（2la) (21b)之各雷射微孔（24a )(24b)鍍設出空心金屬導體（25a) (25c) 後，先於各金屬導體（25a) (25b)上以網印或$ 像移轉手&&導電金屬凸塊（圖未示），再進行上一層介Monthly inquiry. 丨 When the electrical build-up layer is composed of two dielectric layers, the process steps of deleting the dielectric layer are completed, and the processes such as plating metal conductors in the laser drilling micro-holes of the first dielectric layer are completed. After the step, a metal conductor is plated directly in the third dielectric layer (that is, the uppermost dielectric layer) with a conductive metal film on the first dielectric layer, that is, the laser micro-hole is plated, and then a pattern is formed on the conductive gold. Metallized dry film, ballasting flux layer, peeling dry film, pattern, metal circuit, coating solder mask, anti-oxidation layer on the outer surface of the metal heat sink, and the depth of the dielectric buildup and the heat sink. The film ☆ follow-up process steps to complete the substrate fabrication; if the dielectric: layer: above dielectric layer is assembled, repeat the above-mentioned second dielectric layer 20 1244183 step, so that it has multiple layers of process steps. The second dielectric layer, and finally a third dielectric layer. In the aforementioned process steps, the uppermost dielectric layer (2: laser micro (2 4)) can be used to directly plate the conductive metal after the step of Transfer means on the conductive metal film _ out of the patterned metal circuit (not shown) ), Apply a patterned solder layer on the dielectric build-up layer and the metal circuit, and apply the nickel-gold alloy JNl / AU) flux layer on the solder pads where the metal circuit is exposed outside the solder mask layer, and then connect the metal heat sink Outer surface plating—anti-oxidation layer, and excavation of wafer pockets for the dielectric build-up. ^ Specifically, when manufacturing dielectric build-ups with multiple dielectric layers, the first and second dielectric layers (2la ) Each of the laser micro holes (24a) (24b) of (21b) is plated with a hollow metal conductor (25a) (25c), and then the metal conductors (25a) (25b) are screen-printed or $ image-transferred. & & conductive metal bump (not shown)
電層的壓合、雷射鑽孔及對雷射微孔鍍設金屬導體連接= 電金屬凸塊。 V 根據前揭構裝基板之製程設計，將實現本發明之構裝 基板結構’使其在產業上可被據以實施，並達成預 用。 刀 Λ斤过本發明經由其創新的構裝基板結構與製程 "又计，確具有鬲度的產業價值，並可有效克服習用構裝基 板散熱性不佳以及訊號傳輸不良之$題，因此，本發明設 計符合發明專利要件，爰依法具文提出申請。 21 1244183 【圖式簡單說明】 (一）圖式部分 第-圖係本發明為單一介電層構造之基板實施例之平面 示意圖（代表圖）。 圖係第-圖所示之散熱片增設鰭片之實施例圖。 第二圖係本發明為多層介電層構造之基板實施例之平 示意圖。 第四圖係本發明盖你夕甘 + 卜 基板之其他貫施例（-）平面示意圖。 弟五圖係本發明基板之1 讽他貫轭例（二）平面示音 第六圖A〜N係本發明用於製 " 流程圖。肖於“具早-介電層之基板製造 第七圖齡#本發明用—層介電層之基板製造 第八™歎r—㈣介〜 (2 )晶片 (4 )導電金屬凸塊 (11)鰭片 (1 3 )黏晶凹槽 (1 5 )抗氧化層 (21)介電層 (2 lb)介電層 (210)導電金屬膜 二）元件代表符號 (1 )基板 (3)金屬線 (1〇)散熱片 (1 2 )黏晶區間 (14)絕緣層 (2 0 )介電積層 (2 1 a)介電層 (2 1 c)介電層 22 1244183 (2 1 1 )乾膜 (2 2 )晶片容槽 (2 4 )雷射微孔 (2 4 b)雷射微孔 (2 5 )金屬導體 (2 5 b)金屬導體 (2 6 )防焊層 (2 8 )助焊層 (291)導電金屬凸塊 (212)介電材 (2 3 )金屬線路 (2 4 a)雷射微孔 (2 4 c)雷射微孔 (2 5 a)金屬導體 (2 5 c)金屬導體 (2 7 )焊墊 (2 9 )金屬導熱體Lamination of electrical layers, laser drilling, and plating metal conductors on laser micro-holes = electrical metal bumps. V According to the process design of the previously-disclosed structured substrate, the structured substrate structure of the present invention will be realized so that it can be implemented in the industry and achieved pre-use. The knife through the invention through its innovative structure of the substrate structure and manufacturing process " Also, it has a high degree of industrial value, and can effectively overcome the problem of poor heat dissipation and poor signal transmission of conventional structure substrates, so The design of the present invention meets the requirements of the invention patent, and the application is filed according to the law. 21 1244183 [Brief description of the drawings] (I) Schematic part The figure-is a schematic plan view (representative drawing) of the embodiment of the substrate of the present invention having a single dielectric layer structure. The figure is a diagram of an embodiment in which fins are added to the heat sink shown in FIG. The second figure is a schematic plan view of an embodiment of a substrate having a multilayer dielectric layer structure according to the present invention. The fourth figure is a schematic plan view of another embodiment (-) of the cover plate of the present invention. The fifth figure is the first example of the substrate of the present invention, and the second is a plane sound. The sixth figure A ~ N is a flowchart of the present invention for making ". Xiao Yu "Manufacturing of a substrate with an early-dielectric layer. VII 图 龄 # The present invention uses a substrate with a dielectric layer to make the eighth ™ ㈣r-㈣ 介 ~ (2) wafer (4) conductive metal bumps (11 ) Fins (1 3) Sticky grooves (1 5) Anti-oxidation layer (21) Dielectric layer (2 lb) Dielectric layer (210) Conductive metal film 2) Element representative symbol (1) Substrate (3) Metal Line (10) heat sink (1 2) sticky crystal section (14) insulating layer (2 0) dielectric build-up (2 1 a) dielectric layer (2 1 c) dielectric layer 22 1244183 (2 1 1) dry Film (2 2) wafer container (2 4) laser micro hole (2 4 b) laser micro hole (2 5) metal conductor (2 5 b) metal conductor (2 6) solder mask (2 8) Solder layer (291) Conductive metal bump (212) Dielectric material (2 3) Metal circuit (2 4 a) Laser micro hole (2 4 c) Laser micro hole (2 5 a) Metal conductor (2 5 c ) Metal conductor (2 7) pad (2 9) metal heat conductor
23twenty three