TW200421576A - Package substrate having high heat dissipation performance and the process thereof - Google Patents

Abstract

A package substrate having high heat dissipation performance and the process thereof are provided. A stacked dielectric layer that is constructed by single or multiple dielectric layers is pressing-combined on the metal heat dissipation sheet. Then dig a chip containing trough that extends to the heat dissipation sheet in the stacked dielectric layer. Mount the chip on the trough to let the operation-generated heat directly conduct to the heat dissipation sheet. Besides, form micro holes on the stacked dielectric layer by laser drilling and deposit metal conductor in the holes. Guide the ground terminal of the metal circuits of the stacked dielectric layer to the heat dissipation sheet. Therefore, the heat generated by high frequency signal transmission of chip is conducted to the heat dissipation sheet to have excellent heat dissipation performance. On the other hand, the ground inductance is reduced by directly grounding the metal circuit ground terminal to the heat dissipation sheet through a metal conductor, and hence the grounding noise is reduced.

Description

200421576

[The technical field to which the invention belongs] The present invention relates to a mounting process with high heat dissipation, especially a carrier that provides a wafer structure as an external medium, and can work on the wafer. The generated high temperature and heat dissipation caused by high-frequency digital signal transmission provide a fast and effective way to dissipate heat, and the substrate structure and process design of the transmitted signal can be reduced. [Previous technology] The current research and development of electronic products is oriented towards the trend of thinness, shortness, precision, and lightweight. The electronic products, such as high-performance semiconductor components, need to have high heat dissipation performance. In addition, high-frequency digital transmission signals are also used for signal transmission. Direction of development. '' Among the known semiconductor structure mounting board components (such as: ebga, 邡 ,, lebga, ...), in order to make them have high heat dissipation, the structure substrate is mostly on the back The metal heat sink is adhered to provide the chip directly to the eighth middle, so that the heat generated during the operation of the chip is dissipated through the heat sink to prevent the component from overheating and affecting its performance or damage. However, with the arrangement of the heat sink, the Lishu semiconductor element can dissipate the heat generated by the wafer's operating% through the heat sink, but for the heat dissipation generated by the component signal transmission π kg, only the substrate with poor thermal conductivity can be used. The electrical layer is discharged, and cannot be directly conducted to the metal heat sink to dissipate quickly, resulting in insufficient heat dissipation function, so that the component still has a problem of high temperature during use. Also, 'the application of the current high-frequency digital signal transmission mode has increased. For 200421576, the high-frequency pass hole of the semiconductor element, the tiger's pass buckle, and the prevention of noise is an important problem in communication. a. ^ Achieving the prevention of miscellaneous floods. In addition to improving the design through high-frequency circuits, the structural substrates that provide external connection μ Λ should be able to reduce ground bounce. The structure of the mounting substrate is not

Effective grounding circuit design. When the Japanese film is transmitting signals, it is easy to have a grounding signal.

The occurrence of noise (ground bounce) (Za details), resulting in unstable signal transmission. [Summary of the Invention] • The main object of the present invention is to provide a structured substrate with high heat dissipation, a structure and a process for manufacturing the substrate structure, to overcome the heat dissipation property of the substrate for front exposure and provide applications. Chips used in high-frequency circuits have better groundability. In order to achieve the purpose of previous disclosure, the mounting substrate structure with heat dissipation function provided by the present invention is mainly formed by laminating a dielectric laminate on a metal heat sink, and the dielectric laminate can be a single-dielectric layer or a multilayer dielectric. It is electrically laminated, and a wafer container extending to the heat sink is provided thereon, so that the heat sink has a sticky crystal section exposed at the bottom of the wafer container to provide the wafer to be adhered thereto. The upper surface of the dielectric build-up is provided with a pattern. A metal circuit, i. A laser micro-hole extending from a predetermined ground signal end of the metal circuit to the heat sink is provided with a metal conductor to directly or in series with the metal conductor; == a metal thermal conductor disposed between the interlayers of the dielectric layer It is indirectly connected between the metal circuit and the heat sink. The upper surface of the dielectric build-up is additionally provided with a patterned solder mask layer covering the metal circuit, and the metal circuit is formed into a plurality of welding pads exposed outside the solder mask layer, forming a It can dissipate the heat generated by the work of the wafer and the heat loss generated by the high-frequency transmission of the wafer through the direct conduction to the heat sink, and can stabilize the signal transmission substrate 200421576. The process for manufacturing a substrate with high heat dissipation provided by the present invention mainly includes the steps of providing a conductive metal film dielectric layer on a metal heat sink by means of thermocompression bonding, and secondly by laser drilling on the dielectric layer. The laser microholes extending to the heat sink are plated with a conductive metal to form a metal conductor on the laser microholes of the dielectric layer, and then patterned by image transfer on the upper surface of the dielectric layer. The metal circuit is coated with a solder resist layer and a solder pad is formed, and then a deep and heat sink can be excavated into the dielectric build-up and a wafer container can be accommodated to complete the substrate. When the foregoing dielectric laminate is a combination of two or more dielectric layers, the dielectric lamination is performed on a heat sink with a predetermined number of dielectric layers, laser drilling, and plating in laser micro-holes. Conductive metal forming a metal conductor and other steps, and then forming a patterned metal circuit on the upper surface of the uppermost dielectric layer by image transfer, coating a solder resist layer, and digging a deep groove and a heat sink for the dielectric chip. . The structure design of the mounting substrate of the present invention is disclosed at the front. Its characteristics include at least: ',', and 1. It can improve heat dissipation. The mounting substrate designed by the user of the present invention can directly attach the chip to the metal for heat dissipation. On the chip, the M generated during the wafer's operation is directly transmitted to the metal heat sink to dissipate. In addition, the heat dissipation generated during the transmission of the wafer at high height can be passed through the metal conductor in the laser microhole through the metal line ground on the dielectric laminate. (And metal thermal conductive material) quickly and directly to the heat sink to diverge, which makes it have excellent heat dissipation performance. 2. Stable signal transmission and reduced noise: The present invention uses a wafer sinker 200421576 to be placed in a wafer receptacle of a substrate, shortening the length of the metal wire connecting the wafer and the substrate to reduce the signal transmission impedance, and using a dielectric layer to set a mine Shoot micro holes, and set metal conductors in the micro holes to directly connect the ground terminal of the metal line to the metal heat sink to ground, which can reduce the amount of ground inductance and reduce the generation of signal noise (ground bounce). It is also possible to use a conductive method in which only a metallic conductor (Solid Via) is provided in the laser microvia to further reduce stray signals due to the via. The substrate structure manufacturing process designed by the present invention can realize the structure of the substrate structure of the present invention, so as to make it possible to implement it in the industry and achieve the expected function of the previous disclosure. Γ embodiment] For a specific example of a mounting substrate structure with high heat dissipation properties according to the present invention, please refer to FIG. 1 for reference. The mounting substrate (work) is a dust-laminated dielectric layer on a metal heat sink (10). (20), the dielectric build-up layer (20) is provided with a wafer container (2 2) extending to a heat sink (丄 〇), and the heat sink (10) has a chip receiver (2 2) exposed. ), The sticky crystal interval (1 2) of the part is used to provide the wafer (2) adhered to the heat sink (1 0), and the upper surface of the dielectric build-up (20) is opposite to the outside of the wafer receiving groove (2 2). A patterned metal circuit (2 3) is provided, and a laser micro hole (2 4) extending from a predetermined ground signal end of the metal circuit (2 3) to a heat sink (work 0) is provided, and the laser micro hole ( 2 4) is provided with a metal conductor (2 5) connected between the metal circuit (2 3) and the heat sink (丄 〇), and the upper surface of the dielectric build-up layer (20) is provided with a cover for the metal circuit (2 3) ) On the patterned solder mask layer (2 6), and the metal circuit (2 200421576 3) has a plurality of solder pads (2 7) exposed outside the solder mask layer (2 6). The inner pads (2 7) adjacent to the wafer receptacle (2 2) in the middle provide the wafer (2) for electrical connection, and the pads (2 7) located away from the outer side of the wafer receptacle (2 2) provide conductive metal bumps. (4) It is fixed on it. In addition to the structure of the single dielectric layer shown in the first figure, the aforementioned dielectric laminated layer (20) can also be composed of a two-layer (including) dielectric layer 1) as shown in the third figure. In the embodiment in which the dielectric build-up layer (20) is a multilayer dielectric layer (21), please refer to the third figure, as shown in FIG. A patterned metal thermal conductor (29) is interposed between the interlayers of the layer (2 丄), and a metal circuit (⑴) is provided on the upper surface of the uppermost dielectric layer (21), and the uppermost dielectric layer (2 1) is disposed on the upper surface of the upper dielectric layer (2). The upper surface metal circuit (2 3) is provided with a laser micro-hole (2 4) at a position corresponding to the lower surface metal heat-conducting body (2 9), and a connection is provided in the laser micro-hole (2 4). The metal line (2 3) and the metal conductor (25) of the metal / heat conductor (29), and the lower dielectric layer (2 1) is provided with a thunder extending from the upper surface of the metal heat conductor (29) toward 20). The micro-hole (24), in the laser micro-hole (^), the gold connected between the metal thermal conductor (29) and the heat sink "10" = (25), which is between the uppermost dielectric layer (21) ) And the lower dielectric layer (2 1) The layer (2 steps) is provided with laser micro-holes at a predetermined position between the upper and lower metal thermal conductors (2 9), and the laser micro-holes (2 4) are separately processed in the ancient and the lower 4 layers. The metal conductor (25) of the body ()) 'If the dielectric multilayer (2㈡ is composed of the upper and lower dielectric layers (21), there is no 200421576 structure of the above-mentioned intermediate dielectric layer. 2) Laser micropores The solid body shown in (2 4) in gold and the three figures, or the solid layer shown in the dielectric layer (the conductor (25) can be the same as the hollow thin layer on the hole wall. The dielectric layer described above r〇 Electrodeposited layer (20) is a structure composed of two or more layers (2 1). ^ The injection micro-holes can correspond to the up and down mismatches, and hunt metal heat conductors (or As shown in the fourth and fifth figures, + ^ y J is connected, and the micro-holes (2 4) can be the respective lasers 9. ^, The lower corresponding shape, and the penetrations in the upper and lower laser micro-holes (2 4) are used. The core metal conductor (as shown in Figure 5-5) is directly connected, or a conductive metal bump 中 Γ ^ ^ r 0 λ Λ is set in the hollow metal conductor (2 5) of the second hole (2 4). Α 1 9 1) direct connection The upper layer of the metal conductor (2 4) of the laser beam (2 4). The cicada pads with the holes provided outside the dielectric layer (9) are as follows: (2) The top surface is exposed in the solder mask (26 solder layer, surface Plating-nickel-gold alloy (Ni / Au) assists: The metal wire (3) and the conductive metal bump (4) are connected to the pad (2 γ). 4; In other words, the The "α" sheet (1 0) is a dielectric laminated sheet (2 0), and is used to form a patterned Korean sheet (11), as shown in the second figure. Then sex. Surface two metal heat sink (1㈧ in its crystalline interval (⑴ 的 表 =:-insulating layer (not shown)), or, as shown in the first and third pictures: groove (Gongyuewen heat sheet, (1 0) Forming point crystals at the sticky crystal interval (1 2) " and overlaying-insulating the surface of the sticky crystal groove (1 3)

10 200421576 layer (1 4), the aforementioned insulating layer (1 4) may be a black oxide layer, the rhenium metal heat sink (10) may be a copper (Cu) sheet, and the outer surface thereof may be plated with nickel (Ni) ) Or other non-oxidizable metal anti-oxidation layer (1 5) ^ Different dielectric layers can be selected according to different electrical requirements, such as Gteck, FR4, FR5, BT, ... Frequency demand day inch 'can choose low dielectric constant materials, "change the thickness of the dielectric layer' to meet the needs of impedance matching. In the structure design of the mounting substrate previously disclosed in the present invention, during the mounting, the wafer (2) is adhered to the substrate (i) and is located on the political wafer (10) at the bottom P of the wafer container (2 2). ^ (丄 2), and another metal wire () is connected between the contacts on the day # (2) and the corresponding solder (2 7) on the substrate (1), and then the chip and the wiring area are filled with Adhesive sealing, and then a conductive metal bump (4) is provided on the substrate (1) peripheral welding t (2 7) to form a half body element. The semiconductor element is soldered downward with its conductive metal bump (4). External electrical connection on the circuit of the circuit board allows the semiconductor element to be controlled by the circuit board. The present invention has at least the above advantages by using the structure design of the mounting substrate, among which: ', can improve heat dissipation: the mounting substrate designed by the present invention can be used to directly attach the chip to the metal heat sink, so The heat generated by the chip can be directly transmitted to the metal heat sink to dissipate. In addition, the heat loss generated when the chip transmits high-frequency signals can be passed through the metal conductor in the laser #hole through the metal circuit ground terminal on the dielectric laminate ( And metal thermal conductor, etc.) quickly conduct to the heat sink 200421576 and diverge, making it have excellent heat dissipation performance. 2. Stable signal transmission and reduced noise: The structured substrate designed by the present invention uses the wafer to be sunk in the wafer container (2 2) of the substrate (i), which can shorten the connection between the wafer (2) and the substrate (2). ) Length of the metal wire (3) to reduce signal transmission impedance. In addition, the present invention uses a dielectric multilayer to set laser micro-holes, and a metal conductor is provided in the invention to directly connect the ground end of the metal line to the metal heat sink. Grounding makes it possible to reduce the amount of ground inductance, reduce the noise signal of the ground signal (ground bounce), and use the solid metal conductor (Solid Via) conduction method in the laser micro-hole to further reduce the conduction The holes produce stray signals. In order to complete the unveiling of the structured substrate structure, the present invention continues to design an innovative process for realizing the structure of the structured substrate. First, a structured substrate with a dielectric layer as a single dielectric layer is taken as an example. The manufacturing process includes the following steps: Metal heat sinks with high thermal conductivity, such as copper, such as Figure 6A, m. The top surface of the political heat sink (20) can be image-transferred to deposit or etch patterned fins (11), as shown in Figure 6B. As shown, or: the patterned fins are not provided on the 5H metal heat sink (1 0); a conductive metal film with an upper surface ( 21 G) (such as mi, etc.) of the dielectric layer (20) 'as shown in Figure 6c' wherein the heat sink (10) is provided with fins, which can be increased by the fins (11) and the dielectric layer ( 20): laser drilling means to form a laser micro-hole (2 4) from Beton to metal 敎 ΰ at a predetermined position of the dielectric layer (20). ), As shown in figure 200421576 6D; the laser micro-holes (24) of the dielectric multilayer (20) and their upper surfaces are plated with conductive gold such as copper In the step, as shown in the sixth E diagram, the laser micro-holes (2 4) are formed into a hollow or solid metal conductor (2 5), which is connected between the conductive metal film and the metal heat sink (10). In the embodiment, a method of forming a hollow metal conductor (2 5) is used in the laser micro-holes (2 4). After this step, the laser micro-holes (2 1 2) are filled with a dielectric material (2 1 2). 4), as shown in FIG. 6F; forming a patterned dry film (2 1 1) on the conductive metal film (2 1 0) by means of image transfer as shown in FIG. 6G; for the conductive metal film (2 1 〇) The exposed part of the patterned dry film (2 1 1) is plated with a nickel-gold alloy (Ni / Au) flux layer (2 8), as shown in the sixth figure; The dry film (2 1 1) 'on the conductive metal film (2 1 0) is as shown in the sixth figure I; the shirt image transfer means is applied to the conductive metal film (2 metalized circuit (23), such as the sixth As shown in the figure, the metal wire: (23) is connected to the metal conductor in the laser micro hole (24); a picture is coated on the "electrodeposition layer (20)" and the metal circuit (23)? 6), as shown in Figure 6K, and make the metal Circuit 3) forming a solder pad (2 7) exposed outside the solder resist layer (2 6); and the outer surface of the metal heat sink (i 〇) # 而 妙 执 一 可 也 # 'layer (!, 1 u J outer surface The anti-oxidation of nickel plating can be shown in Figure 6L; and, a deep and heat sink (work 13 200421576 0) can be dug at a predetermined position of the electrodeposition layer (20) and can accommodate a wafer chip groove ( 22), as shown in FIG. 6M, when the trench is digged, “step into the heat sink (丄 〇) β to form a sticky crystal groove (1 3), as shown in the sixth N, the adhesive The surface of the crystal groove (i 3) can be further deposited with an insulating layer (1 4), which can be a black oxide layer, to complete the fabrication of the structural substrate. In the foregoing process steps, after the step of plating the conductive metal on the laser micro-holes (24) of the dielectric build-up (20) and its upper surface, a pattern can be directly etched on the conductive metal film by image transfer means. A metalized circuit (not shown) is coated with a patterned solder mask on the dielectric build-up layer and the metal circuit, and a nickel-gold alloy (Ni / Au) is plated on the pads of the metal circuit exposed outside the solder mask. A soldering layer, plating an outer surface of the metal heat sink with an anti-oxidation layer that can be nickel, and digging a wafer container for the dielectric build-up. Regarding the application of the present invention to the manufacture of structural substrates with multiple dielectric layers constituting a dielectric build-up, taking a dielectric build-up consisting of three dielectric layers as an example, the manufacturing process includes the following steps: providing a metal heat sink with high thermal conductivity, As shown in Figure 78, the upper surface of the metal heat sink (10) can be deposited using image transfer (戍--engraved with a patterned Korean film ⑴), as shown in Figure 7B, or = The patterned fins; a first dielectric layer (21a) having a conductive metal film (21a) on its top surface is overlaid on the metal heat sink (10) by means of thermocompression bonding, such as the seventh C As shown in the figure: 〆: Laser drilling means forms laser micro-holes (24a) from Beton to metal heat sink (10) at predetermined positions of the first dielectric layer (2 1 a), such as 14 200421576 As shown in Figure D; the laser micro-holes (24a) of the -dielectric layer (2la) and the step of forming a conductive metal by bonding are known to make the laser micro-holes (can be hollow or solid metals' 4 $ Version and B are shown in the figure. They are connected between the conductive metal film (21〇a) and the metal heat sink (1〇). 24a) adopts the method of forming a hollow metal body (25a); the image transfer method is used to form the conductive metal film (2 〇a) on the first dielectric layer to form a patterned metal heat conductor (29a), as in Qiqi diagram: two = body (, 9a) connected to the laser micro hole (24a) = = combined means on the first dielectric layer (2la) a second layer with a conductive metal film (210b) on the top surface Dielectric layer (2, as shown in Figure 7G, the second dielectric layer (2lb), the first dielectric layer (21a) of the hollow metal conductor, 'true charge; belly, Zba') The laser drilling means forms a laser micro through the second dielectric layer (2ib penetrating to the metal thermal conductor (29b) as shown in the seventh figure; 24b) a laser micro to the second dielectric layer (2 lb) The hole (the surface is provided with a conductive metal plating step, such as the seventh one) and its upper hole (24b) form a hollow (or solid) = laser microb), and is connected to the conductive metal film (2 丄 〇c ) Belongs to the conductor (2 5 a (29a) ... above 15 200421576 the pressure of the electrical layer (21) (that is, the upper dielectric layer). (2 4 C) metal plating Volume Γ 125c, and other steps, such as filling the laser micropores (24c) with the seventh, eighth, seventh, seventh, and seventh maps (2 1 2) ... As shown in the figure, a patterned dry film is formed on the uppermost dielectric layer (2 I. 彡, — the metal film (210C) by means of image transfer) (as shown in the figure of conductive gold; 2 1 1), as shown in FIG. The seventh patterned dry film (2 1 1 flux layer (2 8), such as

The conductive metal film (2 1 0c) is exposed to the outside of) and is plated with a nickel-gold (Ni / Au) alloy as shown in the seventh P picture; the conductive metal film (2 丄 〇c) overlaid on the conductive metal film (2 丄 〇c) is peeled off. The dry film (2) 'is shown in the seventh Q figure; a patterned metal circuit (2 3) is engraved on the conductive metal film (2 丄 Q e) by means of image transfer, as shown in the seventh figure; ^ Apply a patterned solder mask (2 6) on the dielectric build-up layer (20) and the metal circuit (23), as shown in Figure 7s, and make the metal circuit (2 3) to be exposed The pad (2 7) outside the solder layer (2 6); ,,, The outer surface of the metal heat sink (1 0) is plated with an anti-oxidation layer (15), which can be nickel or other materials, such as the seventh as shown in the τ diagram; and a chip receiving groove (2 2) for digging deep and heat sinks (丄 〇) and accommodating the wafer (2) at a predetermined position of the dielectric laminate (20), as shown in the seventh u diagram It can be shown that when digging a groove, it can be further penetrated into the heat sink 1 (1 0), so as to form a crystal sticky groove ("), and the surface of the sticky crystal groove (1 3) can be black / black. Insulating layer of halogenated layer or other insulating material (1 4 16 200421576) As shown in the seventh V diagram, the manufacturing of the multi-dielectric layer structured substrate is completed. In the foregoing process steps, the conductive micro-holes can also be plated on the laser micro holes of the uppermost dielectric layer and the upper surface thereof. After the step, a patterned metal circuit (not shown) is etched directly on the conductive metal film by means of image transfer. 'Continuously apply a patterned solder mask on the dielectric build-up layer and the metal circuit to expose the metal circuit to the The solder pads outside the solder layer are plated with a nickel / gold alloy (Ni / Au) soldering layer, and then the outer surface of the metal heat sink is plated with an anti-oxidation layer that can be nickel, and the dielectric tank is used to excavate a wafer container. step. When the front dielectric layer is composed of two dielectric layers, the process steps of the second dielectric layer are deleted, and metal is plated in the laser drilling and laser micro holes of the first dielectric layer. After the process steps such as the conductor and forming a patterned metal heat conductor, the third dielectric layer (ie, the uppermost dielectric layer) with the conductive metal film, the laser drilling, and the laser are directly laminated on the first dielectric layer. A metal conductor is plated in the microvia, followed by forming a patterned dry film on the conductive metal film, plating a soldering layer, peeling the dry film, engraving the patterned metal circuit, coating a solder resist layer, and a metal heat sink The outer surface is plated with an anti-oxidation layer, and the subsequent process steps such as digging the dielectric build-up layer and the wafer tank of the heat sink are completed to complete the manufacture of the substrate; if the dielectric build-up is composed of three or more dielectric layers Then, the above-mentioned steps of manufacturing the first J-electric layer are repeatedly performed so that it has a plurality of second dielectric layers, and finally, the process steps of the third dielectric layer are performed. In the process steps described in the month, after the conductive metal plating step is completed in the laser micro-holes (2 4) of the dielectric laminate (20), the image can be directly transferred to the 4th and 4th square, and the V-metal film is engraved. Patterned metal circuit (not shown) 200421576, followed by coating a patterned solder mask on the dielectric build-up and the metal circuit, and plating nickel / gold alloy (Ni / Au) on the pads of the metal circuit exposed outside the solder mask. ), And then follow the steps of plating an anti-oxidation layer on the outer surface of the metal heat sink, and digging the chip cavity for the dielectric build-up. The fabrication of a structured substrate with a multi-layered dielectric layer and a dielectric build-up layer can also be completed by the following process steps, which include: Providing a metal heat sink with high thermal conductivity, as shown in Figure 8A, the metal heat sink The patterned fins (] _ JL) can be deposited or etched on the top surface of the wafer (10) by image transfer, as shown in Figure 8B, or the patterned fins may not be provided; Means: a first dielectric layer (21a) is overlaid on the metal heat sink (10), as shown in FIG. 8c; ...: a laser drilling method is scheduled in the first dielectric layer (2la) Laser micro-holes (24a) penetrating to the metal heat sink (10) are formed at the positions, as shown in FIG. 8D; a step of providing a conductive metal to the first dielectric layer, and a solid metal conductor (shown in FIG. 8E) ;

(2 1 a) of the laser micro-holes (2 4 a) are plated so that the laser micro-holes (2 4 a) form a hollow or 25a) connection metal heat sink (1〇), as described in Section 2. In this dielectric layer, l ^} as shown in Figure 8F; laser drilling is used to _ a dielectric layer to the first) 丨 pen layer (2 lb) corresponding to the first, hx a radio The laser micropores (2 4 a) of the micropores (2, as shown in the eighth G diagram; L 2 18 421576 ^ The laser micropores (24b) of the second dielectric layer (2 lb) are plated with conductive metal As shown in the eighth figure, the laser micro-holes (2 4 b) are formed into a hollow or solid metal conductor (2 5b) and connected to the first dielectric layer (2 1 a). (2 5 a); a third η electric layer (2 1) (that is, the uppermost dielectric layer) with a conductive metal film (2 1 0 c) on the top surface of the lamination, and a laser drill is applied thereon Hole-to-laser microvias (2 4 c) are plated with metal conductors (25c) connected to the second dielectric layer (2 1 :) metal conductors (25b), such as the eighth I, eighth J, eighth κ picture; _ Then patterned on the conductive metal film (210C) of the uppermost dielectric layer (2 4 c) by image transfer The dry film (211) is shown in Figure 88. The conductive metal film (2 1 0c) is exposed outside the patterned dry film (2 1 1). Flux layer (2 8), as shown in the eighth M diagram;

Peeling and covering the conductive metal film), as shown in the eighth N diagram;

A patterned metal circuit (2 3 #, dagger J j) is etched on the dry film (211) on the conductive metal electric rabbit film (2 10 c) by means of image transfer, as shown in FIG. 80 ; A patterned solder mask (2 6) is coated on the dielectric build-up layer (20), and the metal lines (2 3) are formed to be exposed to the protection 7); the surface and the metal lines (2 3) are coated as shown in the eighth P diagram The outer surface of the gold solder layer (2 6) (2 pairs of metal heat sinks (10) is plated with an anti-oxidation layer that can be nickel or the like. 19 200421576 Chemical layer (1 5) As shown in the Q picture; and the position of the dielectric multilayer (2Q) is set to 0) and the chip Γ can be accommodated. 9, from the state ", month (1

As shown in the figure, when digging a groove, it is also possible to insert a heat sink (丄 〇 to form a sticky crystal groove (i 3)), and the sticky crystal groove (" ' It can be an insulating layer (1 4) of a black oxide ^ emulsifiable layer, as shown in the eighth s, and complete the fabrication of the multi-dielectric layer structured substrate. In the process steps of Figure 2, it can also be the uppermost layer. After the laser on the dielectric layer and the upper surface finish the step of setting the conductive metal, the patterned metal circuit is directly etched on the conductive metal film by shadowing (not shown, followed by coating on the dielectric layer and metal circuit— 金属The non-metal circuit of the solder mask layer is exposed on the pads outside the solder mask layer, and a nickel-gold alloy (N 丨 / Au), a flux layer is plated, and then the outer surface of the metal heat sink is mined—it can be the oxidation resistance of nickel. Layers, and the steps of digging a wafer cavity for a dielectric build-up.

When the front dielectric layer is composed of a two-layer dielectric layer, the process steps of the second dielectric layer are deleted, and metal is plated in the laser drilling of the first dielectric layer and two micro-holes. After the conductor and other process steps, a third dielectric layer (ie, the uppermost dielectric layer) with a conductive metal film, a laser drill hole, and a laser micro-hole are plated with a metal conductor directly on the first dielectric layer. Continue to form a patterned dry film on the conductive metal film, bond a soldering layer, peel off the dry film, cut a patterned metal circuit, coat a solder mask, and bond an anti-oxidation layer on the outer surface of the metal heat sink. And subsequent process steps such as digging the dielectric build-up layer and the heat sink's chip tank to complete the manufacture of the substrate; if the dielectric build-up layer is composed of three or more dielectric layers, the above-mentioned second dielectric layer is repeated. 20 steps of the fabrication of the electrical layer. The θth -..., and finally the third process of the third dielectric layer is performed. The laser micro μΠ ::! of ^ can be directly transferred after the image transfer means of the uppermost dielectric build-up (2ic), and the conductive metal step is set. (Not shown) ,: patterned metal circuits (solder layer, etc.) are etched on the radio and television metal film (for metal: apply a patterned resist on the dielectric build-up layer and the metal circuit (ni / au: = exposed in the solder resist layer) A gold alloy oxide layer is recorded on the outer welding pad, and the steps of setting the clock on the outer surface of the metal heat sink-resistance two and digging the wafer container for the dielectric layer are performed. The foregoing is used for manufacturing a multilayer dielectric layer. When the dielectric is laminated, the laser micro-holes (24a y 24b) of the first-second dielectric layer [91, / 2 1 a} (21b) are plated with a hollow metal conductor (25a) (after 2 5 c ') First, conductive metal bumps (not shown) are set on each metal conductor (2 5 a) (2 5 b) by screen printing or private image transfer, and then the upper-layer dielectric layer is laminated and lasered. Drilling and plating laser conductors with metal conductors and electric metal bumps. Based on the front substrate structure, the process design of the substrate assembly with 0 is used to implement the invention It is structured so that it can be implemented in the industry and achieve the desired results.

In summary, the invention has a high industrial value through its innovative structure of the substrate structure and manufacturing process, and can effectively overcome the problems of poor heat dissipation and poor signal transmission of conventional substrates. Therefore, the present invention The invention design meets the requirements of the invention patent, and the application is filed according to the law.

21 200421576 [Brief description of the diagram] (I) Schematic part The first diagram is the schematic diagram of the present invention. The month is a plane (representative diagram) of a single embodiment of a substrate structure with a single electric layer structure.苐 一 图 是 一 图 所 + # 私 U Example of adding fins to a pound of non-government hot film. The third figure is the invention of a multi-layered substrate ^ Λ ^ ^ Xi Jin; 丨 cladding structure of the substrate implementation Example diagram. Plane The fourth figure is a schematic plan view of another embodiment (-) of the substrate of the present invention. The fifth diagram is a schematic plan view of another embodiment (2) of the substrate of the present invention. The six figures A to N are flowcharts of the present invention for manufacturing a substrate with a single-dielectric layer.

The seventh figure is Lin Zhuan] is a substrate manufacturing process for manufacturing a substrate with multiple dielectric layers in this month. The eighth figure _! The present invention is a flow chart of the present invention for manufacturing a substrate with multiple dielectric layers. Soil (two) component representative symbols (1) substrate (3) metal wire (10) heat sink (1 2) sticky crystal section (1 4) insulating layer (2 0) dielectric build-up layer (2 1 a) dielectric layer ( 2 1 c) Dielectric layer (4) Conductive metal bump (11) Fin (1 3) Sticky crystal groove (15) Anti-oxidation layer (21) Dielectric layer (2 1 b) Dielectric layer (210) Conductive metal film

22 200421576 (2 1 1) dry film (2 2) wafer container (2 4) laser micro hole (2 4 b) laser micro hole (2 5) metal conductor (2 5 b) metal conductor (2 6) Solder mask layer (2 8) Flux layer (291) Conductive metal bump (2 1 2) Dielectric material (2 3) Metal circuit (2 4 a) Laser microvia (2 4c) Laser microvia ( 2 5 a) metal conductor (2 5 c) metal conductor (2 7) pad (2 9) metal heat conductor

twenty three

Claims (1)

200421576 Scope of patent application ...: 乂,., Read ._: .... 1. A structure substrate structure with high heat dissipation, which is used as a chip carrier and as a medium for external signal transmission. It is composed of a laminated dielectric layer on a metal heat sink. The dielectric layer is provided with a wafer container extending to the heat sink. The heat sink has a sticky crystal section exposed at the bottom of the wafer container to provide the wafer to adhere to it. A patterned metal circuit is provided on the upper surface of the dielectric build-up layer, and a laser micro-hole extending from a predetermined ground signal end of the metal circuit to a heat sink is provided. The laser micro-hole has a metal conductor connected to the metal circuit and the heat sink. In between, the upper surface of the dielectric buildup layer is additionally provided with a patterned solder mask layer covering the metal circuit, and the metal circuit is formed into a plurality of solder pads exposed outside the solder mask layer, forming a heat that can be generated by the work of the wafer. And the high-frequency signal of the chip ^ The heat dissipation generated by the transmission is directly transmitted to the heat sink to dissipate, and it can stabilize the signal transmission. 2. The structure substrate structure with high heat dissipation as described in item (1) of the scope of patent application, wherein the dielectric build-up layer is composed of a single dielectric layer. 3. The mounting substrate structure with high heat dissipation as described in item 1 of the scope of the patent application, wherein the dielectric build-up layer is composed of two or more dielectric layers. The upper surface of the upper dielectric layer, the lowermost dielectric layer is located on the heat sink, the upper and lower dielectric layers are provided with laser micro-holes, and metal conductors are provided in the laser micro-holes, and the metal conductor of the uppermost dielectric layer is connected to the metal The metal ground conductor of the bottom dielectric layer is connected to the heat sink, and a patterned metal heat conductor is connected between the upper and lower dielectric layers to connect the upper and lower metal conductors to the upper metal line. The signal end is connected to the lower heat sink. 24 200421576 4. The substrate structure with high heat dissipation as described in item 1 of the scope of the patent application, where the dielectric multilayer is composed of two or more dielectric layers, and the metal circuit is placed at the top. The upper surface of the upper dielectric layer, the lower dielectric layer is located on the heat sink, and the upper and lower dielectric layers are provided with laser conductors with metal conductors. The metal conductors of the upper dielectric layer are connected to the metal line and the ground terminal is the lowest dielectric layer. The metal conductor of the electrical layer is connected to the heat sink, and the upper and lower laser micro-holes correspond to each other. The metal conductors provided in the laser micro-holes are directly connected to the upper and lower layers to connect the predetermined ground signal end of the upper metal line to the lower heat sink. The structure of the mounting substrate structure with high heat dissipation as described in item 1 of the scope of the patent application, wherein the dielectric multilayer is composed of two or more dielectric layers, and the metal circuit is provided at the uppermost layer of the dielectric. The upper surface of the layer, the lowest dielectric layer is located on the heat sink, and the upper and lower dielectric layers are provided with laser micro-holes with metal conductors. The metal conductors of the uppermost dielectric layer are connected to the predetermined ground signal terminal of the metal line. The metal conductor of the lowest dielectric layer is connected to the heat sink, and the upper and lower laser micro holes correspond to each other. The metal conductors in the upper and lower laser micro holes are connected by conductive metal bumps, and are used to connect the upper metal line to a predetermined ground signal. End is connected to the heat sink under Φ. 6. The mounting substrate structure with high heat dissipation as described in item 2, 3, 4 or 5 of the scope of patent application, wherein the metal conductor provided in the dielectric micro-laser is a solid body. 7. The structural substrate structure with south heat dissipation as described in the scope of application for patents No. 2, 3, 4 or 5, wherein the metal conductor provided in the laser micro-hole of the dielectric layer is attached to the hollow thin wall Floor. 25 200421576 Ancient 8. As described in the patent application scope No. 2, 3, 4 or 5 of the structure of the substrate structure with thermal insulation, the # on the top surface of the dielectric build-up exposed solder mask surface Plating a flux layer. 'Ancient 9. As described in the patent application scope Nos. 2, 3, and "5, the structural substrate structure having the same thermal properties, the metal heat sink in the middle of the dielectric layer to form patterned fins. 10. The substrate structure with high heat dissipation performance as described in Chinese Patent Application No. 2, 3, 4 or 5, wherein the metal heat sink forms a sticky crystal groove at the sticky crystal interval. In addition, the range of profitability is 甲 0… π 丄 U, which is only "I; ~ is a government substrate structure with Gao Leyao ', in which the surface of the sticky crystal groove is covered with an insulating layer. 1 2. The substrate structure with high heat dissipation as described in item 2, 3, 4 or 5 of the patent scope of the patent, wherein the surface of the metal powder is covered with an insulating layer. ， Yue Yunian said that the range of the 2nd-4th and 5th of the patent scope of the Rongqing patent is that the structure of the substrate with the structure of "month = nature" where the metal heat sink is a copper (cu) sheet, and the outer surface is plated Set up a metal anti-oxidation layer. 14. A structural substrate with high heat dissipation properties includes: a step of overlaying a dielectric build-up layer on a metal heat sink with a pressing method; and a laser drilling method provided on the dielectric build-up layer to extend toward the heat sink The dielectric micro-layered laser micro-holes are plated with conductive metal to form a metal conductor and connected to a heat sink; the laser micro-holes 26 200421576 are used to form a patterned metal circuit on the dielectric multi-layered layer by image transfer to connect the laser A metal conductor in a microhole; coating a patterned solder mask on the η electrode build-up layer and the metal circuit, and forming the metal circuit to form a solder pad exposed outside the solder mask layer; and digging deep at a predetermined position of the dielectric layer And a wafer receiving groove capable of accommodating a wafer with a heat sink and completing the manufacture of the structured substrate. 15. The process for mounting a substrate with high heat dissipation as described in item i 4 of the scope of the patent application, wherein the dielectric build-up uses a single dielectric layer with a conductive metal film on its upper surface and is laminated to the heat dissipation After the conductive metal step is performed on the chip, the laser drill hole, and the laser microhole, the image transfer method is used to punch out a patterned metal circuit on the conductive metal film to connect the metal conductor in the laser microhole. 16. The process of mounting a substrate with high heat dissipation as described in item i 4 of the scope of the patent application, wherein the dielectric build-up layer is sequentially and repeatedly laminated with two or more dielectric layers, and each laminated After a dielectric layer, successively apply; the steps of laser drilling and laser micro-hole plating of conductive metal, and then the next dielectric layer pressing, laser drilling and laser micro-hole plating of conductive metal steps, After the metal conductors in the laser micro-holes in the upper dielectric layer are connected, a patterned metal circuit is formed on the upper dielectric layer 2 using image transfer to connect the metal conductors in the laser micro-holes. 17. As described in item i 6 of the scope of the patent application, the fabrication process of a substrate with high dispersiveness, '丨 the dielectric layer above the lowest dielectric layer is drilled during laser drilling,' which makes it lightning. The micro-holes correspond to the laser body of the lower dielectric layer; the micro-holes 'let the laser micro-holes be used when the conductive metal is laid in the mine'. The conductor metal is directly connected to the lower metal conductor 27 200421576. 18. According to the process of mounting a substrate with high heat dissipation as described in item 16 of the scope of the patent application, the dielectric layer above the lower dielectric layer is combined with the lower dielectric layer # 'before the When metal bumps are planted on the metal conductor of the lower dielectric layer, and then the upper dielectric layer is pressed and the upper dielectric layer is laser-drilled, the laser micro-holes correspond to the laser micro-layers of the lower dielectric layer. Holes allow laser microholes to be used to mine conductive metal, so that the metal conductors in the radioactive microholes are connected to the underlying metal conductor through the conductive metal bumps. 9. As described in claim 6 of the patent application for a substrate manufacturing process with high heat dissipation, the dielectric layer below the uppermost dielectric layer uses a dielectric layer with a conductive metal film on it. After the dielectric layer is laminated with a conductive metal by lamination, laser drilling, and laser micro-holes, a patterned metal thermal conductor is etched by means of image transfer. The metal thermal conductor is connected to the upper and lower laser micro-holes to conduct electricity. Metal room. 20. The process of mounting a substrate with high heat dissipation as described in item 17, 7, 8 or 8g of the scope of patent application, wherein the uppermost dielectric layer is a dielectric layer having a conductive metal film on the upper surface, After the steps of the uppermost layer of dielectric lamination, laser drilling and laser micro-hole plating of conductive metal, the patterned metal circuit connecting the metal conductors inside the laser micro-holes is etched by means of shirt image transfer, and then Wafer steps of applying a patterned solder mask and digging deep and heat sinks of the dielectric build-up layer are performed. 2 1. According to the process of framing substrate with high heat dissipation described in item 20 of the scope of the patent application, in which the patterned metal circuit is etched on the conductive metal film of the uppermost dielectric layer, the image is transferred first. Means to form a dry film on the conductive metal film with a dielectric layer 28 200421576 layer + A and take a Q accumulation; dry the conductive metal film with a patterned metal film and peel off the coating The dry film is set on the conductive Z-type film, and then patterned metal lines are engraved on the conductive metal film by means of image transfer. 22. As described in the item 2q of the patent application, a process for fabricating a substrate with a high heat dissipation spoon, wherein the upper dielectric layer and the metal circuit are coated with a patterned solder mask layer at r% of the screen, and then supplied with lightning. The main grasp ^ ^ & electric shovel ^ and a metal soldering layer is plated on the pad 0 2 3, as described in the patent application scope of the 4th process with a high heat dissipation structure of the substrate manufacturing process' 丨 the metal heat dissipation Before laminating the dielectric laminated layer, a patterned fin is formed on the upper surface by means of image transfer. 24. As described in item 24 of the scope of the patent application, a process for mounting a substrate with high heat dissipation is used. A copper plate is used as a metal heat sink, and the dielectric metal laminate is laminated on the 4 metal heat sink, and outside it. An anti-oxidation layer is plated on the surface. 25. The process of mounting a substrate with high heat dissipation as described in item 14 of the patent scope of Shenjing, wherein after the deep layer and the heat sink's wafer container are dug into the dielectric laminate, the heat sink can be exposed on the wafer An insulating layer is deposited in the sticky crystal interval at the bottom of the tank. 26. The process of mounting a substrate with high heat dissipation as described in item 14 of the scope of patent application, wherein when the dielectric buildup is dug deep and the heat sink is sunk, the heat sink is further penetrated, so that It forms a sticky crystal groove to form a sticky crystal groove. 27. The process of mounting a substrate with high heat dissipation performance as described in item 26 of the patent application No. 26, 21,621,576, in which an insulating layer is deposited on the surface of the sticky crystal groove.