TWI244137B - Stacking structure of semiconductor chip and its manufacturing method - Google Patents

Stacking structure of semiconductor chip and its manufacturing method Download PDF

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Publication number
TWI244137B
TWI244137B TW093138402A TW93138402A TWI244137B TW I244137 B TWI244137 B TW I244137B TW 093138402 A TW093138402 A TW 093138402A TW 93138402 A TW93138402 A TW 93138402A TW I244137 B TWI244137 B TW I244137B
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Taiwan
Prior art keywords
layer
wafer
substrate
electrodes
wires
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TW093138402A
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Chinese (zh)
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TW200620462A (en
Inventor
Tzung-Shian Shin
Yi-Bi Huang
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Kingpak Tech Inc
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Publication of TW200620462A publication Critical patent/TW200620462A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Element Separation (AREA)
  • Wire Bonding (AREA)

Abstract

This invention relates to stacking structure of semiconductor chip and its manufacturing method, which includes one substrate, which is equipped with one upper surface and one lower surface and a plurality of 1st electrodes are formed onto the lower surface; one protruding edge layer, which is a frame structure and stacked onto the upper surface of the substrate to form one concave with the substrate, and equipped with a plurality of 2nd electrodes and a plurality of 3rd electrodes; one lower-layer chip, which is installed onto the upper surface of the substrate and located within the concave; a plurality of 1st conducting wires which are wire-bonded from the 1st electrodes on the protruding edge layer to the lower-layer chip; a plurality of insulating elements installed onto the lower-layer chip; one upper-layer chip installed onto the above of the lower-layer chip and held by the plurality of insulating elements; a plurality of 2nd conducting wires, which are wire-bonded from the upper-layer chip to the 3rd electrodes on the protruding edge layer; and one encapsulant layer, which is used to encapsulate the upper-layer chip and the lower-layer chip.

Description

1244137 、發明說明（1) L發明所屬之技術領域】 特別本俾發#明為一種半導體晶片之堆疊構造及其製造方法， r〜係指一種製造上更為便刺B女4， 衣 【先箭社，1 更引及有效降低堆疊之尺寸者。 〜夜術】 言斥求在科技的領域，各項科技產品皆以輕、薄、短小為复 合產：因A ’對於積體電路的體積係越小越理想，更可符 列式：t Ϊ求。：以往積體電路即使體積再小，亦只能並 達η體電rf置數量有效地提昇，是以，欲使產品 2輕：:#、短小之訴求，將有其困難之處。 薄、4- ^ =干個積體電路予以疊合使用，可達到輕、 體#二二=二v，然而，若干個積體電路疊合時，上層積 藉：千曰下層積體電路之導線，以致將影響到下層 積體電路之訊號傳遞。 口 θ「尽 々杠i以使f，厂種積體電路堆疊構造，請參閱圖一，其 ^ 土反、—下層晶片1 2、一上層晶片14、複數個 ，線丨6及:隔離層1δ。下層晶片12係設於基板1〇上，上層 曰曰片1 4係耩由離層i 8疊合於下層晶片i 2上方，使下層晶 片12與上層晶片14形成一適當之間距2〇，如是，複數個導 線1 6即可電連接於下層晶# j 2邊緣，使上層晶片工4疊合於 下層晶片12上枯，不致於壓損複數個導線16。 而，此種結構在製造上必須先製作隔離層1 8，再將 其黏著於了層日曰片丄2上，而後再將上層晶片i 4黏著於隔離 層1 8上’是以’其製造程序較為複雜，生產成本較高，且1244137, Description of the invention (1) Technical field to which the invention belongs] In particular, the present invention is a stack structure of a semiconductor wafer and a method for manufacturing the same. Arrow Club, 1 is even more effective in reducing stack size. ~ Night Technique】 In the field of science and technology, all technology products are light, thin, and short as a composite product: because A 'is smaller for integrated circuits, the smaller the volume is, the more ideal it is, and it is more compatible with the formula: t Ϊ begging. : In the past, even if the size of the integrated circuit is small, it can only effectively increase the number of η bulk electric rf units. Therefore, if you want to make the product 2 lighter: #, short, there will be difficulties. Thin, 4- ^ = dry integrated circuits can be stacked and used to achieve light, body # 二 二 = 二 v, however, when several integrated circuits are stacked, the upper layer is borrowed: Wire, which will affect the signal transmission of the underlying integrated circuit. Mouth θ "make the best use of i to make f, the factory integrated circuit stack structure, please refer to Figure 1, its ^ soil,-lower wafer 1 2, an upper wafer 14, a plurality of lines, 6 and: isolation layer 1δ. The lower wafer 12 is set on the substrate 10, and the upper wafer 14 is superimposed on the lower wafer i 2 by the separation layer i 8 so that the lower wafer 12 and the upper wafer 14 form a proper distance 20. If so, the plurality of wires 16 can be electrically connected to the edge of the lower-layer crystal #j 2 so that the upper-layer wafermaker 4 is superposed on the lower-layer wafer 12 so as not to crush the plurality of wires 16. However, this structure is being manufactured. First, an isolation layer 18 must be made, and then it is adhered to the layer 2 and then the upper chip i 4 is adhered to the isolation layer 18. The manufacturing process is more complicated, and the production cost is High, and

第5頁 1244137Page 5 1244137

五、發明說明（2) 封裝體積亦較大。 有鑑於此，本創作人乃本於精益求精、創 神，戮力於影像感測器封裝之研發，而發明出大破之精 晶片之堆受構造及其製造方法，使其製造上 月半V體 效降低堆疊之尺寸者。 馬便利及有 【發明内容】 晶片之堆疊 以達到降低 晶片之堆疊 以達到輕薄 本發明之主要目的，在於提供一種半導體 構造及其製造方法，其具有製造便利之功效， 生產成本之目的。 本發明之另一目的，在於提供一種半導體 構造及其製造方法，其具有縮小體積之功效， 短小之目的。 本發明半導體晶片之堆疊構 =一基板，其設有—上表面及一下表面，該下表面形成= 複數個第一電極。一凸緣層為_框型結構，係疊合於节其 ，之上表面，而與該基板形成有一凹槽，該凸緣層設有/二 數個第二電極及複數個第三電極。一下層晶片，其係設 於邊基板之上表面上，並位於該凹槽内。複數條第一 :由：緣層上之第-電極打線至該下層晶片上。複數個隔 、吧凡件係設置於該下層晶月上。一上層晶Θ係設置於該 層晶片上方，被該複數個隔絕元件支撐住。複數條第二 線係由該上層晶另打線至該凸緣層之第三電極上。一封膠 層係今以將該上層晶片及該下層晶包覆住0 夕 發明之上述及其他目的、優點和特色由以下較佳實5. Description of the invention (2) The package volume is also large. In view of this, the creator is based on the pursuit of excellence and creation, devoting himself to the research and development of image sensor packaging, and invented the broken structure of the fine chip and its manufacturing method, making it a semi-V body last month. Reduce the size of the stack. Convenience and convenience of the invention [Summary of the invention] Stacking of wafers to reduce stacking of wafers to achieve lightness and thinness The main object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which have the advantages of convenient manufacturing and production costs. Another object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which have the effect of reducing the volume and the purpose of being short. The stacked structure of the semiconductor wafer according to the present invention is a substrate provided with an upper surface and a lower surface, and the lower surface forms a plurality of first electrodes. A flange layer is a frame structure, which is superimposed on the upper surface of the joint layer, and a groove is formed with the substrate. The flange layer is provided with two or more second electrodes and a plurality of third electrodes. The lower layer wafer is disposed on the upper surface of the side substrate and is located in the groove. The plurality of first lines are: from the first electrode on the edge layer to the lower layer wafer. A plurality of partitions and bars are arranged on the lower crystal moon. An upper layer crystal Θ is disposed above the wafer of the layer and is supported by the plurality of isolation elements. The plurality of second wires are separately wired from the upper layer crystal to the third electrode of the flange layer. A glue layer is used to cover the upper wafer and the lower crystal. The above and other objects, advantages, and characteristics of the invention are better as follows.

第6頁 1244137 五、發明說明（3) 施例之詳細說明中並參考圖式當可更加明白，其中·· 【實施方式】 請參閱圖2，為本發明半導體晶片之堆疊構造，其包 括有一基板30、一凸緣層32、一下層晶片34、複數條第一 導線3 6、複數個隔絕元件3 8、一上層晶片4 0、複數條第二 導線4 2及一封膠層4 4 ··其中 基板30設有一上表面4 6及一下表面48，下表面4 8形成 有複數個第一電極5 0。 凸緣層3 2為一框型結構，係疊合於基板3 0之上表面4 6 上，而與基板3 0形成有一凹槽52，凸緣層32上方設有複數 個第二電極5 4及複數個第三電極5 6。 下層晶片3 4係設置於基板3 0之上表面4 6上，並位於凹 槽5 2内。 複數條第一導線3 6係由凸緣層3 2上之第一電極5 0打線 至下層晶片3 4上，是以，第一導線3 6與下層片3 4接觸之 處，可得到較小之線弧。 複數個隔絕元件3 8在本實施例中為金球，其係設置於 下層晶片3 4之周邊。 上層晶片4 0係設置於下層晶片3 4上方，被複數個隔絕 元件3 8支撐住。 複數條第二導線4 2係由上層晶片4 0打線至凸緣層3 2之 第三電極上5 6上。及 封膠層4 4係用以將上層晶片4 0及下層晶片3 4包覆住。 本發明半導體晶片之堆疊構造之製造方法，請參閱圖Page 6 of 1244137 V. Description of the invention (3) It will be more clearly understood in the detailed description of the embodiments and with reference to the drawings, in which. [Embodiment] Please refer to FIG. 2, which is a stack structure of a semiconductor wafer according to the present invention. Substrate 30, a flange layer 32, a lower wafer 34, a plurality of first wires 36, a plurality of isolation elements 3 8, an upper wafer 40, a plurality of second wires 4 2 and an adhesive layer 4 4 · The substrate 30 is provided with an upper surface 46 and a lower surface 48, and the lower surface 48 is formed with a plurality of first electrodes 50. The flange layer 32 is a frame structure, which is superimposed on the upper surface 4 6 of the substrate 30, and a groove 52 is formed with the substrate 30. A plurality of second electrodes 5 4 are provided above the flange layer 32. And a plurality of third electrodes 5 6. The lower wafer 3 4 is disposed on the upper surface 4 6 of the substrate 30 and is located in the recess 5 2. The plurality of first conductive wires 36 are routed from the first electrode 50 on the flange layer 32 to the lower wafer 34, so that the contact between the first conductive wire 36 and the lower wafer 34 can be smaller. The line arc. The plurality of isolation elements 38 are gold balls in this embodiment, which are arranged around the lower wafer 34. The upper wafer 40 is disposed above the lower wafer 34, and is supported by a plurality of isolation elements 38. The plurality of second wires 4 2 are wired from the upper wafer 40 to the third electrodes 56 of the flange layer 32. And the sealant layer 4 4 is used to cover the upper wafer 40 and the lower wafer 34. Manufacturing method of stacked structure of semiconductor wafer according to the present invention, please refer to the drawings

12441371244137

P、發明說明（4) 2,首先提供一基板30,其設有—上表面46及一下表面 48，下表面48形成有複數個第_電極5〇。 的供一凸緣層3 2，其為一框型結構，係疊合於基板3 〇 之上表面4 6上，而與基板3 〇形成有一凹槽5 2，凸緣層3 2上 方$又有複數個第一電極5 4及複數個第三電極$ 6。 提供一下層晶片3 4，其係設置於基板3 〇之上表面4 6 上，並位於凹槽5 2内。 係由凸緣層3 2上之第一電 ’第一導線3 6與下層片34 本實施例中為金球，其係 提供複數條第一導線3 6，其 極5 0打線至下層晶片3 4上，是以 接觸之處’可得到較小之線弧。 提供複數個隔絕元件3 8，在 設置於下層晶片3 4之周邊。 數個 緣層 電極 導線 再者 降低 凸緣 可提 仗识_ 隔絕元 提供複 3 2之第 是以， 5〇打線 3 6可得 。本發 封裝之 層3 2上 高封裝 在較佳 上層晶片 件3 8支撐 數條第二 二電極上 本發明將 至下層晶 到較小之 明以隔絕 尺寸。另 ’可降低 之良率。 貫施例之 住。 導線4 2 ’其係由上層 5 6上。及 曰 複數條第一導線3 6由 片34，因此’位於下 線弧’使得封裴體積 元件38取代傳統的間 ，將第一導線3 6及第 導線之長度’使其製 片3 4上方，被複 晶片4 0打線至凸 凸緣層3 2之第一 層晶片3 4位置之 可有效的縮小。 隔器，亦可有效 二導線4 2打線於 造上較便利，亦 具體實施例僅為 詳細說明中所提出之P. Description of the invention (4) 2. First, a substrate 30 is provided, which is provided with an upper surface 46 and a lower surface 48, and the lower surface 48 is formed with a plurality of first electrodes 50. The flange layer 32 is a frame structure, which is superimposed on the upper surface 46 of the substrate 30, and a groove 5 2 is formed with the substrate 30, and the flange layer 32 is over There are a plurality of first electrodes 5 4 and a plurality of third electrodes $ 6. A lower layer wafer 3 4 is provided, which is disposed on the upper surface 4 6 of the substrate 30 and is located in the groove 5 2. The first electric wires 36 and the lower layer sheet 34 on the flange layer 32 are gold balls in this embodiment, which are provided with a plurality of first wires 36, and the poles 50 thereof are wired to the lower layer chip 3. On the 4th, the smaller arc can be obtained based on the contact point. A plurality of isolation elements 38 are provided on the periphery of the lower wafer 34. Several edge-layer electrode wires and lowering the flanges can also provide a better understanding of the _ insulation element to provide the first 3 of the complex, 50 lines of 36 can be obtained. The layer 32 of the present package is high-encapsulated, and is preferably supported on the upper-layer wafer 38. Several second and second electrodes are supported by the present invention. Another can reduce the yield. Live through the example. The wires 4 2 'are formed on the upper layer 56. Since the plurality of first conductive wires 36 are formed by the sheet 34, "located in the lower arc" causes the sealing volume element 38 to replace the conventional space, and the first conductive wire 36 and the length of the second conductive wire are made above the sheet 34. The coated wafer 40 can be effectively shrunk to the position of the first layer wafer 34 of the convex flange layer 32. The spacer can also be effective. The two wires 4 and 2 are more convenient to make, and the specific embodiments are only provided in the detailed description.

12441371244137

1244137 圖式簡單說明 【圖式簡早說明】 圖1為習知半導體晶片之堆疊構造之剖視圖。 圖2為本發明半導體晶片之堆疊構造之剖視圖。 [ 主 要 元件符號說明 圖 號 說 明 習 知 圖 號 基 板 10 下層晶片 12 上 層 晶片 14 導 線 16 隔離層 18 間 距 20， 本 發 明 圖號 基 板 30 凸緣層 32 下 層 晶 片 34 第 .— 導 線 36 隔絕元件 38 上 層 晶 片 40 第 二 導 線 42 封膠層 44 上 表 面 46 下 表 面 48 第一電極 50 凹 槽 52 第 二 電 極 54 第三電.極 561244137 Brief description of the drawings [Simplified description of the drawings] FIG. 1 is a cross-sectional view of a stack structure of a conventional semiconductor wafer. FIG. 2 is a cross-sectional view of a stacked structure of a semiconductor wafer according to the present invention. [Description of main component symbols, drawing number description, conventional drawing number, substrate 10, lower wafer 12, upper wafer 14, lead 16, isolation layer 18, pitch 20, the drawing substrate of the present invention, 30, flange layer, 32, lower wafer, 34th. — Lead, 36, insulation element, 38, upper layer Wafer 40 Second wire 42 Sealant 44 Upper surface 46 Lower surface 48 First electrode 50 Groove 52 Second electrode 54 Third electrode 56

第10頁Page 10

Claims (1)

1244137 六、申請專利範圍 1. 一種半導體晶片之堆疊構造，其包括有： 一基板，其設有一上表面及一下表面，該下表面形成 有複數個第一電極； 一凸緣層，其為一框型結構，係疊合於該基板之上表 面，而與該基板形成有一凹槽，該凸緣層設有複數個第二 電極及複數個第三電極； 一下層晶片，其係設置於該基板之上表面上，並位於 該凹槽内； 複數條第一導線，其係由凸緣層上之第一電極打線至 該下層晶片上； 複數個隔絕元件，其係設置於該下層晶片上； 一上層晶片，其係設置於該下層晶片上方，被該複數 個隔絕元件支撐住； 複數條第二導線，其係由該上層晶片打線至該凸緣層 之第三電極上；及 一封膠層，其係用以將該上層晶片及該下層晶片包覆 住。 2. 如申請專利範圍第1項所述之半導體晶片之堆$構造’ 其中該複數個隔絕元件為金球。 3. —種半導體晶片之堆疊構造之製造方法，其包括下列步 驟： 提供一基板，其設有一上表面及一下表面，該下表面 形成有複數個第一電極； 提供一凸緣層，其為一框型結構，係疊合於該基板之1244137 VI. Scope of patent application 1. A stacked structure of a semiconductor wafer, comprising: a substrate provided with an upper surface and a lower surface, the lower surface being formed with a plurality of first electrodes; a flange layer, which is a The frame structure is superposed on the upper surface of the substrate, and a groove is formed with the substrate. The flange layer is provided with a plurality of second electrodes and a plurality of third electrodes. The lower layer wafer is provided on the substrate. The upper surface of the substrate is located in the groove; a plurality of first wires are wired from the first electrode on the flange layer to the lower wafer; a plurality of isolation elements are provided on the lower wafer An upper layer wafer, which is disposed above the lower layer wafer and is supported by the plurality of isolation elements; a plurality of second wires, which are wired from the upper layer wafer to the third electrode of the flange layer; and one An adhesive layer is used to cover the upper wafer and the lower wafer. 2. The stack structure of a semiconductor wafer as described in item 1 of the scope of the patent application, wherein the plurality of isolation elements are gold balls. 3. A method for manufacturing a stacked structure of a semiconductor wafer, comprising the following steps: providing a substrate provided with an upper surface and a lower surface, the lower surface being formed with a plurality of first electrodes; providing a flange layer, which is A frame structure superimposed on the substrate 第11頁 1244137 六、申請專利範圍 上表面，而與該基板形成有一凹槽，該凸緣層設有複數個 第二電極及複數個第三電極； 提供一下層晶片，其係設置於該基板之上表面上，並 位於該凹槽内； 提供複數條第一導線，其係由凸緣層上之第一電極打 線至該下層晶片上； 複數個隔絕元件，其係設置於該下層晶片上； 一上層晶片，其係設置於該下層晶片上方，被該複數 個隔絕元件支撐住； 複數條第二導線，其係由該上層晶片打線至該凸緣層 之第三電極上；及 一封膠層，其係用以將該上層晶片及該下層晶包覆 住。 4.如申請專利範圍第1項所述之半導體晶片之堆疊構造之 製造方法，其中該複數個隔絕元件為金球。Page 11 1244137 6. The upper surface of the patent application, and a groove is formed with the substrate, the flange layer is provided with a plurality of second electrodes and a plurality of third electrodes; a lower layer wafer is provided, which is arranged on the substrate On the upper surface and located in the groove; providing a plurality of first wires, which are wired by the first electrode on the flange layer to the lower wafer; a plurality of isolation elements, which are arranged on the lower wafer An upper layer wafer, which is disposed above the lower layer wafer and is supported by the plurality of isolation elements; a plurality of second wires, which are wired from the upper layer wafer to the third electrode of the flange layer; and one An adhesive layer is used to cover the upper wafer and the lower crystal. 4. The method for manufacturing a stacked structure of a semiconductor wafer according to item 1 of the scope of the patent application, wherein the plurality of isolation elements are gold balls. 第12頁Page 12
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