J242269 狄、發明說明： 【發明所屬之技術領域】 本=係關於-種半導體積體電路之覆晶（mpchip) 裝結構與方法。 仏之可減少空間的覆晶封 【先前技術】 最新^導體積體電路(IC)的產品中，多層封裝為其中一 取所之製程之一，豆句合 10 ,, Β 八ι 3 .擴大1c晶粒之電極間距，豆中 10此晶粒包含後層封裝之電路；俘噌Λ 八 外部之應力；提供一適當之執c封裝内部與 熱量；以及形成—電性内部連二IC:專f由晶粒發散之 能、與可靠度。 個封衣日日粒的總成本、性 15密封Γ:;ΐ的:分為兩類:密封式封裝與非 一真空密二特定與外界環 :口㈣封裝並採用高效能應用。換言二： 用非密封式封裝封裝時，其並非 曰曰粒利 2。^式封裝較非密封_製造成本高裝： /、在些特殊應用中使用，例如旦彡傍成 、^ 器。然而，近來先進之密 ζ感測器或壓力感測 其使用範圍與性能。由於一般傳:產品已擴大 處理，故«封裝具有高成本效益。$ ;自動批次 1242269 近來發展之1C晶粒封裝為球狀閘陣列（Ball Grid Array， BGA)封裝，其可用於陶瓷封裝與塑膠封裝，並影響不同形 式之之内部封裝結構。BGA封裝利用複數個焊接球或凸塊 作為1C晶粒與其他微電子元件間之電性、機械、或熱之内 5部連結。此焊接凸塊提供1C晶粒固定於電路板上，並使晶 粒電路圖與電路板上之導電圖樣產生電性上之内部連接。 BGA技術包含在接合技術之下，此接合技術廣泛定義為 C4(Controlled Collapse Chip Connection)或覆晶技術。 覆晶技術可用於各種不同形式之電路板接合，其包含 10陶瓷基材、印刷線路板、可撓式電路、與矽基材。焊接凸 塊一般位於覆晶之面積陣列（Area Array)之導電性接合墊 (bond pad)上，導電性接合墊係與覆晶上之電路圖在電性上 内部相連接。因在覆晶之微電路中一般會執行各種功能， 故相對地需要眾多之焊接凸塊。通常覆晶之各邊尺寸約在 15 13mm間，造成焊接凸塊沿覆晶之週緣擁塞。因此，覆晶之 導電圖樣由各種個別之導體組成，此導體通常之間距=約 等於或小於0.1 mm。 圖1顯示為一般傳統之覆晶26，其包含一焊接凸塊 H)，其直接焊接於凸塊接墊14之連續上表面，此凸塊㈣ 20 14通常為-方形結構如㈣所示，並且由保護心部分覆 蓋，此保護層12可為SiN或Si〇2。在保護層此―圓形接 塾開口 13與凸塊接墊14相接觸，焊接凸塊⑽由此接塾開 口"延伸至凸塊接塾14。而凸塊接墊14被覆晶故介電層 15 (如氧化層）所包圍。 曰 1242269 另外圖1還顯示凸塊接墊丨4與上導電層丨6電性接觸， 此上導電層16藉由絕緣層18與下導電層22分隔。導電層16 與22藉由在絕緣層18延伸貫穿之導電通孔2〇使其互相在電 性相連。不同之絕緣層丨8與導電層22係依照半導體製程之 5傳統方式依序沈積於矽晶粒基材24上。 在焊接凸塊10形成於覆晶26之後，晶粒26即反轉（亦 所謂覆晶），此時焊接凸塊1〇隨即接合於基材28 (如印刷 電路板PCB上）之電性端點上。如圖1B所示，一般覆晶％ 上提供一連串行列之焊接凸塊丨〇。通常在覆晶26之行列間 10會有空乏區間11存在於相鄰之焊接凸塊1〇間，此乃由於製 造晶粒之積體電路結構或其他之考量所致。 在知接凸塊10接合於PCB基材28後，覆晶26將接受一 連串之測試，例如：凸塊剪力測試與晶片剪力（die shear test) 榀測，在此測試下為施予一剪應力於覆晶26上，以測定在 15復日日26與接合pCB基材28間之電性連接點的機械整备程 度。覆晶26亦會接受溫度檢測，在此檢測下覆晶％一般會 達到150〇C之溫度。然而，無引線晶片承載（乙^⑽chip Camer，LCC)封裝-般使用於影像感測器巾，如電荷搞合 =件（Charge Coupled Device，CCD)或互補式金屬氧化半 20 V 體（Complementary Metal Oxide Semiconductor，CMOS) 影像感測器。 y電荷耦合元件（CCD)影像感測器為一可將光學圖樣或 影像轉換為電荷圖樣或電子影像之電子S件。CCD包含數 感光單元此感光單元具有修正、儲存、與傳輸電荷至 1242269 另一感光單元之能；/7。功Μ a , 計之材料€#。# 、m會影響影像感測器設 =:單元代表一畫素。半導體技術- ::規則支配晝素之行列結構與矩陣結構，並由位於二 邊緣之一或多個輪屮访士即 、曰粒 + 1 ^ 修正由CCD傳出之訊號。-電 =像猎由-系列之脈衝獲得，此脈衝在另—脈衝傳輸至 =放ί器傳輸後依行列順序傳輸-畫素之電荷，此時輸 輸出訊號以偵測或揭取。仏路以一適當之形式傳輸 10 15 ^補式金屬氧化半導體影像感測器操作電遂低於電 元件(CCD)影像感測器，其為減少電量損耗利於攜 — c刪主動式晝素感測單元本身具有暫存之放大 益、、可獨立做讀寫動作。—般使用之畫素感測單元 四個電晶體與一光感單元。此畫素感測單元具輸 =將光感測器與—具電容之浮擴散⑽atmgdiffusi(J) 品，介於a擴散與電源供應之重置間極（耽t抑⑷· 一共汲極組態電晶體（source_follower transistor)係將讀出 線電容暫存於浮擴散中；以及一列選擇閘極，以連接主素 感測單元至讀出線。所有行連接之畫素均與一共同感測放 大器相接。 20 &相較於CCD影像感測器，CMOS影像感測器除具有低 耗月b外，由於其去_與結晶特性，通常設計較為簡單。故 其λ计谷易小型化並具有較少之支撐電路需求。 一傳統之無引線晶片承載封裝30如圖1C所示。此封裝 3〇 一般使用於CCD或CMOS影像感測器之IC晶粒，其包含 !242269 1明覆蓋玻璃層32’其具有—支擇層35。—防反射塗覆 "於復盍玻璃32與支揮層35之間。-多層基材36包含-:、堡狀結構4 2其上提供一影像感測器晶片3 8。上部鉛4 〇由 勹=38延伸而出並與底部鉛44電性上相連接，此底部鉛料 5 ^復於基材％之底部與側邊。而透明覆蓋玻璃32利於將光 傳送至影像感測器晶片38。 Ί線aa片承載封裝3G—般具有之厚度Μ為2mm。使 …、引線晶片承载封裝3〇於影像感測器之封裝⑽時需要相 ^大空間。而在許多狀況下，過大之影像感測器造成了 1〇 :::晶片承載封裝3〇之天生限制。因此，在影像感測器 哀上，亟需一種新穎並經改良之封裝結構與方法。 【發明内容】 15 本發明之主要目 測為之封裝結構。 的係在提供一種新穎的用於影像感 種新穎的用於影像感 種新穎的球狀閘陣列 本發明之另一目的係在提供一 測器之封裝結構，俾能節省空間。 本發明之另一目的係在提供一 之影像感測器封裝結構。 20 目的係在提供一 本發明之另一 測器之封裝方法。 種新穎之封裝影像感 裝結構與 1242269 本發明之再—日M y 以封襄影像感測器。、 供—種球狀間陣列之方法 έ士構，1 =目的係在提供—種影像感測器之封裝 5 、.。構其可有效減少封裝後之厚度。 為達成上述目的，本發 之封裝結構，其包含、改良之影像感測器 合墊#，^ 离基材，一位於玻璃基材上之接 接合i/所部覆晶接合塾與外部接合塾。透過 材，此視固，使影像感測器晶粒朝向玻璃基 材此反轉之影像感㈣晶_ 10 接於玻璃基材上之覆曰技人拙 η安·^非知接凸塊連 ^ Βθ σ墊。位在接合墊層上之外部接 合塾利用焊接球，與印刷電路板之接合塾對應接合。 本發明之影像感測器封裝結構其特徵在於具有比傳 統封裝更高之空間利用率，在傳統之影像感測器封裝一般 15 使用無引線晶片承載封裝。本發明之影像感測器封裝結構 整體之厚度約為800〜i 4〇〇μηι，而無引線晶片承載封裂之她 厚度約在2誦。故影像感測器元件相較於傳統之ccd或 參 CMOS影像感測器封裝結構可減少建構之尺寸。 本發明更進-步針對封裝影像感測器之方法。此方法 包含提供-玻璃基材；提供一接合塾層，其上具有多個内 20部覆晶接合墊與外部球狀閘陣列（BGA)接合墊，該接合墊 層位於該玻璃基材上；提供一焊接或非焊接凸塊於一影像 感測器晶粒之接合墊上，並相對應於接合墊層之内部覆晶 接合墊上；接合此反轉之影像感測器晶粒於該接合墊層之 11 1242269 該覆晶接合墊上；提供-BGA焊接球於該BGA接合塾；以 及接合一印刷電路板於該BGA焊接球上。 【實施方式】 5 纟發明係關於一封裝影像感測器1C晶粒之結構與方 法。此結構為一覆晶球狀閘陣列封裝結構，其特徵在於具 有比傳統影像感測器封裝結構更高之空間利用率。故影像 感測器元件相較於傳統之器封裝結構可減少建構之尺寸。 此封裝結構適用於CCD影像感測器或CM〇s#像感測器、。 钃 ίο 圖2D與2E係根據本發明之完整的影像感測器封裝結 構50。封裝結構50包含一玻璃基材52，其上具有一接合墊 層59此接白墊層59包含一聚亞醯胺加卜丨如知ρι)膠帶之 薄膜層54,並利用黏貼方式黏著於玻璃基材52。如圖犯所 示，此玻璃基材之基材厚度53一般約在牝叫㈤至⑼叫⑺之 間，而薄膜層54之膜厚55約為·”多個内部覆晶接合墊 56與外部球狀閘陣列（BGA)接合塾58位在薄膜層M之上表 面。並在必要時，每一内部覆晶接合墊56係與外部球狀閘 鲁 陣列（BGA)接合墊58利用薄膜層54之導電圖樣使兩者電性 上相接。 …一反轉之CCD或CM0S影像感測器1C晶粒60係先形成 複數個内部凸塊62，再接合於每一内部覆晶接合塾％。内 部凸塊62可為烊接凸塊，其可由錫、錯、或錫錯混合物焊 接形成，；或者為-非桿接凸塊，其可為金凸塊、或由阳才-料I设V電孟屬等之複合凸塊利用異方性導電膠或非導電 12 1242269 膠接合於内部覆晶接合墊56，一般來說，非焊接凸塊搭配 異方性導電膠或非導電膠較適合於CMOS影像感測1C晶 粒。而接合於每一外部球狀閘陣列（BGA)接合墊58之外部 焊接球70—般具有與内部焊接凸塊62相同之組成。如圖2D 5 所示，此1C晶粒60之厚度61 —般約在250μιη。此1C晶粒60 具有一光接收面60a朝向玻璃基材52之薄膜視窗57 (如圖 2B所示），此薄膜視窗57位於接合墊層59之中央。故此影 像感測器1C晶粒60透過玻璃基材52之薄膜視窗57以接收光 影像72。一 PCB基材66藉由其上相對應之接合墊68與外部 10 焊接球70接合。此PCB基材66包含一外部電路以在必要時 傳輸由影像感測器1C晶粒60所接收之光影像72，並傳輸輸 出訊號以作適當的偵測或擷取。一介於接合墊層59與1C晶 粒60之未填滿材料64其覆蓋於内部覆晶接合墊56與焊接凸 塊62上。 15 請參考圖2A-2E，首先於圖2A中，接合墊層59—般為 方形結構，其通常包含一聚亞醯胺（polyimide PI)膠帶之薄 膜層54，以便於黏著至透明基材52上。薄膜視窗57—般為 方形結構，並由接合墊層59之中央延伸。多個外部接合墊 58 —般沿接合墊層59之四個外部邊緣排列為行列。多個内 20 部接合墊56 —般沿薄膜視窗57之對邊排列為行列，其與外 部接合墊58之行列平行延伸。而接合墊層59通常利用聚亞 醯胺（polyimide PI)膠帶黏貼於玻璃基材52之上方表面 52a，故玻璃基材52可在黏貼合墊層59前，再包含額外之前 處理，例如在玻璃基材5 2上更可包含其他材料層，例如塗 13 1242269 覆防反射層、或去紅外線層等，以增強影像感測器ic晶粒 60所接收之光影像72或其他效能。 如圖2C所示，在接合墊層59形成於玻璃基材52上後， 一具有内部凸塊62 (例如錫、鉛、或複合凸塊）之影像感 5 測器1C晶粒60反轉並連接至相對應之每一内部接合墊56上 產生電性接觸。故1C晶粒60之光接受面60a透過薄膜視窗57 朝向玻璃基材52之上表面52a。其中内部凸塊62之形狀並非 受限於如圖2所示之圓球形，例如其為複合凸塊時，可為立 方體、圓錐體、圓柱體等。而一般焊接凸塊使用於CCD影 10 像感測器之1C晶粒，而非焊接凸塊用於CMOS影像感測器 之1C晶粒。 如圖2D所示，一介於接合墊層59與1C晶粒60之未填滿 材料64其覆蓋於每一内部焊接凸塊62上。未填滿材料64保 護内部接合墊56與内部焊接凸塊62防止其受到灰塵、水氣 15 或其他污染，以增強介於内部接合墊56與1C晶粒60之電性 連接可靠度。未填滿材料64可為任意適當之材料包含環氧 樹脂之小型填充料以增強散熱。此外，在1C晶粒60與接合 墊層59之間，可再包含一透光性材料於間隙區63中，以降 低其間光訊號之反射震盪雜訊。J242269 D. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a mpchip mounting structure and method for a semiconductor integrated circuit. The chip-on-chip package that can reduce the space [prior technology] Among the latest ^ volumetric circuit (IC) products, multi-layer packaging is one of the processes adopted, Douhe 10, Β ιι 3. Enlarge The electrode spacing of 1c die, 10 in the bean contains the circuit of the rear package; captures the external stress of the package; provides a proper implementation of the package and heat inside the package; and the formation of the electrical internal connection IC: f The energy and reliability of the divergence from the grain. The total cost and performance of each coating day and day. 15 Seals Γ :; ΐ: are divided into two categories: sealed packaging and non-vacuum-tight two specific and external rings: mouth-to-mouth packaging and high-performance applications. In other words: When packaged in a non-hermetic package, it is not a grain of grain2. ^ Package is more non-hermetic _ manufacturing cost is higher: /, used in some special applications, such as 彡 彡 成, ^ ^. Recently, however, the range and performance of advanced dense zeta sensors or pressure sensors has been increasing. As the general story: the product has been expanded, the «package is cost-effective. $; Auto batch 1242269 The recently developed 1C die package is a Ball Grid Array (BGA) package, which can be used for ceramic and plastic packages, and affects different types of internal packaging structures. The BGA package uses a plurality of solder balls or bumps as the electrical, mechanical, or thermal connection between the 1C die and other microelectronic components. This solder bump provides 1C die to be fixed on the circuit board, and makes the chip circuit diagram and the conductive pattern on the circuit board to be electrically connected internally. BGA technology is included under the bonding technology, which is widely defined as C4 (Controlled Collapse Chip Connection) or flip-chip technology. The flip-chip technology can be used for various forms of circuit board bonding, including 10 ceramic substrates, printed circuit boards, flexible circuits, and silicon substrates. The solder bumps are generally located on conductive bond pads of the flip chip area array. The conductive bonding pads are electrically connected internally to the circuit diagram on the flip chip. Since various functions are generally performed in flip-chip microcircuits, a relatively large number of solder bumps are required. Usually the size of each side of the flip chip is between 15 and 13 mm, which causes the solder bumps to congest along the periphery of the flip chip. Therefore, the flip-chip conductive pattern is composed of various individual conductors, and the distance between these conductors is usually equal to or less than 0.1 mm. FIG. 1 shows a conventional conventional flip chip 26, which includes a solder bump H), which is directly welded to the continuous upper surface of the bump pad 14. The bump ㈣ 20 14 is usually a square structure as shown in ㈣. It is also partially covered by a protective heart. The protective layer 12 may be SiN or SiO 2. In the protective layer, the circular connector opening 13 is in contact with the bump pad 14, and the solder bump ⑽ extends from this connector opening to the bump connector 14. The bump pads 14 are surrounded by a crystal-on-dielectric layer 15 (such as an oxide layer). 1242269 In addition, FIG. 1 also shows that the bump pads 4 and 4 are in electrical contact with the upper conductive layer 6. The upper conductive layer 16 is separated from the lower conductive layer 22 by the insulating layer 18. The conductive layers 16 and 22 are electrically connected to each other by a conductive via 20 extending through the insulating layer 18. The different insulating layers 丨 8 and conductive layers 22 are sequentially deposited on the silicon die substrate 24 according to the traditional method of the semiconductor process. After the solder bump 10 is formed on the flip chip 26, the die 26 is reversed (also referred to as flip chip). At this time, the solder bump 10 is then bonded to the electrical end of the substrate 28 (such as on a printed circuit board PCB). Point. As shown in FIG. 1B, a series of solder bumps are generally provided on the flip chip. Usually there are empty sections 11 between the rows and columns of the flip chip 26 between the adjacent solder bumps 10, which is due to the integrated circuit structure of the die or other considerations. After knowing that the bump 10 is bonded to the PCB substrate 28, the flip chip 26 will undergo a series of tests, such as a bump shear test and a die shear test. In this test, a Shear stress was applied to the flip chip 26 to determine the mechanical preparation of the electrical connection point between the 15th day and the 26th and the bonded pCB substrate 28. The flip chip 26 will also undergo a temperature test. Under this test, the flip chip% will generally reach a temperature of 150 ° C. However, leadless chip carrier (LCC) packages-generally used in image sensor towels, such as Charge Coupled Device (CCD) or complementary metal oxide half 20 V body (Complementary Metal Oxide Semiconductor (CMOS) image sensor. A charge-coupled device (CCD) image sensor is an electronic S-piece that converts an optical pattern or image into a charge pattern or electronic image. CCD contains a number of photosensitive units. This photosensitive unit has the ability to correct, store, and transfer charge to another 1242269 photosensitive unit; / 7. Work M a, Calculated materials. # And m will affect the image sensor setting =: unit represents a pixel. Semiconductor technology-:: Rule governs the structure and matrix structure of the day element, and the signal from the CCD is corrected by one or more rounds of interviewers who are located on the two edges. -Electricity = like hunting is obtained by the series of pulses. This pulse is transmitted in the order of rows and columns after the transmission of another pulse to the amplifier. At this time, the output signal is detected or retrieved. Kushiro transmits 10 15 ^ complementary metal oxide semiconductor image sensors in an appropriate form. The operating power is lower than that of electrical element (CCD) image sensors, which is beneficial to reduce power consumption. The measurement unit itself has temporary amplification benefits, and can independently read and write. -General-purpose pixel sensing unit Four transistors and a light sensing unit. This pixel sensing unit has a light sensor and a floating diffusion with capacitance ⑽atmgdiffusi (J), which is between a diffusion and reset of the power supply. The transistor (source_follower transistor) temporarily stores the read line capacitance in the floating diffusion; and a column selects the gate to connect the main pixel sensing unit to the read line. All pixels connected in a row are connected to a common sense amplifier. 20 & Compared with CCD image sensor, CMOS image sensor has low power consumption b, and its design is usually simpler due to its de- and crystallization characteristics. Therefore, its lambda meter valley is easy to miniaturize and Has less support circuit requirements. A traditional leadless wafer carrier package 30 is shown in Figure 1C. This package 30 is generally used in the IC die of a CCD or CMOS image sensor, which contains! 242269 1 cover glass The layer 32 'has-a selective layer 35.-an anti-reflection coating "between the plexiglass 32 and the branched layer 35.-the multilayer substrate 36 comprises-, a fortified structure 4 2 providing an image thereon Sensor chip 3 8. The upper lead 4 〇 extends from 勹 = 38 and is electrically connected to the bottom lead 44 The upper lead is connected to the bottom, and the bottom lead material is 5% of the bottom and the sides of the substrate. The transparent cover glass 32 facilitates the transmission of light to the image sensor chip 38. The aa wire chip package 3G—a thickness generally M is 2mm. A large space is required for the lead chip carrying package 30 to be packaged with the image sensor. In many cases, an oversized image sensor causes a 10 ::: chip carrying package The inherent limitation of 30. Therefore, on the image sensor, a new and improved packaging structure and method are urgently needed. [Summary of the Invention] 15 The main visual inspection of the present invention is the packaging structure. The purpose is to provide a novel Another object of the present invention is to provide a package structure of a tester, which can save space. Another object of the present invention is to provide a The image sensor package structure. 20 The purpose is to provide a method for packaging another sensor of the present invention. A novel packaged image sensor structure and the 1242269 re-invention of the present invention-Japan's My to seal the image sensor ., For the method of providing a spherical array, the purpose is to provide a package of an image sensor 5... It can effectively reduce the thickness of the package. In order to achieve the above purpose, the package of the present invention Structure, which includes and improves the image sensor combination pad #, ^ away from the substrate, a joint on the glass substrate / chip-on-chip joint 所 and external joint 塾. Through the material, this vision is fixed, so that The image sensor crystals with the image sensor grains facing the glass substrate are reversed. 10 The cover is attached to the glass substrate. ^ Ann non-connected bumps ^ θ θ θ pad. It is located at the joint The external joints on the cushion layer are connected to the joints of the printed circuit board using solder balls. The image sensor package structure of the present invention is characterized by having a higher space utilization rate than a conventional package. In the conventional image sensor package, a leadless chip is usually used to carry the package. The overall thickness of the packaging structure of the image sensor of the present invention is about 800 to 400 μm, and the thickness of the leadless chip carrying the seal is about 2 μm. Therefore, compared with the traditional ccd or CMOS image sensor package structure, the image sensor element can reduce the construction size. The present invention further aims at a method for packaging an image sensor. This method includes providing a glass substrate; providing a bonding pad layer having a plurality of inner 20 flip-chip bonding pads and external ball gate array (BGA) bonding pads, the bonding pad layer is located on the glass substrate; Provide a soldered or non-welded bump on a bonding pad of an image sensor die, and correspond to an internal flip-chip bonding pad corresponding to the bonding pad layer; bond the inverted image sensor die to the bonding pad layer 11 1242269 on the flip-chip bonding pad; providing a -BGA solder ball on the BGA bonding pad; and bonding a printed circuit board on the BGA solder ball. [Embodiment] The 5th invention relates to the structure and method of a packaged image sensor 1C die. This structure is a flip-chip spherical gate array package structure, which is characterized by a higher space utilization rate than a conventional image sensor package structure. Therefore, compared with the traditional device packaging structure, the image sensor element can reduce the construction size. This package structure is suitable for CCD image sensor or CM〇s # image sensor.钃 ο Figures 2D and 2E are complete image sensor package structures 50 according to the present invention. The packaging structure 50 includes a glass substrate 52 having a bonding pad layer 59 thereon, and the white pad layer 59 includes a film layer 54 of a polyurethane gauze tape, and is adhered to the glass by an adhesive method. Substrate 52. As shown in the figure, the substrate thickness 53 of this glass substrate is generally between howling and howling, and the film thickness 55 of the thin-film layer 54 is about · "multiple internal flip-chip bonding pads 56 and external Ball gate array (BGA) bonding pads 58 are located on the surface of thin film layer M. When necessary, each internal flip-chip bonding pad 56 is connected to the outer ball gate array (BGA) bonding pad 58 using a thin film layer 54 The conductive pattern connects the two electrically.… A reversed CCD or CM0S image sensor 1C die 60 is formed with a plurality of internal bumps 62 and then bonded to each internal flip-chip bond 塾%. The inner bump 62 may be a bump bump, which may be formed by welding of tin, tin, or a mixture of tin bumps; or a non-rod bump, which may be a gold bump, or may be formed by a positive electrode. The compound bumps of Dianmeng etc. are bonded to the internal flip-chip bonding pad 56 using anisotropic conductive adhesive or non-conductive 12 1242269 glue. Generally speaking, non-welding bumps with anisotropic conductive adhesive or non-conductive adhesive The CMOS image senses the 1C die. The external solder balls 70—typically bonded to each external ball-gate array (BGA) bonding pad 58—are generally It has the same composition as the internal welding bump 62. As shown in FIG. 2D5, the thickness 61 of the 1C die 60 is generally about 250 μm. The 1C die 60 has a film with a light receiving surface 60a facing the glass substrate 52 Window 57 (as shown in FIG. 2B), the thin film window 57 is located in the center of the bonding pad layer 59. Therefore, the image sensor 1C die 60 passes through the thin film window 57 of the glass substrate 52 to receive the light image 72. A PCB substrate 66 is bonded to the external 10 solder ball 70 by a corresponding bonding pad 68 thereon. The PCB substrate 66 includes an external circuit to transmit the light image 72 received by the image sensor 1C die 60 when necessary, and The output signal is transmitted for proper detection or acquisition. An unfilled material 64 between the bonding pad layer 59 and the 1C die 60 covers the internal flip-chip bonding pad 56 and the solder bump 62. 15 Please refer to the figure 2A-2E, first in FIG. 2A, the bonding pad layer 59 is generally a square structure, which usually includes a film layer 54 of polyimide PI tape for easy adhesion to the transparent substrate 52. The film window 57—A generally square structure extending from the center of the bonding pad 59. Multiple exteriors The bonding pads 58 are generally arranged in rows and columns along the four outer edges of the bonding pad layer 59. A plurality of inner 20 bonding pads 56 are generally arranged in rows and columns along the opposite sides of the film window 57 and extend parallel to the rows and columns of the external bonding pads 58. The bonding pad layer 59 is usually adhered to the upper surface 52a of the glass substrate 52 with a polyimide PI tape. Therefore, the glass substrate 52 may include additional pre-treatment before the pad 59 is adhered, such as in The glass substrate 52 may further include other material layers, for example, coating 13 1242269 with an anti-reflection layer, or removing an infrared layer, etc., to enhance the light image 72 or other performance received by the image sensor ic die 60. As shown in FIG. 2C, after the bonding pad layer 59 is formed on the glass substrate 52, an image sensor 5 having internal bumps 62 (such as tin, lead, or composite bumps) 1C grain 60 is inverted and Electrical contact is made on each of the corresponding internal bonding pads 56. Therefore, the light receiving surface 60a of the 1C die 60 passes through the thin film window 57 and faces the upper surface 52a of the glass substrate 52. The shape of the inner bump 62 is not limited to the spherical shape shown in FIG. 2, and for example, when it is a composite bump, it may be a cube, a cone, a cylinder, or the like. Generally, solder bumps are used for the 1C die of a CCD image sensor, while solder bumps are used for the 1C die of a CMOS image sensor. As shown in FIG. 2D, an unfilled material 64 between the bonding pad layer 59 and the 1C die 60 covers each of the internal solder bumps 62. The underfill material 64 protects the internal bonding pads 56 and the internal solder bumps 62 from dust, moisture 15 or other contamination, so as to enhance the reliability of the electrical connection between the internal bonding pads 56 and the 1C die 60. The underfill material 64 may be any suitable material including a small filler containing epoxy resin to enhance heat dissipation. In addition, between the 1C die 60 and the bonding pad layer 59, a translucent material may be further included in the gap region 63 to reduce the reflection vibration noise of the optical signal in between.
20 如圖2E所示，在未填滿材料64沈積於接合墊層59與1C 晶粒60間後，外部焊接球70對應形成於每一外部接合墊58 上。隨後位在PCB基材66之多個接合墊68相對應接合於外 部焊接球70上，以完成影像感測元件74。 14 1242269 再參考圖2D，其影像感測器之封裝結構5〇係為本發明 之技術内容，其具有之總厚度51 —般介於8〇〇至14〇〇μιη。 其璋小於一般習知之像感測器之封裝結構，其習知技藝之 一般厚度約為2mm。故相較於使用傳統之CCD或CM〇s影 像感測器之封裝結構，影像感測元件74可具有更小之尺寸。 圖3係為一般製作影像感測器封裝結構製程步驟之概 10 15 括流程圖。在製程步驟31中，内部接合墊與外部接合墊泰 供於接合墊層上。在製程步驟以中，此接合墊層提供於一 玻璃基材上。在製程步驟S3中，提供一具有内部凸塊之景 像感測器1C晶粒。在製程步驟辦，反轉此影像感測器信 其接合於接合墊層之内部接合墊上。在製程步驟Μ中，摘 供-未填滿材料於IC晶粒與接合塾層之間，防止内部接合 墊與内部焊接凸塊受到灰塵、水氣與其他之污染。在製程 步賴巾，㈣餘#合_之外部接合純供外部焊接 球。在製程步驟S7中’裝置—pCB於外部焊接球。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權·圍自應以申請專利範圍所述為準， 於上述實施例。As shown in FIG. 2E, after the unfilled material 64 is deposited between the bonding pad layer 59 and the 1C die 60, external solder balls 70 are correspondingly formed on each of the external bonding pads 58. Subsequently, a plurality of bonding pads 68 located on the PCB substrate 66 are correspondingly bonded to the external solder balls 70 to complete the image sensing element 74. 14 1242269 Referring again to FIG. 2D, the packaging structure 50 of the image sensor is the technical content of the present invention, and has a total thickness of 51-generally between 800 and 1400 μm. Its size is smaller than the package structure of the conventional image sensor, and its general thickness is about 2mm. Therefore, compared with the packaging structure using a conventional CCD or CMOS image sensor, the image sensing element 74 can have a smaller size. Fig. 3 is a schematic diagram of the general manufacturing process steps for manufacturing an image sensor package structure. In process step 31, the internal bonding pad and the external bonding pad are provided on the bonding pad layer. During the manufacturing process, the bonding pad layer is provided on a glass substrate. In the process step S3, a chip of the image sensor 1C with internal bumps is provided. In the process step, the image sensor is reversed to be bonded to the internal bonding pad of the bonding pad layer. In the process step M, extract-unfilled material is placed between the IC die and the bonding pads to prevent the internal bonding pads and internal solder bumps from being contaminated by dust, water vapor, and others. In the manufacturing process, the external joints of ㈣ 余 # 合 _ are purely for external welding balls. In the process step S7, the device-pCB is externally soldered. The above-mentioned embodiments are merely examples for convenience of explanation. The rights and claims claimed in the present invention should be based on the scope of the patent application, and are in the above-mentioned embodiments.
20【圖式簡單說明】 係習知之半導體覆晶之焊接凸塊與接合塾之結構剖視 圖。 T係習知之半導體覆晶之焊接凸塊與接合墊之結構俯 15 1242269 5 10 15 圖1B係習知之覆晶中晶粒上行列中之多個焊接凸塊之 視圖。 $ 圖1C係習知之用於封裝影像感測器之無引線晶片承載 裝之剖視圖。 圖2A係本發明之位於—玻璃基材上之接合塾層膠帶，具有 多個内部覆晶接合塾與外部球狀料列（bga)接合塾之接 合墊層之爆炸透視圖。 圖2B係本發明之位於玻璃基材上之接合墊層之透視圖。 圖2C係本發明之影像感測器之封裝結構之示意圖，係為— 反轉之影像感測器晶粒接合於接合塾層上之覆晶接合塾。 :本發明之影像感測器之封裝結構之示意圖，係為利 用未填滿材料包覆於覆晶接合墊與凸塊。 圖2E係本發明之影像感測器 ⑽接合於影像感測器之封裝 圖3係為依據本發明之方法的封裝步驟流20 [Brief description of the drawings] It is a cross-sectional view of a conventional structure of a solder bump and a bonding pad of a semiconductor flip chip. T is a structure of a conventional semiconductor flip-chip solder bump and a bonding pad 15 1242269 5 10 15 FIG. 1B is a view of a plurality of solder bumps in a row of grains of a conventional flip-chip. Figure 1C is a cross-sectional view of a conventional leadless wafer carrier package for packaging an image sensor. Fig. 2A is an exploded perspective view of a bonding pad on a glass substrate of the present invention having a plurality of internal flip-chip bonding pads and external bga bonding pads. Figure 2B is a perspective view of a bonding pad layer on a glass substrate of the present invention. FIG. 2C is a schematic diagram of the packaging structure of the image sensor of the present invention, which is a flip-chip bonding wafer in which the inverted image sensor die is bonded to the bonding wafer layer. : The schematic diagram of the packaging structure of the image sensor of the present invention is to cover the flip-chip bonding pads and bumps with unfilled materials. Fig. 2E is the package of the image sensor of the present invention ⑽ bonded to the image sensor Fig. 3 is the flow of the packaging steps according to the method of the present invention
U 明 說 # 圖 rL 焊接凸塊 11 13 圓形接墊開口 14 15 介電層 16 20 導電通孔 22 26 晶粒 28 30 無引線晶片承32 載封裝 〇视接墊 導電層 下導電層 基材 玻璃層 12 保護層 18 絕緣層 24 矽晶粒基材 34 防反射塗覆U 明说 # Figure rL solder bump 11 13 circular pad opening 14 15 dielectric layer 16 20 conductive via 22 26 die 28 30 leadless wafer carrier 32 carrier package Layer 12 Protective layer 18 Insulating layer 24 Silicon die substrate 34 Anti-reflection coating
16 1242269 35 支樓層 36 多層基材 38 影像感測器晶 片 40 上部鉛 42 城堡狀結構 44 底部鉛 46 厚度 50 影像感測器封5 1 總厚度 52 玻璃基材 裝結構 52a 上表面 53 基材厚度 54 薄膜層 55 膜厚 56 内部覆晶接合57 薄膜視窗 塾 58 外部球狀閘陣59 接合塾層 60 1C晶粒 列接合墊 60a 光接收面 61 厚度 62 内部凸塊 63 間隙區 64 未填滿材料 66 PCB基材 68 接合墊 70 外部焊接球 72 光影像 74 影像感測元件 1716 1242269 35 Branch floor 36 Multi-layer substrate 38 Image sensor chip 40 Upper lead 42 Castle-like structure 44 Bottom lead 46 Thickness 50 Image sensor seal 5 1 Total thickness 52 Glass substrate mounting structure 52a Upper surface 53 Substrate thickness 54 thin film layer 55 film thickness 56 internal flip-chip bonding 57 thin film window 球 58 outer spherical gate array 59 bonding 塾 layer 60 1C die row bonding pad 60a light receiving surface 61 thickness 62 inner bump 63 gap area 64 not filled with material 66 PCB substrate 68 Bonding pad 70 External solder ball 72 Light image 74 Image sensing element 17