1241669 故、發明說明： 明所屬^技術^領城^】 本發明係為球狀柵極陣列（BGA)封裝體之平坦化及測 試。 【先前技術】 發明背景 10 15 竿列（BGA)封裝_〜牧,丨六^ 一^ 密度的封襄體之積體電路元件。第1A圖顯示—習知bga圭 衣體100之範例’其在—互連基材14()上含有—半導體元到 7 °可屬於任何種類的半導體元件之元件11()_般係具肩 ('生連接至互連基材⑽上的接觸墊或跡線之電接觸塾。筹 Μ圖顯示線㈣卩12〇將半導體元件u㈣ 制 :並由-包封劑賺護線鲜部12。且加以絕緣： 4如覆㈣倾術料他電錢接技術可提供對於互 ，做電性連接。互連基材14〇—般係由一包含用於 =電訊號路徑的傳導性跡線(未圖示)之絕緣體製成。元件 ^接觸墊或終端係連接至—互連基材丨做巾及之上的 ¥性跡線並經由傳導性跡線連接至外部终端15〇。 卜、，卩、.、& 15G可排列在—稱為球狀柵極陣列（BGA)之 r料亚且通常為諸如銲球等金屬凸塊。外部終端150中的 ΓΓ迴㈣將封裝體】_接至—印刷電路板或其他電 二，統中連接封裝義時所產生的困難處在於 ；；而]5〇水平焉度(e—)的不均勻性。特定言之，製程 •又將生成大於平均值之部份終端15以及小於平均值之 20 1241669 部份終端150”。在迴銲或其他銲接程序期間，較小的終端 ㈣，可能未良好地接觸至—下方的印刷電路板或“，導 致較不可靠的連接。 $ 互連基材的撓曲同樣會使電性連接較不可靠。第汨圖 5顯示-包含-元件110之覆晶封裝體102。在覆晶封裝體ι〇2 中，元件11〇的接觸塾上之金屬凸塊122係接觸一互連基材 =上的塾或跡線。可利用元件11〇與互連基材142之間的— 絕緣充填材料132來改良封裝體1〇2的熱性質或機械性質。 1〇 用於互連基材142之製程或用於將互連基材142附接至 =件110之程序會造缝材142的撓曲。特定言之，元件㈣ 與互連基材142之間在互連歸142上具有可改變厚度或形 狀之充填材料132係會引進造成撓曲之應力。當用於低 =裝體之基材142較薄（譬如小於約2公厘厚）時，此撓曲二 】5吊I不論原因為何’基材142的撓曲會改變終端15〇的水 平高度，使得部份外部終端15 〇，，移動離開-可供封裝體！ 〇 2 附接之印刷電路板的平整表面。因此，換曲導致—不平坦 的終端150陣列及較不可靠的電性連接。 用灰改良球狀栅極陣列或元件的其他外部終端之平土曰 度之方法係可改善在一較大系統中連接封裝體時所形成之 20 電性連接品質。 【智P日月内溶^】 發明概要 根據本發明的一型態，可在封裝體測試用之電性接觸 的同時，利用用來整平電終端之測試設備在元件剛試期間 1241669 改良一元件封裝體上的一球狀柵極陣列或外部終端之平坦 度。測試之後，封裝體具有呈現經改良平坦度之外部終端， 而改良了一包含封裝體的系統在組裝期間形成之電性連接。 本發明的一特定實施例係為一用於測試一包含一元件 5 的封裝體之方法。此方法譬如藉由將封裝體插入一具有電 性接觸用的探針梢部之測試插座内使得封裝體上的外部終 端及一測試器上的探針梢部產生接觸。系統中的壓縮力提 供了良好的電性接觸以經由將探針梢部電性連接至外部終 端來對於元件作電性測試，並可使外部終端變形以改善外 10 部終端的平坦度。 探針梢部可附接至一諸如印刷電路板或插座基材等基 材且其可由與被測試封裝體中的互連基材相同之材料製 成。替代性實施例中，探針梢部可為基材上所形成之墊或 凸塊。各探針梢部可包括一平整的接觸區域並整平一對應 15 的外部終端，同時對於外部終端提供一電性連接。特定言 之，一具有一終端至少一半寬度之平整的接觸區域一般係 可提供適當的終端（譬如銲球）整平作用而不在終端頂部形 成凹陷。為了當探針基材的熱性質不同於封裝體的熱性質 時能夠在寬廣的溫度範圍中測試，更遠離中心點之探針梢 20 部可比較接近中心點的探針梢部具有更大的面積。 本發明的另一實施例為一測試方法。測試方法一般包 括將一包括一組接觸墊之印刷電路板連接至測試設備，其 中此組接觸墊具有一可與一含有一元件的封裝體上之經升 高終端相匹配之圖案。此方法使得封裝體及印刷電路板產 1241669 生接觸，所以元件上的經升高終端與印刷電路板上的接觸 墊產生電性連接。測試設備隨後可經由印刷電路板對於封 裝體的電性連接來測試元件。 本發明另一實施例係為一封裝體測試系統。測試系統 5 包括：一接觸結構，其具有呈現平整接觸表面之探針梢部； 一測試器，其電性連接至接觸結構；及一用於將平整接觸 表面與封裝體上的終端或BGA壓抵在一起之機構。部分實 施例中，探針梢部可為一印刷電路板上的接觸墊或凸塊， 且各接觸表面具有身為一對應終端的至少一半寬度之寬度。 10 圖式簡单說明 第1A及1B圖顯示習知的半導體元件封裝體中之不平 坦的外部終端； 第2圖為根據本發明的一實施例之封裝體測試設備的 方塊圖； 15 第3A、3B、3C及3D圖顯示用於改良一封裝體上的外部 終端平坦度之根據本發明的一實施例之一測試方法； 第4圖為用於測試及平坦化一被測試封裝體的外部終 端之根據本發明的一實施例之一探針的立體圖； 第5A及5B圖顯示用於根據本發明的一實施例在一溫 20 度範圍接受測試下之一探針。 不同圖中利用相同的代號來代表類似或相同的元件。 I：實施方式3 較佳實施例之詳細說明 根據本發明的一型態，一測試方法改良了一具有一 1241669 BGA或類似外部終端之半導體元件封裝體的外部終端之平 垣度。此測試方法可採用一具有使至少一呈現最高水平高 度的封裝體終端變形之探針梢部之接觸結構。結果，可降 低封裝體終端之整體水平高度變異。 5 第2圖為根據本發明的一實施例之測試設備200的方塊 圖，其改良了封裝體終端的平坦度。測試設備2〇〇包括自動 ’則试設備(ATE)210、一具有一測試板2%之測試頭220、一 包括一插座基材232之插座230、及一插座蓋236。測試設備 200對於一具有外部終端255之封裝體250進行電性測試。 10 封裝體250可包含任何類型的元件，其中包括但不限於 記憶體晶片、控制器、處理器、特殊應用積體電路(ASICs) 或任何其他類型的積體電路或分離的元件。可藉由包括但 不限於如第1A圖所示的打線接合(wire bonding)或如第1B 圖所示的覆晶封裝等任何需要的技術將元件連接至外部終 15端255。至於外部終端255，封裝體250具有適合譬如藉由一 迴銲程序附接至一印刷電路板或其他電系統之金屬凸塊。 在本發明的一示範性實施例中，外部終端255形成一球狀栅 極陣列（BGA)。對於目前的元件封裝體，終端150—般具有 依據陣列間距而定介於約5〇〇微米到約1〇〇〇微米之間平均 20 高度。譬如，終端150可為包含多個金屬層之銲球或複合結 構，諸如堆疊狀銲球、或一銅柱或其他金屬柱且其上覆有 一鋅料層、一銲球、金或一金短柱(gold stud)。 為了進行封裝體測試，將身為插座基材232—部分之探 針梢部234排列成與一封裝體250上的終端255圖案相匹配 1241669 之圖案。探針梢部234可為直接形成於插座基材232上之金 屬探針，但插座基材232可進一步包括用於在探針梢部234 與測試頭220之間提供電性連接之一或多個分離的互連基 材或元件。 5 為了測試之用，封裝體250插入插座230内且在其中使 外部終端255接觸探針梢部234。插座蓋236隨後可夾緊或用 其他方式操作而以足夠力量將封裝體250推往探針梢部234 使得終端255非彈性變形。ATE 21〇隨後將電輸入訊號經由 測5式頭220及採針梢部232施加至終端255並測量所產生的 10輸出訊號以決定封裝體200中的元件是否正常運作及提供 所需要的效能。 A T E 210、測試頭22 0及測試板22 5可為購自包括安捷倫 科技(Agilent Tedmologiesjnc·，）、泰瑞鼎（Teradyne，Inc )及 LTX公司（LTX Corporation)等各種不同供應商之標準測試 15設備。ATE 210一般利用依據封裝體250中元件類型而定的 習知方式來進行封裝體250中元件的電性測試。 根據本發明的-型態，探針梢部234具有有限的順應性 以利終端255在封裝體測試期間之變形。插座基材鐾如 可為-凸塊狀或非凸塊狀互連基材或印刷電路板。此等互 20連基材通常係由-種諸如聚酸胺或其他絕緣材料等有機材 料製成並包含用於將互連基材—側上的凸塊或接觸塾電性 連接至互連基枯一相對側上的—接觸墊及/或一 Bga之傳 導性跡線。互連基材一側上之凸塊或墊係形成探針梢部 234’其接觸到封裝體25()的终端255以供電性測試用並且能 10 1241669 夠杨足夠塵力以造成終端255變形。互連基材的相對側上 或其他終、係經由測試板225對於測試頭及ATE 21〇提供電性連接。 μ插座230及包括探針梢部234之插座基材232可為一均 貝性/整合性結構或可分離 一 0 口fM牛。—貫施例中，探針梢部 =4係位於—附接成為插座咖的—可移除構件之分離的基 材上。藉此可使用具有不同探針梢部234的插座23時測試 不同的封裝體。-具有可更換的探針梢部234之插座230传 10 15 步具有可快速更換受損探針梢部因而盡量縮短ΑΤΕ 21〇停工時間之優點。 u 插座基材说可剛性安裝或彈簧式安I在插座咖 對於探針梢部240整體提供有限 〒 I應性。順應性的量值可 從對於非順應性或剛性安裝的〇刊& 王J向達對於彈簧式安 15密耳。如下文進一步所描述，终 、 、缒255在測試期間所需 的變形或平坦化一般將控制了固令^ ^ 疋式或順應性安裝、順瘫 性安裝的最大移行距離、彈筈或货 負& -及其他可壓縮結構的數 及插座基材232的順應性安裝中 双里 模數之選擇。 [縮結構的彈簧常數或 可個印刷電路板技術生成 易構成為可匹配一特定封裝體之優 一有谷 ”、 不佔體積且非)|丨百_ 性探針梢部2 3 4的另-優點係為 #且非順應 』A ’、知1於針、彈I或縣臂彳 探針來說具有耐久性。探針梢部234 〜、f式 觸區域，如下文進-步所描述、可具有較大的平整接 正的接觸區域除了太 用與清理期間較不易受損之外亦$目+ 矛、f在使 J不具有會接取或容納顆粒 20 1241669 "卩或尖點。結果，即使長期使用而不清理，探針梢部 可對於受測試封裝體持續提供低的接觸阻抗。 、/在測試設備200中，一諸如插座蓋236上的夾持件等機 5械系统係生成了當封裝體乃〇以人工插入插座230後可提供 子兔性連接並造成探針梢部232使終端255變形之壓縮 匕或者，一測試處理系統可包括一用於揀取封裝體250並 冬封I體250插入插座230内之自動機械臂或系統。在此同 日夺 、自動系統可將壓力施加至封裝體250以使終端255非彈 1〇 又形並改善其平坦度。測試之後，測試處理系統係將良 好的封裝體移至搬運托板或搬運媒體以供後續運送之用。 第3A及3D圖顯不根據本發明的一實施例之一測試及 平垣化程序。第3A圖顯示測試前之一封裝體3〇〇的一部分。 封裝體300包含-其上安裝有―或多4固元件（未圖示）之互連 基材310。封裝體300的外部終端32〇、322及324可為銲球、 至屬柱或其他傳導性結構。此等終端一般排列在一球狀栅 極陣列（BGA)中。理想上，所有外部終端32〇、322及324皆 相對於一筝考平面升高至相同的水平高度。然而，在圖示 的封裝體300中，製造變異已經使得部分終端322比最高終 端320更短。此外，互連基材31 〇的撓曲亦改變外部終端 20 320、322及324的相對水平高度。第3八圖的範例中，終端322 及324的頂部對於最高終端320頂部的平面相距了偏移值Z1 及Z2。如果一偏移值Z1或Z2過大，當封裝體300附接至一 印刷電路板或其他平面性電系統時將產生微弱或有缺陷的 連接。 12 1241669 材33^3顯示根據本發明的1施例之一包括一測試基 梢13321^ ’且其具有平整的探針梢部阳。平整的探針 W3叫佳係具有身為終端32G、322及似的至少一半直 10 15 20 f寬度。本發日㈣―實施例中，峨基材3觸為-印刷 毛路板且探針梢部332為印刷電路板的—表面上之接觸塾 或金屬跡線。探針梢部说應由—種在施加終端似、切及 24非祕μ形所f要的力量時能夠避免非彈性變形之金 屬製成。當元件終端包含—諸如銲料等延展性材料時，對 於振針梢部332適合採用—諸如鋼等材料。 第3B圖顯㈣部332與基材3观面呈現齊平，但 板針梢部332或者亦可升高至測試基材33〇表面以上或甚至 相對於基材33〇表面其餘部分凹人。或者，_基材3观 可在封裝體3_m或输㈣讓探針梢部说底部相距互 連基材31G表面達到所f要的分離距離。 為了測。式用，一測試系統係驅動封裝體300及/或基材 別，以使探針梢部332底部接駐少部分的職電性終端 3山2〇、332及324(譬如直到探針梢部332抵達包含最高外部終 立而320頂部之平面為止）。在第3Β圖中，基材330處在與包含 具有最大水平高度之終端320的峰部之平面相對應之高度 且°卩刀的彳木針梢部332未與封裝體的各別外部終端332 及324產生良好之電性接觸。 測试5又備隨後進一步將基材310及330驅動更靠近一段 過度移灯距離ζ瑪成為_分離距離Η2，如第3C圖所示。此 方去整平了較咼的外部終端320並對於封裝體300的終端 13 1241669 320、322及324提供良好的電性連接。標準的測試設備35〇 可利用經由基材330中的探針梢部332及跡線334傳輸之電 性訊號來測試封裝體3〇〇。 測试方法使終端320、322及324非彈性變形。為此，當 5測試基材330如第3D圖所示自與封裝體300的接觸狀態抽出 時，經整平的終端340、342及344較均勻地具有相同高度 H3。因此，終端340、342及344的頂部具有比終端32〇、322 及324更好之平坦度，且當被探測封裝體附接至一印刷電路 板時，經改良的平坦度可增進接合的完整性。 10 過度移行距離Z3—般必須至少足以在各終端320、322 及324上提供低的接觸阻抗而能夠進行封裝體之電性測 試。即使一小的過度移行距離Z 3 (譬如電性測試所需要的最 小過度移行）一般亦會導致最大終端的整平作用，而改善了 終端的整體平坦度因而改善隨後利用封裝體3〇〇組裝之一 15 系統中互連接合部的完整性。更大量的過度移行可提供平 坦度的進一步改良，直到過度移行距離Z3提供所有終端 320、322及324之部分非彈性整平為止。在使各終端至少部 份地整平之時點後，終端340、342及342的平坦度變異係依 據平坦度變異及探針梢部332的順應性（compliance)而定。 20 可利用一諸如化學機械式拋光(CMP)在精密程序在製造期 間將探針梢部3 3 2平坦化，以使終端在測試後具有小的平坦 度變異。 第4圖顯示根據本發明的一實施例之一插座基材400的 立體圖，其具有形成於一印刷電路板4]0的接觸墊414或跡 14 1241669 線上之探針梢部412。跡線或導孔（未圖示）將接觸墊414連接 至印刷電路板410—相對側上之各別終端416。終端416係用 來連接至測試設備，譬如連接至一標準測試板或標準測試頭。 本發明的一示範性實施例中，印刷電路板410由一諸如 5 聚醯亞胺等絕緣材料製成，其中含有由一諸如銅或銘等金 屬製成的傳導性跡線。板410的尺寸可配合在測試設備中的 一插槽内，但具有呈現與被測試封裝體上終端（譬如BGA) 相匹配的圖案之接觸墊414。此BGA目前具有1或2公厘（譬 如1.7公厘）之常見的栅極間隔。探針梢部412可形成為一種 10 由諸如鋁、銅、鉑、铑或錫-鉛等金屬或傳導性環氧樹脂或 有機材料製成具有〇到約250微米高度的柱。如上述，一諸 如CMP等程序可將探針梢部412頂部平坦化。各探針梢部 412的面積或直徑一般係依據被測試封裝體之外部終端尺 寸而定。對於一含有約800微米直徑的銲球之BGA，探針梢 15 部412需要約400微米或更大的直徑。 根據本發明的一型態，可選擇板410的材料以匹配被測 試的封裝體中互連基材之熱性質。為此，在一溫度下與被 測試封裝體上的外部終端之圖案呈現匹配之基材上的探針 梢部412之圖案亦將在一升高溫度下與外部終端的圖案相 20 匹配。或者，如果板410的材料及互連基材不同，可設計探 針梢部412 (及墊414)的圖案以在任何所需要的測試溫度下 皆與封裝體終端的圖案相匹配。 根據本發明的另一型態，即使封裝體及探針具有不同 的熱性質，探針卡上之探針梢部的圖案或尺寸可在一寬廣 15 1241669 的溫度範圍中與一封裝體的終端產生適當的接觸。第5八及 5B圖顯示一探針510具有隨著相距探針51 〇中心的距離而拎 大尺寸之探針梢部511、512及513。為了探測用，探針51〇 中心係對準於一封裝體520的中心。第5A圖顯示封裝體52〇 5的外部終端522如何在第一溫度（譬如室溫）下對準於探針梢 部511、512及513。可在一升高溫度（譬如12(TC)下進行一‘‘所 處溫度（at-temperature)”測試。結果，因為其各別的熱膨服 係數差異，封裝體520的熱膨脹可與探針510的膨騰不同。 通常，封裝體520的差異性膨脹將使各終端522相對於對靡、 10 的探針梢部511、512或513移動，其移動量係與終端522及 封裝體520中心之間的距離成正比。為了補償差異性膨服， 塾511、512及513在對應終端522的位置範圍上延伸，以如 第5B圖所示使探針梢部511、512及513部分即便在升高溫产 下仍保持對準於各別終端522。 15 第5A及5B圖顯示一項使墊的面積隨著相距探針51〇中 心的距離而增大之實施例。或者，墊511、512及513可皆與 最大墊513製成相同的尺寸。 雖然已經參照特定實施例來描述本發明，只描述了本 發明的應用之一範例且不應視為限制。對於所揭露實施例 20的特性之各種改用及合併係位於由申請專利範圍界定之本 發明的範圍内。 【圖武1簡單* 明】 第1A及1 B圖顯示習知的半導體元件封裝體中之不平 坦的外部終端； 16 1241669 第2圖為根據本發明的一實施例之封裝體測試設備的 方塊圖； 弟3A、3B、3C及3D圖顯示用於改良一封裝體上的外部 終端平坦度之根據本發明的一實施例之一測試方法； 第4圖為用於測試及平坦化一被測試封裝體的外部終 令而之根據本發明的一實施例之一探針的立體圖； 第5A及5B圖顯示用於根據本發明的一實施例在一溫 度範圍接受測試下之一探針。 【圖式之主要元件代表符號表】 100···習知BGA封裝體 232,400···插座基材 102···覆晶封裝體 234,412?5115512,513 · · 110···半導體元件 236···插座蓋 120···線銲部 250,300,520···封裝體 122···金屬凸塊 330···測試基材 130···包封劑 332···平整的探針梢部 132···絕緣充填材料 340,342,344· · ·經整平的終端 140，142,31〇···互連基材 3 5 0…標準的測試設備 150,255,320,322,324,522 .··外 410···印刷電路板 部終端 414…接觸塾 150 ’…大於平均值之部份終端 416···終端 150’’···小於平均值之部份終端 510···探針 200…測試設備 m，H3…高度 210…自動測試設備(ATE) H2···分離距離 220…測試頭 Z1，Z2…偏移值 225…測試板 Z3···過度移行距離 230···插座 171241669 Therefore, the description of the invention: ^ Technology ^ Leading City ^] The present invention is a planarization and test of a ball grid array (BGA) package. [Prior Art] Background of the Invention 10 15 pole-row (BGA) packages are integrated circuit elements with a density of 6 ^^^. Figure 1A shows an example of the conventional bga body 100 'which contains-on the interconnect substrate 14 ()-semiconductor elements to 7 ° can belong to any type of semiconductor element 11 ()-generally with shoulders (The electrical contacts are connected to the contact pads or traces on the interconnect substrate. The chip diagram shows that the semiconductor device u is fabricated by: and the protective wire 12 is protected by an encapsulant. And insulation: 4 if the electrical connection technology can provide other electrical connections for electrical connection. The interconnection substrate 14 is generally composed of a conductive trace for the = electrical signal path ( (Not shown) is made of insulators. The components, contact pads, or terminals are connected to—interconnecting substrates—to make towels and traces on top of them and to conductive terminals to connect to external terminals 15. Bu ,,卩,., & 15G can be arranged in a material called a ball grid array (BGA) and usually a metal bump such as a solder ball. The ΓΓ in the external terminal 150 will package the package] _ To—printed circuit boards or other electrical components, the difficulty that arises when connecting package meanings is; and] 50 degrees of unevenness (e—) In particular, the process • will generate part of the terminal 15 larger than the average value and part of the terminal 150 less than the average value of 20 1241669 150 ”. During reflow or other welding procedures, smaller terminals may not work well. Contact to the printed circuit board or "below", resulting in a less reliable connection. $ The deflection of the interconnect substrate also makes the electrical connection less reliable. Figure 5 shows the flip-chip package containing-component 110 The body 102. In the flip-chip package ι02, the metal bump 122 on the contact pad of the component 11 is in contact with an interconnect substrate or trace. The component 11 and the interconnect substrate can be used. Between 142 — Insulative filling material 132 to improve the thermal or mechanical properties of the package body 102. 10. The process used to interconnect the substrate 142 or to attach the interconnect substrate 142 to the substrate 110. The procedure will cause the deflection of the seam material 142. In particular, the filling material 132 having a changeable thickness or shape on the interconnection layer 142 between the element ㈣ and the interconnection base material 142 will introduce stress that causes deflection. When For low = body substrate 142 is thin (for example, less than about 2 mm thick), this Deflection 2] 5 Hanging I No matter what the reason, 'The deflection of the substrate 142 will change the horizontal height of the terminal 15 °, so that some external terminals 15 °, move away-available for packaging! 〇2 The attached printed circuit The flat surface of the board. Therefore, the change of curvature results in-an uneven terminal 150 array and less reliable electrical connections. The method of improving the flatness of the spherical grid array or other external terminals of the component with gray can be improved 20 electrical connection qualities formed when the package is connected in a larger system. [Chi P dissolves within the sun and the moon ^] Summary of the invention According to a form of the present invention, the electrical contact for the package test can be performed at the same time In order to improve the flatness of a spherical gate array or external terminal on a component package, the test equipment used for leveling electrical terminals was used during the component test 1241669. After testing, the package has external terminals that exhibit improved flatness, and an electrical connection formed during assembly by a system containing the package is improved. A specific embodiment of the present invention is a method for testing a package including a component 5. This method, for example, inserts the package into a test socket having a probe tip for electrical contact so that the external terminal on the package and the probe tip on a tester are brought into contact. The compressive force in the system provides good electrical contact to electrically test the component by electrically connecting the probe tip to an external terminal, and can deform the external terminal to improve the flatness of the external 10 terminals. The probe tip can be attached to a substrate such as a printed circuit board or socket substrate and it can be made of the same material as the interconnect substrate in the package under test. In alternative embodiments, the probe tip may be a pad or a bump formed on the substrate. Each of the probe tips may include a flat contact area and a flat external terminal corresponding to 15 while providing an electrical connection to the external terminal. In particular, a flat contact area with at least half the width of a terminal generally provides a suitable terminal (e.g., solder ball) leveling action without forming a depression on top of the terminal. In order to be able to test in a wide temperature range when the thermal properties of the probe substrate are different from the thermal properties of the package, the probe tip 20 further away from the center point may have a larger probe tip than the probe tip closer to the center point. area. Another embodiment of the present invention is a test method. The test method generally includes connecting a printed circuit board including a set of contact pads to a test device, wherein the set of contact pads has a pattern that can be matched to a raised terminal on a package containing a component. This method makes contact between the package body and the printed circuit board 1241669, so the raised terminal on the component and the contact pad on the printed circuit board are electrically connected. The test equipment can then test the components via the printed circuit board's electrical connection to the package. Another embodiment of the present invention is a package testing system. The test system 5 includes: a contact structure having a probe tip showing a flat contact surface; a tester electrically connected to the contact structure; and a terminal or BGA pressure for connecting the flat contact surface to the package body Arrival institutions. In some embodiments, the probe tip may be a contact pad or a bump on a printed circuit board, and each contact surface has a width of at least half the width of a corresponding terminal. 10 Schematic illustrations Figures 1A and 1B show uneven external terminals in a conventional semiconductor device package; Figure 2 is a block diagram of a package testing device according to an embodiment of the present invention; 15 Section 3A , 3B, 3C and 3D diagrams show a test method according to an embodiment of the present invention for improving the flatness of an external terminal on a package; FIG. 4 is a diagram for testing and planarizing the exterior of a package under test A perspective view of a probe of a terminal according to an embodiment of the present invention; FIGS. 5A and 5B show a probe used for a test under a temperature of 20 degrees according to an embodiment of the present invention. The same reference numbers are used in different drawings to represent similar or identical elements. I: Detailed description of the preferred embodiment of Embodiment Mode 3 According to a form of the present invention, a test method improves the external terminal level of a semiconductor device package having a 1241669 BGA or similar external terminal. This test method may employ a contact structure having a probe tip that deforms at least one package terminal that exhibits the highest level of height. As a result, the overall level height variation of the package termination can be reduced. 5 FIG. 2 is a block diagram of a test apparatus 200 according to an embodiment of the present invention, which improves the flatness of the package terminal. The test equipment 200 includes an automatic test equipment (ATE) 210, a test head 220 having a test board 2%, a socket 230 including a socket base 232, and a socket cover 236. The test equipment 200 performs an electrical test on a package 250 having an external terminal 255. 10 Package 250 may contain any type of component, including but not limited to memory chips, controllers, processors, application-specific integrated circuits (ASICs), or any other type of integrated circuit or discrete component. The components can be connected to the external terminal 255 by any desired technique including, but not limited to, wire bonding as shown in FIG. 1A or flip-chip packaging as shown in FIG. 1B. As for the external terminal 255, the package 250 has metal bumps suitable for attachment to a printed circuit board or other electrical system, such as by a reflow process. In an exemplary embodiment of the present invention, the external terminal 255 forms a spherical gate array (BGA). For current component packages, the terminals 150 typically have an average height of between about 500 microns and about 1,000 microns, depending on the pitch of the array. For example, the terminal 150 may be a solder ball or a composite structure including a plurality of metal layers, such as a stacked solder ball, or a copper pillar or other metal pillar, and a zinc layer, a solder ball, gold, or a gold short is covered thereon. Gold stud. For the package test, the probe tip portion 234, which is a part of the socket base material 232, is arranged to match the pattern of the terminal 255 on the package 250 with a pattern of 1241669. The probe tip 234 may be a metal probe formed directly on the socket base 232, but the socket base 232 may further include one or more for providing electrical connection between the probe tip 234 and the test head 220. Separate interconnect substrates or components. 5 For testing purposes, the package 250 is inserted into the socket 230 with the external terminal 255 in contact with the probe tip 234 therein. The socket cover 236 may then be clamped or otherwise manipulated to push the package 250 toward the probe tip 234 with sufficient force to deform the terminal 255 inelastically. ATE 21〇 then applies the electrical input signal to the terminal 255 via the test head 220 and the needle tip 232 and measures the 10 output signals to determine whether the components in the package 200 are operating normally and provide the required performance. ATE 210, test head 22 0 and test board 22 5 are standard tests purchased from various suppliers including Agilent Tedmologiesjnc, Teradyne, Inc, and LTX Corporation 15 device. The ATE 210 generally performs electrical testing of the components in the package 250 using a conventional method that depends on the type of components in the package 250. According to the -type of the present invention, the probe tip 234 has limited compliance to facilitate deformation of the terminal 255 during package testing. The socket substrate may be, for example, a bump-shaped or non-bump-shaped interconnect substrate or a printed circuit board. These interconnected substrates are usually made of an organic material, such as polyurethane or other insulating materials, and contain bumps or contacts on the side of the interconnect substrate to electrically connect to the interconnect substrate. Dry on the opposite side-contact pads and / or a conductive trace of Bga. The bumps or pads on one side of the interconnect substrate form the probe tip 234 'which contacts the terminal 255 of the package 25 () for power supply testing and can be 10 1241669 enough dust to cause deformation of the terminal 255 . On the opposite side of the interconnect substrate or other terminals, an electrical connection is provided to the test head and the ATE 21 via a test board 225. The μ socket 230 and the socket base 232 including the probe tip 234 may be a homogeneous / integrated structure or may be separated by a 0-port fM cow. —In the embodiment, the probe tip = 4 is located on—a separate substrate that is attached to the socket—a removable member. This makes it possible to test different packages when sockets 23 having different probe tips 234 are used. -The socket 230 with 10 replaceable probe tips 234 has 10 15 steps, which has the advantage of quickly replacing damaged probe tips, thereby minimizing the ATOE 21 downtime. u The socket base material can be rigidly mounted or spring-loaded. The socket provides limited overall probe tip 240 performance. The magnitude of compliance can be found in the 0 & Wang J Xiangda for spring-loaded 15 mils for non-compliant or rigid installations. As described further below, the deformation or flattening required for the final, 缒, and 255 during the test will generally control the maximum travel distance, impeachment, or cargo load of the sturdy or compliant installation, paraplegic installation, and &-and the number of other compressible structures and the choice of the dual-line modulus in the compliance installation of the socket base 232. [The spring constant of the contracted structure or the printed circuit board technology can be easily constructed to match the advantages of a specific package. It does not take up volume and is not.] | 丨 百 _ probe tip 2 3 4 of the other- The advantage is # and non-compliant. "A", known as a needle, bullet I or county arm 彳 probe has durability. Probe tip 234 ~, f-type contact area, as described in the next step, It can have a large flat and straight contact area, in addition to being too used and less susceptible to damage during cleaning. The mesh + spear, f makes J not have the ability to pick up or contain particles 20 1241669 " 卩 or sharp points. As a result, the probe tip can continuously provide a low contact resistance to the package under test even if it is used for a long time without cleaning. In the test equipment 200, a mechanical system such as a clamp on the socket cover 236 A compression dagger that can provide a sub-rabbit connection when the package is manually inserted into the socket 230 and cause the probe tip 232 to deform the terminal 255 or a test processing system may include a package for picking the package 250 and Winter robot I body 250 or an automatic robotic arm or system inserted into the socket 230. On the same day, the automatic system can apply pressure to the package 250 to make the terminal 255 non-elastic and improve its flatness. After the test, the test processing system moves the good package to the carrier pallet or the media to For subsequent shipping. 3A and 3D diagrams show a test and flattening procedure according to one embodiment of the present invention. FIG. 3A shows a part of the package 300 before the test. The package 300 contains-its An interconnect substrate 310 is mounted thereon—or more than four solid-state components (not shown). The external terminals 32, 322, and 324 of the package 300 can be solder balls, subordinate pillars, or other conductive structures. These terminals Generally arranged in a ball grid array (BGA). Ideally, all external terminals 32, 322, and 324 are raised to the same level relative to a zigzag plane. However, the package 300 shown in the figure In manufacturing variations, some terminals 322 have been made shorter than the highest terminal 320. In addition, the deflection of the interconnect substrate 31 0 also changes the relative horizontal heights of the external terminals 20 320, 322, and 324. In the example in Figure 38, The tops of terminals 322 and 324 are for The plane at the top of the highest terminal 320 is offset by Z1 and Z2. If an offset Z1 or Z2 is too large, the package 300 will be weak or defective when attached to a printed circuit board or other planar electrical system. Connected. 12 1241669 Material 33 ^ 3 shows that one of the 1 examples according to the present invention includes a test base tip 13321 ^ 'and it has a flat probe tip. The flat probe W3 is called Jiaxi and has a terminal 32G. , 322, and the like are at least half straight 10 15 20 f width. In the present example, the contact between the substrate 3 and the probe tip 332 is a printed circuit board.塾 or metal trace. The tip of the probe should be made of a metal that can prevent inelastic deformation when applying the force required by the terminal shape, cutting, and 24 non-secret μ shapes. When the component terminal contains—a ductile material such as solder, the vibrating pin tip 332 is suitable—a material such as steel. Figure 3B shows that the protuberance 332 is flush with the surface of the substrate 3, but the plate needle tip 332 may be elevated above the surface of the test substrate 33o or even concave relative to the rest of the surface of the substrate 33o. Alternatively, the substrate 3 can be separated from the surface of the interconnecting substrate 31G to the desired separation distance at the bottom of the package 3_m or the probe tip. To test. For testing, a test system is used to drive the package 300 and / or the substrate so that the bottom of the probe tip 332 is connected to a small number of electrical terminals 3, 20, 332, and 324 (for example, up to the probe tip). 332 reaches the plane containing the highest external termination and the top of 320). In FIG. 3B, the substrate 330 is at a height corresponding to a plane including the peak portion of the terminal 320 having the maximum horizontal height, and the cypress needle tip portion 332 of the trowel is not connected to the respective external terminal 332 of the package. And 324 produces good electrical contact. Test 5 was then prepared to further drive the substrates 310 and 330 closer to a distance of excessive moving distance ζma to _ separation distance Η2, as shown in Figure 3C. This smoothes the relatively large external terminals 320 and provides good electrical connections to the terminals 13 1241669 320, 322, and 324 of the package 300. Standard test equipment 35 may test the package 300 using electrical signals transmitted through the probe tips 332 and traces 334 in the substrate 330. The test method deforms the terminals 320, 322, and 324 inelastically. For this reason, when the 5 test substrate 330 is extracted from the contact state with the package 300 as shown in FIG. 3D, the flattened terminals 340, 342, and 344 have the same height H3 more uniformly. Therefore, the tops of the terminals 340, 342, and 344 have better flatness than the terminals 32, 322, and 324, and when the probe package is attached to a printed circuit board, the improved flatness can improve the integrity of the joint. Sex. 10 Excessive travel distance Z3—Generally, it must be at least enough to provide low contact impedance at each terminal 320, 322, and 324 to enable electrical testing of the package. Even a small over-travel distance Z 3 (such as the minimum over-travel required for electrical testing) generally results in the leveling effect of the largest terminal, which improves the overall flatness of the terminal and thus improves subsequent assembly using the package 300. One of the 15 integrity of the interconnection joint in the system. A larger amount of over-migration can provide further improvement in flatness until the over-migration distance Z3 provides some inelastic leveling of all terminals 320, 322, and 324. After the terminals are leveled at least partially, the flatness variation of the terminals 340, 342, and 342 is determined based on the flatness variation and the compliance of the probe tip 332. 20 A precision procedure such as chemical mechanical polishing (CMP) can be used to flatten the probe tip 3 3 2 during manufacturing so that the terminal has a small flatness variation after testing. FIG. 4 shows a perspective view of a socket substrate 400 according to an embodiment of the present invention, which has a probe tip 412 formed on a contact pad 414 or a trace 14 1241669 on a printed circuit board 4] 0. Traces or vias (not shown) connect the contact pads 414 to the printed circuit board 410-respective terminals 416 on opposite sides. The terminal 416 is used to connect to a test device, such as a standard test board or a standard test head. In an exemplary embodiment of the present invention, the printed circuit board 410 is made of an insulating material such as polyimide, and contains conductive traces made of a metal such as copper or metal. The board 410 is sized to fit in a slot in the test equipment, but has contact pads 414 that present a pattern that matches the terminals on the package under test (such as BGA). This BGA currently has a common gate spacing of 1 or 2 mm (for example, 1.7 mm). The probe tip 412 may be formed as a post having a height of 0 to about 250 micrometers made of a metal such as aluminum, copper, platinum, rhodium, or tin-lead or a conductive epoxy or organic material. As described above, a procedure such as CMP can flatten the top of the probe tip 412. The area or diameter of each probe tip 412 generally depends on the external terminal size of the package under test. For a BGA containing solder balls having a diameter of about 800 microns, the probe tip portion 412 requires a diameter of about 400 microns or greater. According to a form of the present invention, the material of the board 410 may be selected to match the thermal properties of the interconnect substrate in the package under test. For this reason, the pattern of the probe tip 412 on the substrate that matches the pattern of the external terminal on the package under test at a temperature will also match the pattern of the external terminal at an elevated temperature. Alternatively, if the material of the board 410 and the interconnect substrate are different, the pattern of the probe tip 412 (and pad 414) can be designed to match the pattern of the package termination at any required test temperature. According to another aspect of the present invention, even if the package body and the probe have different thermal properties, the pattern or size of the probe tip on the probe card can be matched with the end of a package in a wide temperature range of 15 1241669. Make the right contact. Figures 58 and 5B show that a probe 510 has probe tips 511, 512, and 513 that are large in size as the distance from the center of the probe 51 °. For detection, the center of the probe 51 is aligned with the center of a package 520. FIG. 5A shows how the external terminal 522 of the package 5205 is aligned with the probe tips 511, 512, and 513 at a first temperature (for example, room temperature). An "at-temperature" test can be performed at an elevated temperature, such as 12 (TC). As a result, the thermal expansion of the package 520 can be compared with that of the probe because of its different thermal expansion coefficient. The expansion of 510 is different. Generally, the differential expansion of the package 520 will cause each terminal 522 to move relative to the probe tip 511, 512, or 513 of the counterclockwise, and the amount of movement is the same as that of the terminal 522 and the center of the package 520 The distance between them is proportional. In order to compensate for the differential swelling, 塾 511, 512, and 513 extend over the position range corresponding to the terminal 522, so as to make the probe tip 511, 512, and 513 even as shown in Figure 5B. Aligned to the respective terminal 522 under high temperature production. 15 Figures 5A and 5B show an embodiment in which the area of the pad increases with the distance from the center of the probe 51. Or, the pads 511, 512 Both and 513 can be made the same size as the largest pad 513. Although the present invention has been described with reference to specific embodiments, only one example of the application of the present invention is described and should not be considered as a limitation. For the characteristics of the disclosed embodiment 20 The various conversions and mergers are located in patent applications It is within the scope of the present invention. [Figure 1 is simple and clear] Figures 1A and 1B show uneven external terminals in a conventional semiconductor device package; 16 1241669 Figure 2 is a schematic view of the first embodiment of the present invention. The block diagram of the package test equipment of the embodiment; 3A, 3B, 3C and 3D diagrams show a test method according to an embodiment of the present invention for improving the flatness of external terminals on a package; FIG. 4 is A perspective view of a probe according to an embodiment of the present invention for testing and flattening the exterior of a package under test; FIGS. 5A and 5B show a temperature range used for an embodiment of the present invention. Accept the test of one of the probes below. [Schematic representation of the symbols of the main components of the drawing] 100 ··· BGA package body 232,400 ·· Socket base material 102 ·· Flip chip package body 234,412-5115512,513 ·· 110 Semiconductor component 236. Socket cover 120. Wire bond 250, 300, 520. Package 122. Metal bump 330. Test substrate 130. Encapsulant 332. Flat Probe tip 132 ... Insulation filling material 340,342,344 ... · · Flattened terminals 140, 142, 31 · · · Interconnect substrate 3 5 0 ... Standard test equipment 150, 255, 320, 322, 324, 522 · · Outer 410 · · · Printed circuit board terminal 414 ... Contact 塾 150 '... larger than Part of average terminal 416 ... Terminal 150 '' ... Part of terminal 510 smaller than average ... Probe 200 ... Test equipment m, H3 ... Height 210 ... Automatic test equipment (ATE) H2 ... · Separation distance 220… Test head Z1, Z2… Offset value 225… Test board Z3 ··· Over-travel distance 230 ··· Socket 17