TWI236743B - Flip chip package and process thereof - Google Patents
Flip chip package and process thereof Download PDFInfo
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- TWI236743B TWI236743B TW93110324A TW93110324A TWI236743B TW I236743 B TWI236743 B TW I236743B TW 93110324 A TW93110324 A TW 93110324A TW 93110324 A TW93110324 A TW 93110324A TW I236743 B TWI236743 B TW I236743B
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- bump
- wafer
- pads
- bumps
- flip
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- 238000000034 method Methods 0.000 title claims description 10
- 238000012858 packaging process Methods 0.000 claims abstract description 17
- 229910000679 solder Inorganic materials 0.000 claims description 25
- 239000000853 adhesive Substances 0.000 claims description 23
- 230000001070 adhesive effect Effects 0.000 claims description 23
- 230000003064 anti-oxidating effect Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 238000004806 packaging method and process Methods 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000010117 shenhua Substances 0.000 claims 2
- 238000003466 welding Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 39
- 239000010410 layer Substances 0.000 description 36
- 239000000463 material Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000003292 glue Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
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- Wire Bonding (AREA)
Abstract
Description
1236743 五、發明說明(1) 發明所屬之技術領域 本發明是有關於一種封裝結構及封裝製程,且特別是 有關於一種藉由柱狀凸塊與凹陷的接合區之設計來提高晶 片與承載器之對位精度的覆晶封裝結構及其封裝製程。 先前技術 在半導體產業中,積體電路(Integrated Circuits, I C )的生產,主要分為三個階段:晶圓(w a f e r )的製 造、積體電路(IC)的製作以及積體電路的封裝 (package )等。其中,封裝的目的在於防止裸晶片受到 濕氣及雜訊等外界物質的影響,並提供裸晶片與外部電路 之間電性連接的媒介。 然而,隨著積體電路之積集度的增加,晶片的封裝結 構也越來越多樣化,而覆晶接合技術(F 1 i p C h i p Interconnect Technology,簡稱FC)由於具有縮小晶片 封裝面積及縮短訊號傳輸路徑等優點,目前已經廣泛應用 於晶片封裝領域,其中諸如晶片尺寸構裝(Chip Scale Package, CSP)、晶片直接貼附封裝(Direct Chip Attached, DCA)以及多晶片模組封裝(Multi-Chip Module, MCM )等型態的封裝模組,均可以利用覆晶接合 技術而達到封裝的目的。 覆晶接合技術乃是利用面陣列(a r e a a r r a y )的方 式,將多個銲塾配置於晶片(chip)之主動表面(active surface )上,並在銲塾上形成凸塊(bump)。接著,將 晶片翻覆(f 1 i P ),並使晶片上之凸塊與承載器1236743 V. Description of the invention (1) Technical field to which the invention belongs The present invention relates to a packaging structure and a packaging process, and more particularly to a method for improving a chip and a carrier by designing a bonding region between a columnar bump and a recess Chip-on-chip packaging structure with its alignment accuracy and its packaging process. Prior technology In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages: the manufacture of wafers, the manufacture of integrated circuits (ICs), and the packaging of integrated circuits (packages) )Wait. The purpose of the package is to prevent the bare chip from being affected by external substances such as moisture and noise, and to provide a medium for the electrical connection between the bare chip and external circuits. However, with the increase of the integration degree of integrated circuits, the package structure of chips has become more and more diversified, and F 1 ip Chip Interconnect Technology (FC) has reduced the package area and shortened the chip size. Signal transmission paths and other advantages have been widely used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA), and Multi-chip Module Packaging (Multi- Chip modules (MCM) and other types of packaging modules can use the flip-chip bonding technology to achieve the purpose of packaging. The flip-chip bonding technology uses an area array (a r a a r r a y) method to arrange a plurality of solder pads on an active surface of a chip and form bumps on the solder pads. Next, the wafer is turned over (f 1 i P), and the bumps and the carrier on the wafer are turned over.
12314twf.ptd 第6頁 1236743 五、發明說明(2) (carrier : 預銲材(p r 機械性連接 並透過承載 值得一 題: 1 .由於 導電膠材上 上,如 便可能 上的期 2. 塊墊的 能使得 承載器 發明内 有 構,其 導電膠 精度。 本 於承載 導電膠 基 此一 會有 望位 由於 間距 相鄰 上之 鑒於 中凸 材量 發明 器之 材量 於上 )上之凸塊墊透過一導電膠材 e-solder )或助銲劑(flux) ,使得晶片可經由凸塊而電性 器之内部線路而電性連接至外 提的是,習知之覆晶接合製程 導電膠材係為膏狀的樣式,因 之後,凸塊並不能穩固地固定 來,只要凸塊與承載器之接點 凸塊偏移的現象發生,使得凸 置。 積體電路之積集度的增加,使 縮小,而當凸塊墊上之導電膠 之凸塊藉由導電膠材橋接(br 電路發生短路的情形。 此,本發明的目的就是在提供 塊墊上方具有凹陷的接合區, ,並有助於提供晶片與承載器 的另一目的是在提供一種覆晶 凸塊墊上方形成一凹陷的接合 J並提南晶片與承載裔之間的 述目的,本發明提出一種覆晶 ,例如導電膠、 ,而相互電性及 連接至承載器, 界之電子裝置。 通常具有下列問 此當凸塊附著到 在承載器之接點 之對位不精確, 塊偏離在承載器 得承載器上之凸 材過多時,便可 i d g e ),而導致 一種覆晶封裝結 因而可有效控制 之間較佳的對位 封裝製程,其係 區,以有效控制 對位精度。 封裝結構,其例12314twf.ptd Page 6 1236743 V. Description of the invention (2) (carrier: pre-welded material (pr mechanically connected and through the bearing is worth a question: 1. Since the conductive adhesive material is on, it will be possible if the period is 2.) The pad can make the carrier invention structured, and its conductive adhesive precision. Originally, the conductive adhesive base is expected to be in a position where the distance is adjacent due to the convexity on the convex material. The pad passes a conductive adhesive material (e-solder) or flux, so that the chip can be electrically connected to the outside through the internal circuit of the bump and the electrical device. The conventional conductive adhesive material for the flip-chip bonding process is The paste-like pattern, because afterwards, the bumps cannot be firmly fixed, as long as the bumps at the contact points of the carrier and the bumps are offset, the protrusions are placed. The increase of the integration degree of the integrated circuit makes it shrink, and when the bumps of the conductive glue on the bump pad are bridged by the conductive glue (br circuit short circuit occurs. Therefore, the purpose of the present invention is to provide a block pad above It has a recessed bonding area, and helps to provide a wafer and a carrier. Another purpose is to provide a recessed joint J over a flip-chip bump pad and to mention the stated purpose between the wafer and the carrier. The invention proposes a flip chip, such as a conductive adhesive, an electronic device that is electrically and connected to a carrier. It usually has the following problems: when the bumps are attached to the contacts of the carrier, the alignment is inaccurate, and the blocks deviate. When the carrier has too many convex materials on the carrier, it can be IDD), which results in a flip-chip packaging junction, which can effectively control the better alignment packaging process, and its area to effectively control the alignment accuracy. Package structure, its example
12314twf.ptd 第7頁 1236743 五、發明說明(3) 如包括一承 包括一基板 置於基板表 凸塊容納開 外,晶片係 具有多個銲 另夕卜,柱狀 凸塊之部分 在本發 更包括一抗 凸塊 且抗 墊。此 氧化層 在本發 更包括一導 並電性連接 更包括多個 維持承載器 基於上 先,提供一 基板 並具 口係分別暴 如具 後 表面具 有對應 有一主 於晶片 載器 ,其 面, v , 配置 墊 , 凸塊 係位 明之 氧化 外, 例如 明之 電膠 凸塊 間隙 與晶 述目 承載 有多 於凸 露出 動表 之銲 、一晶 表面例 其中銲 且凸塊 於承載 且銲墊 係配置 於其所 較佳實 層,其 抗氧化 可以是 較佳實 材,其 塾與柱 物,其 片間之 的,本 器,其 個凸塊 塊墊之 凸塊墊 面,且 墊上形 片以及 如具有 罩層例 容納開 器上方 的位置 於銲墊 對應的 施例中 係配置 層更可 多個 多個 如具 口係 ,且 與凸 與凸 凸塊 ,上 於凸 覆蓋 柱狀凸 凸塊墊 有對應 分別暴 晶片之 塊墊的 塊墊之 容納開 述之覆 塊容納 凸塊容 塊。承載器例如 ,而鐸罩層係配 於凸塊墊的多個 露出凸塊墊。此 一主動表面例如 係相對應。 位置 間, 口内 晶封 開口 納開 鎳/金層 施例中 係配置 狀凸塊 係配置 間隙。 發明更 例如包墊,而 多個凸 。接著 主動表 成多個 ,上 於凸 。此 於承 述之覆晶封 塊塾與柱狀 外,覆晶封 載器與晶片 提出一種覆晶封 括一基板與一銲 層係配置於 納開口 ,且 銲罩 塊容 ,提 面上 柱狀 供一 曰曰 片 例如具有多 凸塊。之後 且每一柱狀 〇 裝結構例如 内,並覆蓋 口之側壁, 裝結構例如 凸塊之間, 裝結構例如 之間,用以 裝製程。首 罩層,其中 基板表面, 凸塊容納開 其中晶片例 個銲墊。然 ,以覆晶方12314twf.ptd Page 7 1237643 V. Description of the invention (3) If a bearing is included, a substrate is placed on the surface of the substrate and the bumps are accommodated. The wafer has a plurality of solders. It also includes an anti-bump and anti-pad. The oxide layer in the present invention further includes a conductive and electrical connection, and further includes a plurality of maintenance carriers. Based on the above, a substrate is provided and the openings are respectively exposed on the rear surface with a main carrier corresponding to the wafer. v, configuration pads, bumps are exposed to bright oxidation, for example, the gap between the bumps and crystals of Mingjiao Electrode carry more welds than those exposed on the moving surface, a crystal surface example where the welds and bumps are on the load and the pads are It is arranged in its preferred solid layer, and its anti-oxidation can be a better solid material, its puppets and pillars, between the pieces, the device, the bump pad surface of each bump block pad, and the shaped sheet on the pad And if there is a cover layer to accommodate the position above the opener, the arrangement layer in the embodiment corresponding to the pad can be more than one, such as with a mouth, and with convex and convex bumps, above the convex cover cylindrical convex convex The block pad has a block accommodating block accommodating block accommodating block as described in the block pad corresponding to the block pad of the wafer. The carrier is, for example, and the Duo cover layer is attached to a plurality of exposed bump pads of the bump pad. This active surface corresponds, for example. Between the positions, the mouth is crystal-sealed and the opening is opened to open the nickel / gold layer. In the embodiment, the bumps are arranged, and the gaps are arranged. The invention is more like a cushion, while multiple convex. Then take the initiative to form a number of, on the convex. Based on the chip-on-chip seals and pillars described above, the chip-on-chip carriers and wafers propose a chip-on-chip encapsulation that includes a substrate and a solder layer that are arranged in the nano-opening, and the solder mask block volume and column on the surface For example, the sheet has multiple bumps. Afterwards, each column-shaped structure is installed inside, for example, and covers the side wall of the mouth, the structure is installed between the bumps, and the structure is installed between the structures, for example. The first cover layer, in which the substrate surface, the bumps are accommodated, and the wafer is a pad. Of course
12314twf.ptd 第8頁 1236743 五、發明說明(4) 式將晶片之柱 凸塊與凸塊墊 在本發明 對應插入凸塊 成一抗氧化層 "ί匕層更例如包 在本發明 對應插入凸塊 形成多個間隙 在本發明 對應插入凸塊 入一導電膠材 口之後,更包 基於上述 狀凸塊,並於 片與承載器接 開口内。與習 程可提高晶片 塊墊之間發生 導電膠材係位 到較有效的控 橋接。 為讓本發 對應插入凸 合。 實施例中, 口之前,更 抗氧化層係 凸塊容納開 實施例中, 口之前,更 實施例中, 口之前,更 ,在將柱狀 狀凸塊進行 狀凸塊 對應接 之較佳 容納開 ,且此 括覆蓋 之較佳 容納開 物。 之較佳 容納開 。此外 括對柱 之柱狀凸塊 納開口内形 此外,此抗 之柱狀凸塊 與晶片之間 之柱狀凸塊 納開口内填 凸塊容納開 狀凸塊球 程係搭配柱 口,使付晶 入凸塊容納 結構及其製 免凸塊與凸 與凸塊墊之 電膠材量得 溢出而相互 塊容納開口内,並使柱狀 其中在將晶片 包括於凸塊容 覆蓋凸塊塾。 口之側壁。 其中在將晶片 包括於承載器 其中在將晶片 包括於凸塊容 凸塊對應插入 迴銲,以將柱 ,本發明之覆晶封裝結構及其製 承載器上形成凹陷的凸塊容納開 合時,晶片之柱狀凸塊可對應納 知相較之下,本發明之覆晶封裝 與承載器之間的對位精度,以避 錯位。此外,由於連接柱狀凸塊 於凸塊容納開口内,因此可對導 制,以避免相鄰兩凸塊因導電膠 明之上述和其他目的、特徵、和優點能更明12314twf.ptd Page 8 1236743 V. Description of the invention (4) Insert the bumps of the wafer and the bump pads into the corresponding bumps of the present invention to form an anti-oxidation layer. For example, wrap the bumps in the corresponding inserts of the present invention. The blocks form a plurality of gaps. After the corresponding insertion bumps of the present invention are inserted into a conductive adhesive port, the gaps are further based on the above-mentioned bumps, and are placed in the openings between the sheet and the carrier. And the practice can improve the occurrence of conductive adhesive material between the wafer block pads to more effective control bridging. In order to make the hair corresponding to insert convex. In the embodiment, before the mouth, more anti-oxidation layer-type bumps are accommodated. In the embodiment, before the mouth, in the embodiment, before the mouth, and more, the columnar bumps are better accommodated by the corresponding bumps. Open, and this encompasses the better containing openings. The better to accommodate open. In addition, it includes the inner shape of the columnar bumps of the column. In addition, the columnar bumps between the columnar bumps of the resistance and the wafer are filled with bumps to accommodate the open bumps. Fu Jing into the bump accommodating structure and the method for preventing the amount of the electric adhesive material of the bumps and the bumps and the bump pads from overflowing and mutually accommodating into the openings, and the columnar shape including the wafer in the bumps and covering the bumps 覆盖. The side wall of the mouth. When the wafer is included in the carrier, the wafer is included in the bump, and the bump is correspondingly inserted into the reflow soldering to form a pillar, a flip chip package structure of the present invention, and a recessed bump formed on the carrier to accommodate the opening and closing. In comparison, the columnar bumps of the wafer can correspond to the receiving accuracy. In comparison, the alignment accuracy between the flip-chip package and the carrier of the present invention is to avoid misalignment. In addition, since the columnar bumps are connected in the bump receiving openings, it can be guided to avoid the above and other purposes, features, and advantages of the two adjacent bumps due to the conductive glue being clearer.
12314twf.ptd 第9頁 1236743 五、發明說明(5) 顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細 說明如下。 實施方式 請參考圖1 ,其繪示本發明之較佳實施例之一種晶片 封裝結構的示意圖。覆晶封裝結構10 0例如包括一承載器 1 1 0、一晶片1 2 0以及多個柱狀凸塊1 3 0 ,其中承載器1 1 0例 如包括一基板1 1 2以及一銲罩層1 1 4。此外,基板1 1 2可以 是一單層板或一多層板,其例如具有一承載表面1 1 2 a,而 銲罩層1 1 4係配置於承載表面1 1 2 a,且銲罩層1 1 4例如具有 多個凸塊容納開口 1 1 4 a,其係暴露出承載表面1 1 2 a上的多 個凸塊墊1 1 6。另外,凸塊墊1 1 6之表面與凸塊容納開口 1 1 4 a之側壁例如可配置有一抗氧化層1 1 8,其例如可以是 一鎳/金層,用以防止凸塊墊116過度氧化,並可在凸塊墊 1 1 6上構成一凹陷的接合區。 請再參考圖1 ,晶片1 2 0係配置於承載器1 1 0之承載表 面112a上方,其中晶片120之一主動表面120a上具有對應 於凸塊墊116的多個銲墊122,而柱狀凸塊130係配置於銲 墊1 2 2上。此外,柱狀凸塊1 3 0之一端係對應嵌入銲罩層 114之凸塊容納開口114a内,並透過一導電膠材140與凸塊 墊1 1 6接合。值得注意的是,為維持晶片1 2 0與承載器1 1 0 之間的間隙與其接合強度,晶片1 2 0與承載器1 1 0更例如可 配置多個間隙物(s p a c e r ) 1 5 0。 為了詳細說明本發明之特徵,下文係針對上述之覆晶 封裝結構的製程加以說明。請參考圖2 A〜2 E,其依序繪示12314twf.ptd Page 9 1236743 V. Description of the invention (5) It is easy to understand. The preferred embodiment will be described in detail below with reference to the attached drawings. Embodiments Please refer to FIG. 1, which illustrates a schematic diagram of a chip package structure according to a preferred embodiment of the present invention. The flip-chip package structure 10 0 includes, for example, a carrier 1 10, a wafer 1 2 0, and a plurality of columnar bumps 1 3 0, wherein the carrier 1 1 0 includes a substrate 1 1 2 and a solder mask layer 1 1 4. In addition, the substrate 1 1 2 may be a single-layer board or a multi-layer board. For example, the substrate 1 1 2 has a bearing surface 1 1 2 a, and the solder mask layer 1 1 4 is disposed on the bearing surface 1 1 2 a, and the solder mask layer 1 1 4 has, for example, a plurality of bump receiving openings 1 1 4 a, which exposes a plurality of bump pads 1 1 6 on the bearing surface 1 1 2 a. In addition, the surface of the bump pad 1 16 and the sidewall of the bump receiving opening 1 1 4 a may be configured with an anti-oxidation layer 1 1 8, which may be, for example, a nickel / gold layer to prevent the bump pad 116 from being excessive. It can be oxidized and can form a recessed bonding area on the bump pad 1 16. Please refer to FIG. 1 again. The wafer 120 is disposed above the carrying surface 112a of the carrier 110, wherein one of the active surfaces 120a of the wafer 120 has a plurality of pads 122 corresponding to the bump pads 116, and the columnar shape The bumps 130 are disposed on the pads 1 2 2. In addition, one end of the columnar bump 130 is correspondingly embedded in the bump receiving opening 114a of the solder mask layer 114, and is connected to the bump pad 116 through a conductive adhesive 140. It is worth noting that, in order to maintain the gap between the wafer 120 and the carrier 110, and the bonding strength thereof, the wafer 120 and the carrier 110 can be configured with multiple gaps (s p a c e r) 150. In order to explain the features of the present invention in detail, the following describes the manufacturing process of the above-mentioned flip-chip packaging structure. Please refer to Figure 2 A ~ 2 E, which are shown in order
12314twf.ptd 第10頁 1236743 五、發明說明(6) 本發明之較佳實施例之一種覆晶封裝製程的示意圖。 首先,如圖2A所示,提供一承載器110,其例如包括 一基板1 1 2與一銲罩層1 1 4。其中,基板1 1 2例如可以是一 單層板或一多層板,而焊罩層1 1 4係配置於基板1 1 2之一承 載表面1 1 2 a上,且銲罩層1 1 4具有多個凸塊容納開口 1 1 4 a,其係分別暴露出承載表面1 1 2 a上的多個凸塊墊 116° 接著,如圖2 B所示,於凸塊容納開口 1 1 4 a内形成一抗 氧化層1 1 8,且抗氧化層1 1 8係覆蓋凸塊墊1 1 6以及凸塊容 納開口 1 1 4 a之側壁,以形成一凹陷的接合區。其中,形成 抗氧化層1 1 8的方法例如可以先於凸塊容納開口 1 1 4a的側 φ 壁上形成一電鍵種子層(未繪示)之後,再於電鑛種子層 (未繪示)上電鍵一鎳/金材料層(未繪示),以形成抗 氧化層1 1 8。 然後,如圖2 C所示,於凸塊容納開口 1 1 4 a内填入一導 電膠材140。其中,藉由凸塊容納開口114a,可使導電膠 · 材1 4 0的量得到良好的控制,而導電膠材1 4 0例如可為導電 、 膠、預銲材(pre-solder)或助銲劑(flux)等。 接著,如圖2D所示,提供一晶片120,其具有一主動 表面120a,且主動表面120a上例如配置有多個銲墊122。 並且,於銲墊122上形成多個柱狀凸塊130,以及於主動表 面1 2 0 a的其他區域上形成多個間隙物1 5 0。其中,柱狀凸 _ 塊1 3 0的材質則例如可為錫鉛合金、無鉛合金(1 e ad f r e e a 1 1 oy )或金等導電材質。當然,在合理的範圍内,亦可12314twf.ptd Page 10 1236743 V. Description of the Invention (6) A schematic diagram of a flip-chip packaging process according to a preferred embodiment of the present invention. First, as shown in FIG. 2A, a carrier 110 is provided, which includes, for example, a substrate 1 12 and a solder mask layer 1 1 4. Wherein, the substrate 1 1 2 may be, for example, a single-layer board or a multilayer board, and the solder mask layer 1 1 4 is arranged on one of the bearing surfaces 1 1 2 a of the substrate 1 1 2, and the solder mask layer 1 1 4 There are a plurality of bump receiving openings 1 1 4 a, which respectively expose a plurality of bump pads 116 ° on the bearing surface 1 1 2 a. Next, as shown in FIG. 2B, the bump receiving openings 1 1 4 a An anti-oxidation layer 1 1 8 is formed inside, and the anti-oxidation layer 1 1 8 covers the sidewalls of the bump pad 1 16 and the bump receiving opening 1 1 4 a to form a recessed bonding area. The method for forming the anti-oxidation layer 1 1 8 can be, for example, forming an electric bond seed layer (not shown) on the side φ wall of the bump receiving opening 1 1 4a, and then forming an electric seed layer (not shown). Power on a layer of nickel / gold material (not shown) to form an oxidation resistant layer 1 1 8. Then, as shown in FIG. 2C, a conductive adhesive 140 is filled in the bump receiving opening 1 1 4a. Among them, the amount of the conductive adhesive material 140 can be well controlled by the bump receiving opening 114a, and the conductive adhesive material 140 can be, for example, conductive, glue, pre-solder, or auxiliary material. Flux, etc. Next, as shown in FIG. 2D, a wafer 120 is provided, which has an active surface 120a, and for example, a plurality of solder pads 122 are arranged on the active surface 120a. In addition, a plurality of columnar bumps 130 are formed on the pads 122, and a plurality of gaps 150 are formed on other areas of the active surface 12a. The material of the columnar convex blocks 1 3 0 can be, for example, a tin-lead alloy, a lead-free alloy (1 e ad f r e a 1 1 oy), or a conductive material such as gold. Of course, within a reasonable range,
12314twf.ptd 第11頁 1236743 五、發明說明(7) 以將柱狀凸塊130改為圖釘狀凸塊(stud bump)或其他可 與凸塊容納開口 1 1 4 a配合之凸塊。 承接上述,間隙物1 5 0之材質例如可為導電材質或絕 緣材質,然為避免承載器1 1 0之表面線路的誤橋接或造成 其他元件之間的電子干擾,其中當以絕緣材質為較佳之選 擇。此外,間隙物1 5 0應具有一較佳之抗壓強度,以在後 續之晶片1 2 0與承載器1 1 0接合時,可有效地維持晶片1 2 0 與承載器1 1 0之間的距離,而在本發明之其他實施例中, 亦可改為將間隙物1 5 0形成於承載器1 1 0之銲罩層1 1 4上。12314twf.ptd Page 11 1236743 V. Description of the invention (7) The columnar bump 130 is changed to a stud bump or other bump that can be matched with the bump receiving opening 1 1 4 a. Following the above, the material of the gap 150 can be, for example, a conductive material or an insulating material, but in order to avoid mis-bridge of the surface line of the carrier 1 10 or cause electronic interference between other components, the insulating material is preferred The best choice. In addition, the gap 150 should have a better compressive strength, so that when the subsequent wafer 1 2 0 and the carrier 1 10 are joined, the gap between the wafer 1 2 0 and the carrier 1 1 0 can be effectively maintained. Distance, and in other embodiments of the present invention, the spacer 150 may be formed on the solder mask layer 1 1 4 of the carrier 1 10 instead.
之後,如圖2 E所示,以覆晶方式將晶片1 2 0與承載器 1 1 0接合。其中,晶片1 2 0上之柱狀凸塊1 3 0係對應插入承 載器110之凸塊容納開口114a内,並透過導電膠材130而與 凸塊墊1 1 6上的抗氧化層11 8對應接合,而間隙物1 5 0係位 於晶片1 2 0與承載器1 1 0之間。Thereafter, as shown in FIG. 2E, the wafer 120 and the carrier 110 are bonded in a flip-chip manner. Among them, the columnar bumps 130 on the wafer 120 are correspondingly inserted into the bump receiving openings 114a of the carrier 110 and pass through the conductive adhesive 130 to the anti-oxidation layer 11 8 on the bump pads 1 1 6 Corresponding to the bonding, the gap 150 is located between the wafer 120 and the carrier 110.
承上所述,本發明之特徵係在於藉由承載器上之銲罩 層的凸塊容納開口形成一凹陷的接合區,並於晶片上形成 柱狀凸塊,以與凹陷的接合區對應後合。此外,承載器之 凸塊墊上例如可形成有抗氧化層,而本發明之抗氧化層除 可如上述實施例所示全面性地覆蓋晶片容納開口的内表面 之外,在一較佳實施例中,亦可僅於凸塊墊之表面形成抗 氧化層。如圖3所示即為本發明之較佳實施例之另一種晶 片封裝結構的示意圖,其中抗氧化層Π 8僅覆蓋於凸塊墊 1 1 6之表面,並與晶片容納開口 1 1 4 a之側壁形成凹陷之接 合區。另外,本實施例之其他相關元件及其配置關係因與As mentioned above, the present invention is characterized in that a recessed bonding area is formed by the bump receiving opening of the solder mask layer on the carrier, and a columnar bump is formed on the wafer to correspond to the recessed bonding area. Together. In addition, an anti-oxidation layer may be formed on the bump pad of the carrier, for example, and the anti-oxidation layer of the present invention can cover the inner surface of the wafer receiving opening in a comprehensive manner as shown in the above embodiment, in a preferred embodiment. It is also possible to form an anti-oxidation layer only on the surface of the bump pad. Figure 3 is a schematic diagram of another chip packaging structure according to a preferred embodiment of the present invention, in which the anti-oxidation layer Π 8 covers only the surface of the bump pad 1 1 6 and is in contact with the wafer receiving opening 1 1 4 a The sidewalls form recessed joints. In addition, other related elements and their configuration relationships in this embodiment are related to
12314twf.ptd 第12頁 1236743 五、發明說明(8) 前述實施例類似,在此不再重複贅述。 值得注意的是,本發明之覆晶封裝結構及其封裝製程 係於凸塊墊上方之凹陷接合區内配置導電膠材,並藉由導 電膠材連接柱狀凸塊及凸塊墊,以期在不經過習知之回銲 融熔製程的情形下,仍可於晶片與承載器之間提供良好的 接著性。當然,在其他情形下,本發明之覆晶封裝製程亦 可在晶片與承載器接合後,再對柱狀凸塊進行一迴銲製 程,以增加晶片與承載器之接著性。請參考圖4,其繪示 本發明之較佳實施例之又一種晶片封裝結構的示意圖。如 圖4所示,原先之柱狀凸塊與導電膠材在加熱至半融熔狀 態後,將因内聚力的作用而成為一球體,並在冷卻後,於 銲墊1 2 2與凸塊墊1 1 4上之抗氧化層1 1 8之間形成一球狀凸 塊 1 3 0 a。 綜上所述,本發明的覆晶封裝結構及其製程係於承載 器的凸塊墊上方形成多個凹陷的接合區,以使得晶片與承 載器對應接合時,晶片上之柱狀凸塊可對應納入凸塊墊上 方之凹陷的接合區内,用以提高晶片與承載器之間的對位 精度,並避免凸塊與凸塊墊之間錯位的情形發生。此外, 凸塊墊上方之凹陷的接合區内可容納導電膠材,並可在晶 片與承載器接合時,防止導電膠材溢出而導致相鄰兩凸塊 或承載器之表面線路藉由導電膠相互橋接,因而可提高覆 晶封裝製程之良率。另外,在凸塊墊之形狀與導電膠材之 材質之間取得良好搭配的前提下,本發明之覆晶封裝製程 更可省略習知對凸塊進行迴銲的步驟,改為提供較簡單之12314twf.ptd Page 12 1236743 V. Description of the invention (8) The foregoing embodiments are similar, and are not repeated here. It is worth noting that the flip-chip packaging structure and the packaging process of the present invention are configured with a conductive adhesive material in a recessed joint area above the bump pad, and the columnar bumps and the bump pad are connected by the conductive adhesive material, so as to It can still provide good adhesion between the wafer and the carrier without going through the conventional reflow process. Of course, in other cases, the flip-chip packaging process of the present invention can also perform a re-soldering process on the columnar bumps after the wafer is bonded to the carrier to increase the adhesion between the wafer and the carrier. Please refer to FIG. 4, which illustrates a schematic diagram of another chip package structure according to a preferred embodiment of the present invention. As shown in FIG. 4, the original columnar bumps and conductive adhesive material will become a sphere due to cohesion after heating to a semi-melted state, and after cooling, they will be applied to the solder pads 1 2 2 and the bump pads. A spherical bump 1 3 0 a is formed between the antioxidant layers 1 1 8 on 1 1 4. In summary, the flip-chip packaging structure of the present invention and its manufacturing process form a plurality of recessed bonding areas above the bump pads of the carrier, so that when the wafer and the carrier are correspondingly bonded, the columnar bumps on the wafer can be bonded. Correspondingly incorporated into the recessed joint area above the bump pad, to improve the alignment accuracy between the wafer and the carrier, and to avoid misalignment between the bump and the bump pad. In addition, the conductive bonding material can be accommodated in the recessed bonding area above the bump pad, and can prevent the conductive adhesive material from overflowing when the wafer is bonded to the carrier, which can cause the surface lines of two adjacent bumps or the carrier to pass through the conductive adhesive. Bridges each other, which can improve the yield of the flip-chip packaging process. In addition, under the premise of a good match between the shape of the bump pad and the material of the conductive adhesive material, the flip-chip packaging process of the present invention can omit the conventional step of re-soldering the bumps and provide a simpler
12314twf.ptd 第13頁 1236743 五、發明說明(9) 製程,以達到降低生產成本,提高生產效率的目的。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。12314twf.ptd Page 13 1236743 V. Description of the invention (9) Process to achieve the purpose of reducing production costs and improving production efficiency. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
12314twf.ptd 第14頁 1236743 圖式簡單說明 圖1繪示為本發明之較佳實施例之一種晶片封裝結構 的示意圖。 圖2 A〜2 E依序繪示為本發明之較佳實施例之一種覆晶 封裝製程的示意圖。 圖3繪示為本發明之較佳實施例之另一種晶片封裝結 構的示意圖。 圖4繪示為本發明之較佳實施例之又一種晶片封裝結 構的示意圖。 【圖式標示說明】 1 0 0 :覆晶封裝結構 1 1 0 :承載器 1 1 2 :基板 1 1 2 a :承載表面 1 1 4 :録罩層 1 1 4 a :凸塊容納開口 1 1 6 :凸塊墊 1 1 8 ··抗氧化層 120 :晶片 1 20a :主動表面 1 2 2 :銲墊 1 3 0 :柱狀凸塊 1 3 0 a :球狀凸塊 1 4 0 :導電膠材 1 5 0 :間隙物12314twf.ptd Page 14 1236743 Brief Description of Drawings Figure 1 shows a schematic diagram of a chip package structure according to a preferred embodiment of the present invention. 2A to 2E are schematic diagrams of a flip-chip packaging process according to a preferred embodiment of the present invention. FIG. 3 is a schematic diagram of another chip packaging structure according to a preferred embodiment of the present invention. FIG. 4 is a schematic diagram of another chip packaging structure according to a preferred embodiment of the present invention. [Illustration of diagrammatic labeling] 1 0 0: flip-chip package structure 1 1 0: carrier 1 1 2: substrate 1 1 2 a: bearing surface 1 1 4: recording cover layer 1 1 4 a: bump receiving opening 1 1 6: bump pad 1 1 8 ·· antioxidation layer 120: wafer 1 20a: active surface 1 2 2: pad 1 3 0: columnar bump 1 3 0 a: spherical bump 1 4 0: conductive adhesive Material 1 5 0: Spacer
12314twf.ptd 第15頁12314twf.ptd Page 15
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TW93110324A TWI236743B (en) | 2004-04-14 | 2004-04-14 | Flip chip package and process thereof |
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TW93110324A TWI236743B (en) | 2004-04-14 | 2004-04-14 | Flip chip package and process thereof |
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Publication Number | Publication Date |
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TWI236743B true TWI236743B (en) | 2005-07-21 |
TW200534444A TW200534444A (en) | 2005-10-16 |
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TW93110324A TWI236743B (en) | 2004-04-14 | 2004-04-14 | Flip chip package and process thereof |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN114725031A (en) * | 2021-11-19 | 2022-07-08 | 杰华特微电子股份有限公司 | Packaging structure of flip chip |
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2004
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114725031A (en) * | 2021-11-19 | 2022-07-08 | 杰华特微电子股份有限公司 | Packaging structure of flip chip |
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TW200534444A (en) | 2005-10-16 |
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