TWI236743B - Flip chip package and process thereof - Google Patents

Abstract

A flip chip package and a packaging process thereof are provided. A carrier has a plurality of bump pads, and a cavity for carrying bump is formed above each bump pad. In addition, a chip is disposed on the carrier, and a plurality of pillar-bumps is formed on the bonding pads. The pillar-bumps are embedded into the cavities above the bumping pads and connected between the bonding pads and the bump pads. The flip chip package and the packaging process thereof can improve the alignment precision between the chip and the carrier, and can prevent bridging by the conductive material between the neighboring bonding pads.

Description

1236743 V. Description of the invention (1) Technical field to which the invention belongs The present invention relates to a packaging structure and a packaging process, and more particularly to a method for improving a chip and a carrier by designing a bonding region between a columnar bump and a recess Chip-on-chip packaging structure with its alignment accuracy and its packaging process. Prior technology In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages: the manufacture of wafers, the manufacture of integrated circuits (ICs), and the packaging of integrated circuits (packages) )Wait. The purpose of the package is to prevent the bare chip from being affected by external substances such as moisture and noise, and to provide a medium for the electrical connection between the bare chip and external circuits. However, with the increase of the integration degree of integrated circuits, the package structure of chips has become more and more diversified, and F 1 ip Chip Interconnect Technology (FC) has reduced the package area and shortened the chip size. Signal transmission paths and other advantages have been widely used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA), and Multi-chip Module Packaging (Multi- Chip modules (MCM) and other types of packaging modules can use the flip-chip bonding technology to achieve the purpose of packaging. The flip-chip bonding technology uses an area array (a r a a r r a y) method to arrange a plurality of solder pads on an active surface of a chip and form bumps on the solder pads. Next, the wafer is turned over (f 1 i P), and the bumps and the carrier on the wafer are turned over.

12314twf.ptd Page 6 1236743 V. Description of the invention (2) (carrier: pre-welded material (pr mechanically connected and through the bearing is worth a question: 1. Since the conductive adhesive material is on, it will be possible if the period is 2.) The pad can make the carrier invention structured, and its conductive adhesive precision. Originally, the conductive adhesive base is expected to be in a position where the distance is adjacent due to the convexity on the convex material. The pad passes a conductive adhesive material (e-solder) or flux, so that the chip can be electrically connected to the outside through the internal circuit of the bump and the electrical device. The conventional conductive adhesive material for the flip-chip bonding process is The paste-like pattern, because afterwards, the bumps cannot be firmly fixed, as long as the bumps at the contact points of the carrier and the bumps are offset, the protrusions are placed. The increase of the integration degree of the integrated circuit makes it shrink, and when the bumps of the conductive glue on the bump pad are bridged by the conductive glue (br circuit short circuit occurs. Therefore, the purpose of the present invention is to provide a block pad above It has a recessed bonding area, and helps to provide a wafer and a carrier. Another purpose is to provide a recessed joint J over a flip-chip bump pad and to mention the stated purpose between the wafer and the carrier. The invention proposes a flip chip, such as a conductive adhesive, an electronic device that is electrically and connected to a carrier. It usually has the following problems: when the bumps are attached to the contacts of the carrier, the alignment is inaccurate, and the blocks deviate. When the carrier has too many convex materials on the carrier, it can be IDD), which results in a flip-chip packaging junction, which can effectively control the better alignment packaging process, and its area to effectively control the alignment accuracy. Package structure, its example

12314twf.ptd Page 7 1237643 V. Description of the invention (3) If a bearing is included, a substrate is placed on the surface of the substrate and the bumps are accommodated. The wafer has a plurality of solders. It also includes an anti-bump and anti-pad. The oxide layer in the present invention further includes a conductive and electrical connection, and further includes a plurality of maintenance carriers. Based on the above, a substrate is provided and the openings are respectively exposed on the rear surface with a main carrier corresponding to the wafer. v, configuration pads, bumps are exposed to bright oxidation, for example, the gap between the bumps and crystals of Mingjiao Electrode carry more welds than those exposed on the moving surface, a crystal surface example where the welds and bumps are on the load and the pads are It is arranged in its preferred solid layer, and its anti-oxidation can be a better solid material, its puppets and pillars, between the pieces, the device, the bump pad surface of each bump block pad, and the shaped sheet on the pad And if there is a cover layer to accommodate the position above the opener, the arrangement layer in the embodiment corresponding to the pad can be more than one, such as with a mouth, and with convex and convex bumps, above the convex cover cylindrical convex convex The block pad has a block accommodating block accommodating block accommodating block as described in the block pad corresponding to the block pad of the wafer. The carrier is, for example, and the Duo cover layer is attached to a plurality of exposed bump pads of the bump pad. This active surface corresponds, for example. Between the positions, the mouth is crystal-sealed and the opening is opened to open the nickel / gold layer. In the embodiment, the bumps are arranged, and the gaps are arranged. The invention is more like a cushion, while multiple convex. Then take the initiative to form a number of, on the convex. Based on the chip-on-chip seals and pillars described above, the chip-on-chip carriers and wafers propose a chip-on-chip encapsulation that includes a substrate and a solder layer that are arranged in the nano-opening, and the solder mask block volume and column on the surface For example, the sheet has multiple bumps. Afterwards, each column-shaped structure is installed inside, for example, and covers the side wall of the mouth, the structure is installed between the bumps, and the structure is installed between the structures, for example. The first cover layer, in which the substrate surface, the bumps are accommodated, and the wafer is a pad. Of course

12314twf.ptd Page 8 1236743 V. Description of the invention (4) Insert the bumps of the wafer and the bump pads into the corresponding bumps of the present invention to form an anti-oxidation layer. For example, wrap the bumps in the corresponding inserts of the present invention. The blocks form a plurality of gaps. After the corresponding insertion bumps of the present invention are inserted into a conductive adhesive port, the gaps are further based on the above-mentioned bumps, and are placed in the openings between the sheet and the carrier. And the practice can improve the occurrence of conductive adhesive material between the wafer block pads to more effective control bridging. In order to make the hair corresponding to insert convex. In the embodiment, before the mouth, more anti-oxidation layer-type bumps are accommodated. In the embodiment, before the mouth, in the embodiment, before the mouth, and more, the columnar bumps are better accommodated by the corresponding bumps. Open, and this encompasses the better containing openings. The better to accommodate open. In addition, it includes the inner shape of the columnar bumps of the column. In addition, the columnar bumps between the columnar bumps of the resistance and the wafer are filled with bumps to accommodate the open bumps. Fu Jing into the bump accommodating structure and the method for preventing the amount of the electric adhesive material of the bumps and the bumps and the bump pads from overflowing and mutually accommodating into the openings, and the columnar shape including the wafer in the bumps and covering the bumps 覆盖. The side wall of the mouth. When the wafer is included in the carrier, the wafer is included in the bump, and the bump is correspondingly inserted into the reflow soldering to form a pillar, a flip chip package structure of the present invention, and a recessed bump formed on the carrier to accommodate the opening and closing. In comparison, the columnar bumps of the wafer can correspond to the receiving accuracy. In comparison, the alignment accuracy between the flip-chip package and the carrier of the present invention is to avoid misalignment. In addition, since the columnar bumps are connected in the bump receiving openings, it can be guided to avoid the above and other purposes, features, and advantages of the two adjacent bumps due to the conductive glue being clearer.

12314twf.ptd Page 9 1236743 V. Description of the invention (5) It is easy to understand. The preferred embodiment will be described in detail below with reference to the attached drawings. Embodiments Please refer to FIG. 1, which illustrates a schematic diagram of a chip package structure according to a preferred embodiment of the present invention. The flip-chip package structure 10 0 includes, for example, a carrier 1 10, a wafer 1 2 0, and a plurality of columnar bumps 1 3 0, wherein the carrier 1 1 0 includes a substrate 1 1 2 and a solder mask layer 1 1 4. In addition, the substrate 1 1 2 may be a single-layer board or a multi-layer board. For example, the substrate 1 1 2 has a bearing surface 1 1 2 a, and the solder mask layer 1 1 4 is disposed on the bearing surface 1 1 2 a, and the solder mask layer 1 1 4 has, for example, a plurality of bump receiving openings 1 1 4 a, which exposes a plurality of bump pads 1 1 6 on the bearing surface 1 1 2 a. In addition, the surface of the bump pad 1 16 and the sidewall of the bump receiving opening 1 1 4 a may be configured with an anti-oxidation layer 1 1 8, which may be, for example, a nickel / gold layer to prevent the bump pad 116 from being excessive. It can be oxidized and can form a recessed bonding area on the bump pad 1 16. Please refer to FIG. 1 again. The wafer 120 is disposed above the carrying surface 112a of the carrier 110, wherein one of the active surfaces 120a of the wafer 120 has a plurality of pads 122 corresponding to the bump pads 116, and the columnar shape The bumps 130 are disposed on the pads 1 2 2. In addition, one end of the columnar bump 130 is correspondingly embedded in the bump receiving opening 114a of the solder mask layer 114, and is connected to the bump pad 116 through a conductive adhesive 140. It is worth noting that, in order to maintain the gap between the wafer 120 and the carrier 110, and the bonding strength thereof, the wafer 120 and the carrier 110 can be configured with multiple gaps (s p a c e r) 150. In order to explain the features of the present invention in detail, the following describes the manufacturing process of the above-mentioned flip-chip packaging structure. Please refer to Figure 2 A ~ 2 E, which are shown in order

12314twf.ptd Page 10 1236743 V. Description of the Invention (6) A schematic diagram of a flip-chip packaging process according to a preferred embodiment of the present invention. First, as shown in FIG. 2A, a carrier 110 is provided, which includes, for example, a substrate 1 12 and a solder mask layer 1 1 4. Wherein, the substrate 1 1 2 may be, for example, a single-layer board or a multilayer board, and the solder mask layer 1 1 4 is arranged on one of the bearing surfaces 1 1 2 a of the substrate 1 1 2, and the solder mask layer 1 1 4 There are a plurality of bump receiving openings 1 1 4 a, which respectively expose a plurality of bump pads 116 ° on the bearing surface 1 1 2 a. Next, as shown in FIG. 2B, the bump receiving openings 1 1 4 a An anti-oxidation layer 1 1 8 is formed inside, and the anti-oxidation layer 1 1 8 covers the sidewalls of the bump pad 1 16 and the bump receiving opening 1 1 4 a to form a recessed bonding area. The method for forming the anti-oxidation layer 1 1 8 can be, for example, forming an electric bond seed layer (not shown) on the side φ wall of the bump receiving opening 1 1 4a, and then forming an electric seed layer (not shown). Power on a layer of nickel / gold material (not shown) to form an oxidation resistant layer 1 1 8. Then, as shown in FIG. 2C, a conductive adhesive 140 is filled in the bump receiving opening 1 1 4a. Among them, the amount of the conductive adhesive material 140 can be well controlled by the bump receiving opening 114a, and the conductive adhesive material 140 can be, for example, conductive, glue, pre-solder, or auxiliary material. Flux, etc. Next, as shown in FIG. 2D, a wafer 120 is provided, which has an active surface 120a, and for example, a plurality of solder pads 122 are arranged on the active surface 120a. In addition, a plurality of columnar bumps 130 are formed on the pads 122, and a plurality of gaps 150 are formed on other areas of the active surface 12a. The material of the columnar convex blocks 1 3 0 can be, for example, a tin-lead alloy, a lead-free alloy (1 e ad f r e a 1 1 oy), or a conductive material such as gold. Of course, within a reasonable range,

12314twf.ptd Page 11 1236743 V. Description of the invention (7) The columnar bump 130 is changed to a stud bump or other bump that can be matched with the bump receiving opening 1 1 4 a. Following the above, the material of the gap 150 can be, for example, a conductive material or an insulating material, but in order to avoid mis-bridge of the surface line of the carrier 1 10 or cause electronic interference between other components, the insulating material is preferred The best choice. In addition, the gap 150 should have a better compressive strength, so that when the subsequent wafer 1 2 0 and the carrier 1 10 are joined, the gap between the wafer 1 2 0 and the carrier 1 1 0 can be effectively maintained. Distance, and in other embodiments of the present invention, the spacer 150 may be formed on the solder mask layer 1 1 4 of the carrier 1 10 instead.

Thereafter, as shown in FIG. 2E, the wafer 120 and the carrier 110 are bonded in a flip-chip manner. Among them, the columnar bumps 130 on the wafer 120 are correspondingly inserted into the bump receiving openings 114a of the carrier 110 and pass through the conductive adhesive 130 to the anti-oxidation layer 11 8 on the bump pads 1 1 6 Corresponding to the bonding, the gap 150 is located between the wafer 120 and the carrier 110.

As mentioned above, the present invention is characterized in that a recessed bonding area is formed by the bump receiving opening of the solder mask layer on the carrier, and a columnar bump is formed on the wafer to correspond to the recessed bonding area. Together. In addition, an anti-oxidation layer may be formed on the bump pad of the carrier, for example, and the anti-oxidation layer of the present invention can cover the inner surface of the wafer receiving opening in a comprehensive manner as shown in the above embodiment, in a preferred embodiment. It is also possible to form an anti-oxidation layer only on the surface of the bump pad. Figure 3 is a schematic diagram of another chip packaging structure according to a preferred embodiment of the present invention, in which the anti-oxidation layer Π 8 covers only the surface of the bump pad 1 1 6 and is in contact with the wafer receiving opening 1 1 4 a The sidewalls form recessed joints. In addition, other related elements and their configuration relationships in this embodiment are related to

12314twf.ptd Page 12 1236743 V. Description of the invention (8) The foregoing embodiments are similar, and are not repeated here. It is worth noting that the flip-chip packaging structure and the packaging process of the present invention are configured with a conductive adhesive material in a recessed joint area above the bump pad, and the columnar bumps and the bump pad are connected by the conductive adhesive material, so as to It can still provide good adhesion between the wafer and the carrier without going through the conventional reflow process. Of course, in other cases, the flip-chip packaging process of the present invention can also perform a re-soldering process on the columnar bumps after the wafer is bonded to the carrier to increase the adhesion between the wafer and the carrier. Please refer to FIG. 4, which illustrates a schematic diagram of another chip package structure according to a preferred embodiment of the present invention. As shown in FIG. 4, the original columnar bumps and conductive adhesive material will become a sphere due to cohesion after heating to a semi-melted state, and after cooling, they will be applied to the solder pads 1 2 2 and the bump pads. A spherical bump 1 3 0 a is formed between the antioxidant layers 1 1 8 on 1 1 4. In summary, the flip-chip packaging structure of the present invention and its manufacturing process form a plurality of recessed bonding areas above the bump pads of the carrier, so that when the wafer and the carrier are correspondingly bonded, the columnar bumps on the wafer can be bonded. Correspondingly incorporated into the recessed joint area above the bump pad, to improve the alignment accuracy between the wafer and the carrier, and to avoid misalignment between the bump and the bump pad. In addition, the conductive bonding material can be accommodated in the recessed bonding area above the bump pad, and can prevent the conductive adhesive material from overflowing when the wafer is bonded to the carrier, which can cause the surface lines of two adjacent bumps or the carrier to pass through the conductive adhesive. Bridges each other, which can improve the yield of the flip-chip packaging process. In addition, under the premise of a good match between the shape of the bump pad and the material of the conductive adhesive material, the flip-chip packaging process of the present invention can omit the conventional step of re-soldering the bumps and provide a simpler

12314twf.ptd Page 13 1236743 V. Description of the invention (9) Process to achieve the purpose of reducing production costs and improving production efficiency. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

12314twf.ptd Page 14 1236743 Brief Description of Drawings Figure 1 shows a schematic diagram of a chip package structure according to a preferred embodiment of the present invention. 2A to 2E are schematic diagrams of a flip-chip packaging process according to a preferred embodiment of the present invention. FIG. 3 is a schematic diagram of another chip packaging structure according to a preferred embodiment of the present invention. FIG. 4 is a schematic diagram of another chip packaging structure according to a preferred embodiment of the present invention. [Illustration of diagrammatic labeling] 1 0 0: flip-chip package structure 1 1 0: carrier 1 1 2: substrate 1 1 2 a: bearing surface 1 1 4: recording cover layer 1 1 4 a: bump receiving opening 1 1 6: bump pad 1 1 8 ·· antioxidation layer 120: wafer 1 20a: active surface 1 2 2: pad 1 3 0: columnar bump 1 3 0 a: spherical bump 1 4 0: conductive adhesive Material 1 5 0: Spacer

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Claims (1)

1236743 VI. Scope of patent application 1 · A bearing is provided for correspondingly receiving the placement surface in the opening chip, and there are a lot of ridges in it, and each of these columns openings 2. It includes a primary antibody, and the Anti-oxidation 4. The anti-oxidation 5. Includes a guide pillar convex 6. Including the majority of the Ruoxi oxidation cover such as Shenhua layer such as Shenhua layer such as Shendian plastic block as described in a flip chip package structure, including: The device includes: a substrate having a plurality of bump pads on the surface of the substrate; a solder mask layer disposed on the surface of the substrate, wherein the solder mask layer has a plurality of bumps accommodating openings of the bump pads, and the bumps are different from each other; The bump pads are exposed; disposed above the carrier, the wafer has an active watch wafer, the active surface of the wafer has a plurality of solder pads, and the positions of the solder pads are corresponding; The bumps, which are arranged on the solder pads and the bump-like bumps, are located in the bumps to accommodate one. The flip-chip packaging structure described in item 1 of the patent scope, more clad And the anti-oxidation layer is disposed on the bump container Opening the plurality of bump pads. The flip-chip package structure described in item 2 of the patent scope further includes a side wall covering the bump receiving openings. The flip-chip package structure described in item 2 of the patent scope includes a nickel / gold layer. The flip-chip packaging structure described in item 1 of the patent scope is more packaged, and the conductive adhesive is disposed between the bump pads and the pads, and electrically connects the bump pads and the pillars. Bump. The chip-on-chip packaging structure described in item 1 of the patent scope is more inclusive, and the spacers are arranged on the carrier and the wafer. 12314twf.ptd Page 16 1236743 6. Scope of patent application Between films. 7 · A flip-chip packaging process, including: providing a carrier, the carrier including a substrate and a solder mask layer, wherein the substrate surface has a plurality of bump pads, and the solder mask layer is arranged on the substrate The surface has a plurality of bump receiving openings corresponding to the bump pads, and the bump receiving openings respectively expose the bump pads; a wafer is provided, the wafer has an active surface, and the wafer The active surface has a plurality of pads; a plurality of columnar bumps are formed on the pads of the wafer; and the columnar bumps of the wafer are correspondingly inserted into the bump receiving openings in a flip-chip manner. And make the columnar bumps corresponding to the bump pads. 8. The flip-chip packaging process according to item 7 of the scope of patent application, wherein before the corresponding columnar bumps of the wafer are correspondingly inserted into the bump receiving openings, it further comprises forming a bump receiving opening in the bump receiving openings. An anti-oxidation layer, and the anti-oxidation layer covers the bump pads. β 9. The flip-chip packaging process as described in item 8 of the patent application scope, wherein the resist layer further includes a side wall covering the bump receiving openings. 10. The flip-chip packaging process as described in item 7 of the scope of patent application, wherein before the corresponding columnar bumps of the wafer are correspondingly inserted into the bump receiving openings, they are further included in the carrier and the wafer. Many gaps are formed between them. 1 1. The flip-chip packaging process as described in item 7 of the scope of the patent application, wherein before the columnar bumps of the wafer are correspondingly inserted into the bump-receiving openings, they are further included in the bump-receiving openings. Filled with a conductive adhesive. 12314twf.ptd Page 17 1236743 6. Application for patent scope 1 2. The flip-chip packaging process as described in item 7 of the scope of patent application, wherein the columnar bumps of the wafer are correspondingly inserted into the bump receiving openings Afterwards, the method further includes re-welding the columnar bumps to spheroidize the columnar bumps. 12314twf.ptd Page 18