TWI234857B - Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same - Google Patents
Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same Download PDFInfo
- Publication number
- TWI234857B TWI234857B TW090125968A TW90125968A TWI234857B TW I234857 B TWI234857 B TW I234857B TW 090125968 A TW090125968 A TW 090125968A TW 90125968 A TW90125968 A TW 90125968A TW I234857 B TWI234857 B TW I234857B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- heat dissipation
- layer
- pattern
- bga
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
1234857 五、發明說明(1) 發明領域: 本發明揭露一種有關於B G A ( b a 1 1 - g r i d a r r a y )封裝技 術,特別是指具有散熱層(h e a t s i n k 1 a y e r )的封裝技 術,該散熱層係利用導電貫孔與接地焊錫球(so 1 d ba 1 1 for ground)相連接 ° 景 背 明 發 寸些 尺某 寺 體Μ 整期 }更 6 i者 d C業 元體 晶導 由半 藉’ ,勢 步趨 進成 之已 程, 製本 路成 電位 體單 積低 著降 隨, 小 縮 單為導 ,而接 善,連 改小内 著縮致 顯寸導 得尺, 獲元下 而晶況 此 ,青 因而的 可然增 、。反 度能減 速功不 行的卻 執多件 如更元 例入, ,注能 能以功 性可片 的片曰ea 面晶加 方一增 阻 線 -一彐c 内 與 容。 電兇 生元 寄的 的降 生下 衍現 ,表 此能 因性 , 片 集晶 密使 加是 更都 的, 反加 相增 卻的 線值 為此,為解決上述問題,半導體製造業,除了利用低 阻值的銅導線取代傳統的鋁導線以降低導線阻值,更尋求 低介電常數介電層解決寄生電容的問題。另一具有對成本 與性能有直接且關鍵性影響的即是封裝技術。因為可以想 見當晶片元件增加注入新的功能時,勢必大量增加輸出入 端子以因應和系統之連接,同時晶片的功率消耗與散熱問 題也因此更加突顯。為克服上述問題,即便是新一代的覆1234857 V. Description of the invention (1) Field of the invention: The present invention discloses a packaging technology related to BGA (ba 1 1-gridarray), especially a packaging technology with a heat sink (heatsink 1 ayer). The hole is connected to the ground solder ball (so 1 d ba 1 1 for ground) ° Jingbei Mingfa, some feet, a temple body M full period} more 6 i d C industry element crystal guide from half borrowed, The progress of progress has been made. The unit volume of the electric potential system of the manufacturing system is lower and lower, and the small contraction is the guide, and the connection is improved, and the small internal contraction is reduced to make a significant difference. This is the case. As a result, youth can increase. If you can reduce the speed and do not work, you can implement multiple pieces. For example, if you are more familiar with the example, you can use a functional piece of ea surface crystal plus a resistance-increasing line-as long as it is inside the capacitor. The emergence of the birth of the electric warrior is reflected in the nature of the reason. The chip set is denser to make the addition more uniform. The value of the reverse addition and increase is this. To solve the above problems, the semiconductor manufacturing industry, in addition to using Low-resistance copper wires replace traditional aluminum wires to reduce the resistance of the wires, and a low-k dielectric layer is sought to solve the problem of parasitic capacitance. Another technology that has a direct and critical impact on cost and performance is packaging technology. Because it is conceivable that when chip components are added with new functions, a large number of I / O terminals will inevitably be added to respond to the connection to the system. At the same time, the power consumption and heat dissipation problems of the chip will become more prominent. To overcome these problems, even the new generation of
1234857 五、發明說明(2) 晶封裝技術與球腳陣列(BGA)基板封裝技術也需要加以檢 討0 習知BGA基板封裝製程步驟如下:首先請參考圖一 a形 成TAB貫通孔(sprocket hole)10於基板5之邊界内,TAB貫 通孔1 0,係便利於基板5於輸送帶上之傳輸。基板5可以是 B T、聚醯氨或玻璃纖維強化環氧樹脂等絕緣性基板其中之 一。基板5並壓合一銅8。對T - B G A而言,典型的基板上 都只有一層金屬圖案,銅箔8即是用以定義導線圖案,及 錫球之連接圖案。1234857 V. Description of the invention (2) Crystal packaging technology and ball-pin array (BGA) substrate packaging technology also needs to be reviewed Within the boundary of the substrate 5, TAB through-holes 10 facilitate the transportation of the substrate 5 on the conveyor belt. The substrate 5 may be one of insulating substrates such as B T, polyurethane, or glass fiber reinforced epoxy resin. The substrate 5 is laminated with a copper 8. For T-B G A, there is only one metal pattern on a typical substrate. Copper foil 8 is used to define the wire pattern and the connection pattern of the solder balls.
隨後如圖一 b所示先去毛邊(desmear)、化學拋光等。 接著,形成光阻(未圖示)於銅箔8上,並施以微影程序以 定義圖案。經顯影、烘烤定型後,再以光阻圖案做為蝕刻 罩幕以蝕刻銅箔以形成電導線圖案及/或焊錫球之連接圖 案2 0。最後再剝除光阻。Subsequently, as shown in Fig. 1b, first, demear, chemical polishing and the like are performed. Next, a photoresist (not shown) is formed on the copper foil 8 and a lithography process is performed to define a pattern. After development, baking and setting, the photoresist pattern is used as the etching mask to etch the copper foil to form the electrical wiring pattern and / or solder ball connection pattern 20. Finally remove the photoresist.
隨後,如圖一 c所示,再覆蓋一背膠膜2 5於基板5背 面,用以防止防焊綠漆(solder mask)沾粘。隨後再形成 具絕緣性及防止沾粘焊錫的防焊綠漆 3 0層於銅箔8上。再 經微影程序及顯影步驟將銅箔8焊錫球之連接圖案2 〇上之 防焊綠漆去除。 請參考圖一 d,接著,進行電鍍製程Subsequently, as shown in FIG. 1c, a back adhesive film 25 is covered on the back surface of the substrate 5 to prevent the solder mask from sticking. Subsequently, a layer of solder-resistant green paint 30 having an insulation property and preventing solder sticking is formed on the copper foil 8. After that, the solder mask green paint on the connection pattern 20 of the solder ball of the copper foil 8 is removed through a lithography process and a developing step. Please refer to Figure 1d, and then perform the plating process
用以在鋼箔技上Used in steel foil technology
1234857 五、發明說明(3) 依序形成錄及金膜層35。緊接著,再去除背膠膜25。 請參考圖- e,將基板劃割’隨後,再枯貼一枯著層 42於基板5背®。再對基板核心區域材料切除, 陷區40用以容置晶4。必要時也形成匯流排貫穿孔,及元 件貫穿孔’最後’再將另-銅羯55枯貼於枯著層似,用 :乂 散熱:及BGA基板之支撐。最後,再將銲錫球伽 網板印刷方式形成於金膜層35上。其結果如圖一 f所示。 傳統製程為形成散熱層,需要再將散熱片一 片粘貼上去。因此,不但耗時’且效果有。 5 5係隔著一層絕緣基板盥正面圄莹爲沾+ ε π…、/1 電導線遙對。彳皮此沒:連;圖案層的電源電導線或接地 圖一 g及圖一 h為3Μ公司之方法,3Μ公司 ,麵,,通孔10内利用無電電鍍電鑛方式;= 圖案正面與政熱層導通。不㉟,上述的連接,也並未充分 使圖案層的散熱效果發揮,#竟,連 地之電導線並沒有連接。 电守冰'接 因此,習知技術所製作之BGA基板散熱層效果不佳 5改i ί=ί,$!!用。本發明將提供新的bga基板架 構改善上述問通,並提供對應之製造方法。 1234857 五、發明說明(4) 發明目的及概述: ^ 本發明目的係提供一種改善球腳陣列封裝(B G A )基板 散熱層效率之基板結構及其製造方法。 本赉明之再一目的係應用改善球腳陣列封裝(β G A )基板散 熱層效率之基板結構及其製造方法。 ^ 本發明係揭露一種具有改善球腳陣列封裝(BG A )基板 散熱層效率之基板結構。其中該BGA基板具有單一圖案 層’以連接導線及鍚球。一散熱層結合於基板之另一面 政熱層同時也是接地層,用以分散該BGA基板之接地導電 圖案所需面積,其中該BGA基板之接地銲錫球係利用填滿 導電膠之貫穿孔連接。 、 々本發明的方法是先對基板鑽孔及切割以形成貫通孔與 凹陷區。基板上下兩面各有一不沾膜。次填入導電膠於^ ,孔中,在第一實施例中,先去除一面之不沾膜,以貼合 散熱層於該面上,次利用保留之不沾膜遮蔽基板表面,^ 形成黑氧化層於凹陷區,待去除其餘之一面不沾膜後, 形成一銅箔於基板表面。次利用微影與蝕刻技術在 形成BGΑ圖案,包含導線圖案,與形成焊錫球連接之圖 案。之後再塗佈黑色油墨於散熱層表面,用以絕緣," fG/A圖案面則利用微影技術將防焊綠漆覆蓋於導線圖 最後進订鎳、金膜電鍍及網板印刷連接焊錫球,及將晶片1234857 V. Description of the invention (3) The recording and gold film layers 35 are sequentially formed. Immediately thereafter, the adhesive film 25 is removed. Please refer to Figure-e, cut the substrate ', and then apply a dead layer 42 on the back of the substrate 5®. The material in the core area of the substrate is cut away, and the recessed area 40 is used to receive the crystal 4. If necessary, also form a bus bar through-hole, and the component through-hole ‘finally’ and then attach another-copper 羯 55 to the dry layer, use: 乂 to dissipate heat and support the BGA substrate. Finally, a solder ball gamma screen printing method is formed on the gold film layer 35. The result is shown in Figure 1f. In the traditional process, a heat sink layer is formed, and a heat sink needs to be pasted up. Therefore, it is not only time consuming ', but also effective. 5 The 5 series is separated by a layer of insulating substrate and the front surface is faint as + + ε…, / 1 electric wires are far away. This is not true: Connected; the electrical wires or grounding of the pattern layer are shown in Figure 1g and Figure 1h. The method of 3M company, 3M company, surface, and through-hole 10 uses electroless electroplating method; = pattern front and politics Thermal layer is on. Alas, the above-mentioned connection has not fully exerted the heat dissipation effect of the pattern layer. In fact, the electrical wires to the ground have not been connected. Therefore, the heat dissipation layer of the BGA substrate produced by the conventional technology is ineffective. 5 改 i ί = ί, $ !! The present invention will provide a new bga substrate structure to improve the above-mentioned problem, and provide a corresponding manufacturing method. 1234857 V. Description of the invention (4) Purpose and summary of the invention: ^ The purpose of the present invention is to provide a substrate structure for improving the efficiency of a heat dissipation layer of a ball-foot array package (B G A) substrate and a manufacturing method thereof. Still another object of the present invention is to apply a substrate structure for improving the efficiency of a heat dissipation layer of a ball-foot array package (β G A) substrate and a manufacturing method thereof. ^ The present invention discloses a substrate structure having an improved heat dissipation layer efficiency of a ball-foot array package (BG A) substrate. The BGA substrate has a single pattern layer 'to connect the wires and the ball. A heat-dissipating layer is bonded to the other side of the substrate. The political and thermal layer is also a ground layer to disperse the required area of the ground conductive pattern of the BGA substrate. The ground solder balls of the BGA substrate are connected by through-holes filled with conductive glue. The method of the present invention is to first drill and cut the substrate to form a through hole and a recessed area. There are non-stick films on the upper and lower sides of the substrate. The conductive adhesive is filled in the holes twice. In the first embodiment, the non-stick film on one side is removed first to fit the heat-dissipating layer on the surface. The remaining non-stick film is used to mask the surface of the substrate, and black is formed. The oxide layer is in the recessed area. After removing the remaining surface without sticking to the film, a copper foil is formed on the surface of the substrate. The photolithography and etching techniques were used to form a BGA pattern, including a wire pattern, and a pattern connected to a solder ball. After that, black ink is applied on the surface of the heat-dissipating layer for insulation, and the fG / A pattern surface uses lithographic technology to cover the solder mask with green paint. Finally, nickel, gold film plating, and screen printing are used to connect the solder. Ball and chip
1234857 五、發明說明(5) 安置於凹陷區並作最後晶片,隨後利用引腳與BGA圖案連 接’再注入樹脂封住晶片與引腳等步驟。 本發明之第二實施例中,則是在導電膠注入於貫通孔 後’同時移去上下兩面不沾膜,再將銅箔與散熱層同時貼 合於基板上。次,將銅箔以微影及蝕刻技術形成形成BGa 圖案’然後’在BGA圖案面上貼上一護膜,再形成黑氧化 層於凹陷區後除去護膜。之後的步驟,一如第一實施例所 述。 發明詳細說明: 有鑑於如發明背景所述,習知技術中粘貼於基板之散 熱層,係隔著基板與圖案層相對,因此,可以達到的散熱 效果必定有限。傳統B G A基板即使有連接,例如3 Μ公司的 專利,一片基板也約只有8個利用傳送帶上保留之TAB貫通 孔(sprocket hole)而已,可以增加的散熱效果有限。有 鑑於此,本發明提供一方法,可以解決上述問題。 本發明方法之實施例步驟請參考如圖二a至圖二1所 示 首先请參考圖二a’在基板20 5之兩面各先钻貼一層不 沾膜 (release film)210a、210b。不沾膜係選用與導電 膠不具親和性之薄膜。例如聚乙烯膜(polyethy lene 聚丙烯膜(p〇iyacryiine film)、聚酯膜(PET)或1234857 V. Description of the invention (5) Place it in the recessed area and make the final wafer, then connect the pin to the BGA pattern 'and inject resin to seal the wafer and the pin. In the second embodiment of the present invention, after the conductive adhesive is injected into the through hole, the upper and lower non-stick films are simultaneously removed, and then the copper foil and the heat dissipation layer are simultaneously attached to the substrate. Next, a copper foil is formed by lithography and etching techniques to form a BGa pattern ', and then a protective film is pasted on the BGA pattern surface, and then a black oxide layer is formed in the recessed area to remove the protective film. The subsequent steps are as described in the first embodiment. Detailed description of the invention: In view of the background of the invention, in the conventional technology, the heat dissipation layer attached to the substrate is opposed to the pattern layer through the substrate, and therefore, the heat dissipation effect that can be achieved must be limited. Even if the traditional B G A substrate is connected, for example, the patent of 3M Company, there are only 8 TAB through holes (sprocket holes) reserved on the conveyor belt, which can only increase the heat dissipation effect. In view of this, the present invention provides a method that can solve the above problems. For the steps of the method of the present invention, please refer to FIG. 2 a to FIG. 2. First, please refer to FIG. The non-stick film is a film that has no affinity with the conductive adhesive. Such as polyethylene film (polyethy lene polypropylene film), polyester film (PET) or
1234857 五、發明說明(6) 亞克力樹脂其中之一種皆可。隨後,以C0 2雷射鑽孔,以 形成貫穿孔2 1 5,及切割基板以形成凹陷區2 2 0於基板2 0 5 之中。請注意貫穿孔2 1 5位置係設於預定之接地焊錫球 (solder ball for ground)位置。接著,如圖二 b所示, 將導電膠2 2 5以滾筒印刷方式或刮刀擠入貫穿孔2 1 5内。由 於基板2 0 5上具有不沾膜2 1 0 b,因此只有貫穿孔2 1 5沾附導 電膠2 2 5,而形成如圖二b所示之鉚釘狀。 隨後,以刮板移除高於基板2 0 5表面之導電膠。緊接 著,再去除不沾膜2 1 Oa,保留不沾膜2 1 Ob,結果如圖二c 所示。請參考圖二d,隨後利用熱壓合法,在基板2 〇 5上形 成一較厚之銅、治2 3 0 ’以做為散熱層2 3 0。接著再形成一奪 氧化層2 3 5於凹陷區2 2 0表面,黑氧化層2 3 5係做為隔絕基 板2 0 5和晶片之接觸,同時,也具有增加晶片固定於凸陷 區之中,如圖二e所示。 請參考圖二f,接著,去除不沾膜層21〇b。另一第二 銅癌2 4 0 ’接著壓合於基板2 0 5不具散熱層的一面。以做為 BG A基板之導電圖案層。隨後如圖二g再形成負型光阻 245’並以光罩250 a及2 5 0 b做為微影罩幕,再施以曝光程 序以定義圖案後。再經顯影程序而形成如圖二示之光 阻圖案245c、2 4 5a、2 4 5b。請注意由於散熱層23吐係以 透光之罩幕2 3 0a,因此光阻照光後光阻245c將不會被顯影 去除。而圖案層24 0上除了銲錫球連接之光阻圖案Mg 8外1234857 V. Description of the invention (6) Either acrylic resin is acceptable. Subsequently, a C0 2 laser is drilled to form a through hole 2 1 5, and the substrate is cut to form a recessed area 2 2 0 in the substrate 2 5. Please note that the position of the through hole 2 1 5 is set at a predetermined solder ball for ground position. Next, as shown in FIG. 2b, the conductive adhesive 2 2 5 is squeezed into the through hole 2 1 5 by a roller printing method or a scraper. Since the substrate 2 0 5 has a non-sticking film 2 1 0 b, only the through hole 2 1 5 is adhered with the conductive adhesive 2 2 5 to form a rivet shape as shown in FIG. 2 b. Subsequently, the conductive adhesive above the surface of the substrate 205 is removed by a squeegee. Immediately after that, the non-stick film 2 1 Oa is removed, and the non-stick film 2 1 Ob is retained. The result is shown in Figure 2c. Please refer to FIG. 2d, and then use the hot pressing method to form a thicker copper plate 2 3 0 'on the substrate 2 05 as a heat dissipation layer 2 3 0. An oxide layer 2 3 5 is then formed on the surface of the recessed area 2 0. The black oxide layer 2 3 5 is used to isolate the contact between the substrate 2 05 and the wafer. At the same time, the wafer is also fixed in the recessed area. As shown in Figure 2e. Please refer to FIG. 2f, and then, remove the non-stick film layer 21b. Another second copper cancer 2 4 0 ′ is then laminated on the side of the substrate 2 05 without a heat dissipation layer. As a conductive pattern layer of the BG A substrate. Then, as shown in Fig. 2g, a negative photoresist 245 'is formed again, and the photomasks 250a and 250b are used as the lithographic mask, and then an exposure process is performed to define the pattern. After the development process, photoresist patterns 245c, 2 4 5a, and 2 4 5b shown in FIG. 2 are formed. Please note that since the heat-dissipating layer 23 is covered with a light-transmitting curtain 2 3 0a, the photoresist 245c will not be removed by development after the photoresist illuminates the light. The pattern layer 24 0 is in addition to the photoresist pattern Mg 8 connected by solder balls.
1234857 五、發明說明(7) 並有電導線(c ο n d u c t i V e t r a c e )之光阻圖案2 4 5 b做為蝕刻 罩幕。 請參考圖二I,再以光阻圖案245c、245a、245b為罩 幕’以酸性溶液或電漿蝕刻第二銅箔2 4 〇以形成圖案層 240a。最後再移除光阻圖案245c、245a、245b。 緊接著,如圖二j所示,再以黑色油墨2 5 2塗佈於散熱 層2 3 0上,用以做為絕緣層。請注意形成黑色油墨於該散 熱層之前可選擇性地先在散熱層2 3 〇鍍上鎳層。接著再塗 佈防焊綠漆(solder mask) 2 5 5於圖案層24 0a上。 請參考圖二k,再以光罩圖案2 6 0進行曝光及顯影製 程’以裸露錫球所要連接之銅箔處。最後再以電鍵製程依 序鍍「鎳及金膜」27 0於裸露之銅箔上,其結果如圖二1。 最後將錫球2 8 0以網板印刷方式接種於鍍有金的膜層2 7 〇 上。晶片2 7 5安置於凹陷區2 2 0,並將晶片2 7 0上之接觸墊 以導線引腳2 8 0連接於圖案層2 4 0 a上。最後,再以樹脂2 8 5 將晶片2 7 5及導線包覆而得到如圖二m所示之結構。 上述的製程程序中,部分的步驟是可以更換先後而不 影響最後之結果的。例如,請參考本發明之第二實施例, 如圖三a所示,在將導電膠2 2 5注入貫通孔2 1 5後,即將銅 箔2 4 0及散熱層2 3 0同時壓合於基板2 0 5之兩面。接著,圖1234857 V. Description of the invention (7) Photoresist pattern 2 4 5 b with electric wires (c ο n d u c t i V e t a c e) is used as an etching mask. Referring to FIG. 2I, the photoresist patterns 245c, 245a, and 245b are used as a mask 'to etch the second copper foil 2 4 0 with an acidic solution or plasma to form a pattern layer 240a. Finally, the photoresist patterns 245c, 245a, and 245b are removed. Next, as shown in FIG. 2j, a black ink 2 5 2 is coated on the heat dissipation layer 2 3 0 as an insulating layer. Please note that a black ink may be optionally plated with a nickel layer on the heat sink layer 230 before forming the black ink layer. Then, a solder mask 2 5 5 is applied on the pattern layer 24 0a. Please refer to FIG. 2k, and then perform the exposure and development process with a mask pattern 2 60 to expose the copper foil to which the solder ball is to be connected. Finally, a "nickel and gold film" was plated on the exposed copper foil in order by the key bonding process. The result is shown in Figure 2-1. Finally, the solder ball 2 80 is seeded on the gold-plated film layer 27 by screen printing. The chip 2 7 5 is disposed in the recessed area 2 2 0, and the contact pads on the chip 2 7 0 are connected to the pattern layer 2 4 0 a with a wire pin 2 8 0. Finally, the wafer 2 7 5 and the wires are covered with a resin 2 8 5 to obtain the structure shown in FIG. 2 m. In the above process procedure, some steps can be changed in sequence without affecting the final result. For example, please refer to the second embodiment of the present invention. As shown in FIG. 3a, after the conductive adhesive 2 2 5 is injected into the through hole 2 1 5, the copper foil 2 4 0 and the heat dissipation layer 2 3 0 are simultaneously pressed on Both sides of the substrate 2 0 5. Next, the figure
第10頁 1234857 五、發明說明(9) 氣呵成。不需要將散熱片以一片片的粘著方式粘著於基 板。 4.本發明之散熱層不僅是散熱層同時可作為接地層,因 此,可分散BGA基板圖案層所需要之接地所需之面積。 以上所述僅為本發明之較佳實施例而已,並非用以限 定本發明之申請專利範圍;凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾,均應包含在下述之申請 專利範圍内。例如,上述實施例中散熱層同時可作為接地 層,本發明也可將散熱層同時作為電源層。Page 10 1234857 V. Description of the invention There is no need to adhere the heat sink to the substrate in a piece-by-piece manner. 4. The heat-dissipating layer of the present invention is not only a heat-dissipating layer but also a grounding layer. Therefore, the area required for grounding required by the BGA substrate pattern layer can be dispersed. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. For example, in the above embodiment, the heat dissipation layer can be used as the ground layer at the same time, and the present invention can also be used as the power supply layer.
第12頁 1234857 圖式簡單說明 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述: 圖一 a至圖一 f顯示傳統BGA基板之形成程序,散熱層 與BGA圖案層並沒有連接。 圖一 g至圖一 h顯示另一種習知技術所製作之BGA基 板,基板之BGA圖案層僅藉由TAB貫通孔連接散熱層。 圖二a至圖二1顯示依據本發明之方法,第一實施例所 製作之BGA基板步驟,BGA圖案層中,散熱板藉由貫通孔連 接BGA圖案層之接地焊錫球。 圖二m顯示依據本發明之方法,第一實施例所製作之 BGA基板架構。 圖三a至圖三d顯示依據本發明第二實施例之方法,所 製作之BGA基板步驟,圖示中僅顯示與第一實施例步驟不 同的部分。 圖號對照表: 基板 5 銅猪 8 TAB貫通孔 10 貫穿孔 15 電導線及 /或焊錫球之連接圖案 20 背膠膜 25 防焊綠漆 30 鎳及金膜層 35 凹陷區 40 粘著層 42 焊錫球 45 散熱層 55 基板 205 不沾膜層 210Page 1234857 The diagram briefly illustrates the preferred embodiment of the present invention and will be explained in more detail in the following explanatory text with the following figures: Figures 1a to 1f show the traditional BGA substrate formation process, heat dissipation layer It is not connected to the BGA pattern layer. Figures 1g to 1h show a BGA substrate made by another conventional technique. The BGA pattern layer of the substrate is only connected to the heat dissipation layer through the TAB through hole. Figures 2a to 21 show the steps of the BGA substrate produced in the first embodiment according to the method of the present invention. In the BGA pattern layer, the heat sink is connected to the ground solder balls of the BGA pattern layer through through holes. FIG. 2m shows a BGA substrate structure fabricated according to the method of the present invention in the first embodiment. Figures 3a to 3d show the steps of the BGA substrate manufactured according to the method of the second embodiment of the present invention. Only the parts different from the steps of the first embodiment are shown in the figure. Drawing number comparison table: Substrate 5 Copper pig 8 TAB through hole 10 Through hole 15 Connection pattern of electrical wires and / or solder balls 20 Adhesive film 25 Solder green paint 30 Nickel and gold film layer 35 Depressed area 40 Adhesive layer 42 Solder ball 45 Heat dissipation layer 55 Substrate 205 Non-stick film layer 210
第13頁 1234857 圖式簡單說明 穿 孔 215 凹 陷 區 220 導 電 膠 225 散 熱 層 230 愛 氧 化 層 235 圖 案 層 24 0 > 2 4 0a 光 阻 2 4 5c、 245a、 245b 光 罩 2 5 0 a、 2 5 0b 防 焊 綠 漆 255 望 色 油 墨 252 光 罩 圖 案 260 鎳 及 金 膜 270 晶 片 275 導 線 引 腳 280 樹 脂 285 護 膜 254Page 13 1234857 Simple illustration of perforation 215 recessed area 220 conductive adhesive 225 heat dissipation layer 230 love oxide layer 235 pattern layer 24 0 > 2 4 0a photoresist 2 4 5c, 245a, 245b photomask 2 5 0 a, 2 5 0b Solder mask green paint 255 Permanent ink 252 Mask pattern 260 Nickel and gold film 270 Chip 275 Lead wire 280 Resin 285 Protective film 254
第14頁Page 14
Claims (1)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW090125968A TWI234857B (en) | 2001-10-19 | 2001-10-19 | Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same |
US10/083,105 US6569712B2 (en) | 2001-10-19 | 2002-02-27 | Structure of a ball-grid array package substrate and processes for producing thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW090125968A TWI234857B (en) | 2001-10-19 | 2001-10-19 | Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
TWI234857B true TWI234857B (en) | 2005-06-21 |
Family
ID=36597966
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW090125968A TWI234857B (en) | 2001-10-19 | 2001-10-19 | Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI234857B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109585406A (en) * | 2017-09-29 | 2019-04-05 | 现代自动车株式会社 | Power module for vehicle |
-
2001
- 2001-10-19 TW TW090125968A patent/TWI234857B/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109585406A (en) * | 2017-09-29 | 2019-04-05 | 现代自动车株式会社 | Power module for vehicle |
CN109585406B (en) * | 2017-09-29 | 2023-04-07 | 现代自动车株式会社 | Power module for vehicle |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW571371B (en) | Method for fabricating semiconductor package | |
RU2146067C1 (en) | Organic chip holder for integrated circuits with wire connections | |
JP3201975B2 (en) | Chip carrier module, information processing system and forming method | |
US5198693A (en) | Aperture formation in aluminum circuit card for enhanced thermal dissipation | |
TW201041109A (en) | Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package | |
US7791120B2 (en) | Circuit device and manufacturing method thereof | |
TW200522228A (en) | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof | |
JPS60116191A (en) | Board for placing electronic parts and method of producing same | |
TW445558B (en) | Manufacturing method for cavity-down plastic ball grid array package substrate | |
TW201220457A (en) | Package structure having embedded semiconductor component and fabrication method thereof | |
JP2013115345A (en) | Component built-in substrate, manufacturing method of the same, and component built-in substrate packaging body | |
TWI429043B (en) | Circuit board structure, packaging structure and method for making the same | |
JP7333454B2 (en) | Package substrate based on molding process and manufacturing method thereof | |
TW201611135A (en) | Structure of embedded component and manufacturing method thereof | |
WO2019007082A1 (en) | Chip encapsulation method | |
JP2009016377A (en) | Multilayer wiring board and multilayer wiring board manufacturing method | |
TWI234857B (en) | Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same | |
JP2004071946A (en) | Wiring substrate, substrate for semiconductor package, semiconductor package, and their manufacturing method | |
JP2006013367A (en) | Circuit device and manufacturing method thereof | |
JPH07111379A (en) | Multi-chip module packaging type printed wiring board | |
JP2004006670A (en) | Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus | |
TWI242268B (en) | Ball grid array package substrate structure for improving efficiency of heat sink layer and the manufacturing method | |
CN215266272U (en) | High-radiating-plate-level fan-out packaging structure based on copper foil carrier plate | |
TW571413B (en) | Method of manufacturing BGA substrate with high performance of heat dissipating structure | |
TW515056B (en) | Method for making a build-up package on a semiconductor die and structure formed from the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |