TW515056B - Method for making a build-up package on a semiconductor die and structure formed from the same - Google Patents

Abstract

A method for making a build-up package on a semiconductor die and a structure formed from the same. The method for build-up package comprises: a copper foil with conductive columns is bonded to an encapsulated chip by thermal compression, between thereof there is a pre-curing dielectric film. The dielectric film is cured to form a dielectric layer of a chip build-up package for etching conductive traces from the copper foil.

Description

515056 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a method and a structure for packaging a semiconductor wafer, and more particularly to a method and a structure for enlarging a semiconductor wafer. [Previous technology] In the past, the semiconductor packaging technology first stuck the chip to a substrate, such as a printed circuit board or a lead frame, and then passed the electrical connection steps such as wire bonding or TAB bonding. Then, the chip was packaged with a gel, but With the miniaturization and high density of wafers, a "nip chip" combination technology has been proposed, which first forms a conductive bump on the front of the wafer, then mechanically and electrically combines it with a substrate, and finally encapsulates to form a sealant. However, the thermal expansion coefficients of the semiconductor wafer and the substrate made of plastic (or metal) are different, and it is easy to fail in electrical connection. Although the method of underfill (un (Jerf i 1 1 ing)) is proposed, it is due to time and yield. The consideration cannot be promoted as the basic process of flip chip.%: A packaging method is disclosed in US Patent No. 6, 2 71, 4 6 9 which is a method of manufacturing a multilayer printed circuit board after packaging a chip. The layered manufacturing technology is used to form electrical connection lines to meet the advanced high-density, micro-size chip packaging. As shown in Figure 丨, the manufacturing method is as follows: The front side 10 of the piece 102 is adhered to a protective film 104, and then a mold 112 is formed by molding, which covers the side 114 and the side 116 of the wafer 102, and then tears off the protective glue. Film 104, the sealing compound ii2 and a surface on the same plane as the front surface 106 of the wafer 102, as shown in Figure 2, and then a dielectric layer 118, 126 is formed by a build-up method, and the sealing compound 112 The surface is spin-coated or deposited to form a first dielectric layer 118 made of a material such as silicon nitride, one or five, description of the invention (2) oxidized stone, etc. Laser vias [laser U ing] or photolithography [photol i thography] are used to form through holes [v 丨 a] in the first "electrical layer 11 8", and then, in the first dielectric layer 丨 i 8 A metal layer is formed thereon, and the conductive layer I 2 4 is formed by etching the metal layer with a lithographic development image. Similarly, a second dielectric layer is formed, a hole is formed, a metal layer is formed, and the metal layer is formed later. After the conductive plug 132 and the conductive pad 134, a solder resist 136 is printed, and the solder resist 136 is etched to form an opening and form a solder resist. Electrical bumps 38 are opened in the solder mask 136 to serve as external termination points for the semiconductor's multilayer encapsulation structure. During the manufacturing process, both the dielectric layer and the metal layer in the semiconductor's multilayer encapsulation structure are used. The formation of holes one by one is required for each dielectric layer. In addition, the openings of the through holes in the first dielectric layer φ II 8 and between the holes and the holes are required to be relatively small. Corresponding to the pads 108 of the wafer 102, the conductive lines 124 connected to the wafer pads 108 through the through-holes are very difficult to manufacture, and the thickness of the conductive lines 124 deposited in the through-holes is extremely uneven, which is easy to fail. problem. & [Objective and Summary of the Invention] The main object of the present invention is to provide a half-packing method 'copper-copper box plate with conductive plugs together with-dielectric adhesive film core two: body saving in ΐ = after the dielectric adhesive film' Forming-the second electrical layer with electrical continuity, "P " opening step of the electrical layer, for rapid layer-up packaging. The second object of the present invention is to provide a method for mounting the copper layer with a conductive plug. Sing :, take the body of the film and add a layer of b-board white board with the same dielectric adhesive film hot-pressed to

MDIDO V. Description of the Invention (3) Two-sealed colloid, after thermally curing the dielectric adhesive film, " electrical layer, after repeated thermocompression bonding, can make umn] vertical multilayer dielectric layers to reduce the cost Another object of the invention is to provide a 2nd structure: the first dielectric is passed through the conductive plug to ensure a good electrical connection. Another object of the present invention is to provide a " fabrication, using each layer of dielectric adhesive film has electrical connection, and part of the conductive plug can be plugged directly to the dielectric adhesive film of adjacent layers. The conductive layer and the conductive path 最 f are added to the semiconductor wafer according to the present invention. The layer-encapsulated colloid on which the wafer is carried is then bonded to one of the encapsulants with a hot-pressed square plate and sandwiched therebetween. Adhesive film. When the dielectric adhesive film is cured, a crystalline layer is formed. Preferably, the thermocompression bonding system and the thermally cured isoelectric layer are etched to make the copper foil plate-shaped conductive pads and conductive lines. In addition, Combined with solder balls or pins at the outermost, these conductive plugs can be soldered or plated on copper foil or [Anisotropic Conductive Film, copper posts. The increase of the semiconductor wafer according to the present invention forms a plug-to-bolt with electrical conduction (column on wiring space and strengthens the electrical seal of the semiconductor wafer, and increases the semiconductor wafer electrically connected to the wafer. Several conductive plugs are sealed in layers to achieve mutual column [column on column] pain plugs to achieve circuit distribution in fewer interlayers. The encapsulation method is carried out when a copper foil with a conductive plug is firstly provided with a non-cured solidified dielectric sheet, and one of the encapsulation structures is formed, and then the dielectric can be electrically connected to the layer dielectric of the conductive plug. The conductive pads of the adhesive film are various conductive materials, such as solder paste or anisotropic conductive adhesive (ACF). The packaging structure of the copper foil is mainly composed of

Page 6

J 丄 JUJU J 丄 JUJU 5. Description of the invention (4) A wafer and a bearing system that have the sealant system have:]: sealant and at least-a dielectric film, which is formed on the sealant = exposed solder joint of the wafer, The dielectric adhesive film and the dielectric adhesive film are electrically connected to the conductive plug to pass through the two rc dielectric adhesive films, which are stacked on the surface of the encapsulant, and t, vertically correspond to the dielectric adhesive layer of the adjacent layer. A conductive plug is formed with a circuit layer between the dielectric adhesive films. And [Detailed description of the invention]: Γ: Drawings The invention will enumerate the following embodiment description ..., and ..., one specific embodiment of the invention, and FIG. 3 is a flowchart of a method for increasing the packaging of a semiconductor wafer , Figures 43 to 4} 1 are process cross-sectional views of the layer-encapsulation method. Month: As shown in Figures 3 and 4a, first in the "provide-chip" step 11, the chip 30 is a microprocessor, microcontroller, memory or special-purpose integrated circuit (ASIC) chip. Preferably, it is an advanced wafer with multiple terminals (its I / O number is more than one hundred or more) and high density. The wafer 30 has a front surface 31 (active surface), a back surface 32, and a front surface 31 and a back surface 3 The side surface 3 3 between 2 is formed with a plurality of pads 3 4 on the front surface 31 of the wafer 30. These pads 3 4 may also be combined with bumps or small solder balls. In the step of "colloid" 12, an encapsulation material 40 carrying a wafer 4 30 is formed, which is combined with the wafer 30. The encapsulation 40 has a surface 41 to expose the pads 34 of the wafer 30. 'In the present embodiment, the surface 41 of the sealing compound 40 is formed with a recessed area 4 2' to combine the wafer 3 0 'so that the front surface 31 of the wafer 30 and the sealing compound

JUJO

The method of packaging the wafer 30 is a protective film (not shown in the figure), and the protective film is removed, and another sealing compound is laser-drilled to form a wafer with pre-molding. 30 is adhered to the sealant 40, which is limited to the present invention, and the layer of the sealant 40 is formed in a layer. The surface 41 of / 40 is formed on the same plane. First, the front surface 3 1 of the wafer 30 is adhered to the wafer 30 after the molding or printing is performed to form a sealant. The method is to first bond the pads 34 of the wafer 30, or Pre-mold the sealing compound 40 with the recessed area 42. The above are all feasible methods. The surface 41 which is not local is provided with a dielectric layer and conductivity. As shown in Figures 3 and 4b, Step "13 of the pig plate" The first copper box plate together with the dielectric adhesive film 6G is thermally laminated to the surface of the sealing compound 40. The "first copper box plate 50" has a plurality of corresponding to the wafer pads 34. Guide pins 51. These conductive pins 51 may be various conductive materials and are combined with the first copper fl plate 50, such as solder printed or plated on the first copper pig plate 5 () or solder paste or anisotropic Conductive glue [Anis〇tr〇pic. "Yan"

(Film, ACF) Welded to a metal pillar of a copper foil (such as a copper pillar), which is not thermoset | p, the first chemical film 60 is located on the first copper foil 50 and the sealing compound 4. In between, through the first dielectric adhesive film 60, the first copper foil plate 50 is not in direct contact with the sealing compound 40, and only the conductive plug 51 on the first copper foil plate 50 is in contact with the soldering of the wafer 30. Pad 34, and the first dielectric adhesive film 60 is a β-staged [β-staged] polymer, an uncured thermosetting resin, which can also be referred to as "prepreg" (prepreg), which has a suitable Plasticity and smeltability [fusib 1 e] instead of liquid with high fluidity. During the hot-pressing process, the conductive plug 51 of the first copper box plate 50 passes through the first dielectric adhesive film 60 and is electrically charged. The bonding pad 34 is bonded to the wafer 30 as shown in Figures 3 and 40:

515056 V. Description of the invention (6) 1. In the step of "Adhesive film" 14, the first dielectric adhesive film 60 is heated and cured into a polymer of c P white & [C-staged] to form a first dielectric. Layer 61, which combines the encapsulant 40 and the first copper pig plate 50, and the first dielectric layer 61 is no longer sexual and fusible. Preferably, "thermocompression copper foil plate" 13 steps and ", ， Curing the dielectric adhesive film ”Steps 4 and 4 are performed simultaneously to simplify the manufacturing process, and the first dielectric adhesive film suitable for the steps of simultaneous thermal compression and thermal curing is the second such as epoxy resin [ep〇xy resin] and other polymers], and the prepreg [prepreg] or a nano composite material jnanocomposlte], the heat curing temperature should be consistent with the heat pressing temperature is better. -After inserting the ® 5? Dielectric dielectric film "1 and 4 steps, the conductive plug 5 1 is copper-coated ^" as shown in Figures 3 and M, the "contact etch 50 :: i 成 步骤" use Lithography technology etched the first-copper pig plate 丨 connection correspondence: If the lead line 52 and the lead pad 53, their electrical properties (JV of 3 and 4e) then perform another "Hot-pressed copper pig plate" In step 16, the second copper box plate 70 is bonded to the second dielectric film 6 as described in the 80th to Λth heat. ] ,; layer 61 [that is, the heat-cured first-dielectric adhesive film: the first or the anisotropic conductive adhesive is bonded to the second copper box plate 70; Door technology + 扪: on the board, and on the second, the dielectric adhesive film 80, the first person thunder rubber 2: the second track of the B-stage polymer without the unheat cured second track H series The same adhesive film 80 as the first dielectric adhesive film 60, so that the electrical heart heat of the two = the plug 71 is passed through the second dielectric electrical connection 忒 the lower conductive pad 53 and is electrically coupled to the conductive pad

ΙΗ 515056 5. Description of the invention (7) The plug 51 and the wafer pad 34, as shown in Figs. 3 and 4f, during the process of "thermosetting the dielectric adhesive film" 17, the second dielectric adhesive film 80 is cured. The reaction is a second dielectric layer 81, which can be performed simultaneously with the 16 steps of "hot-bonded steel foil plate", and then the second step of "etching the copper foil plate" 18 is shown in Figures 3 and 4g, so that The second copper foil 70 forms a circuit layer, which includes a conductive pin 71 corresponding to the electrical connection line 72 and the conductive line 73 ′. In this way, according to the characteristics of the product and the degree of circuit distribution, repeatedly execute the " The steps of "thermo-compression copper box board" 16, "thermosetting dielectric film" 17 and "etching copper box board" 18 are continuously stacked to form multiple dielectric layers.

After the completion of the multilayer dielectric layer 61, the "second dielectric layer 81" of "forming the outer termination" 19 is printed to prevent the outermost conductive pads 73 from forming through-hole conductive pads 73 to form a semiconductor pattern. Shown]. After 81, as shown in Figures 3 and 4h, the steps are to use the lithographic imaging technology on the outermost dielectric layer solder layer 91, and combine the pins 92 or solder balls to increase the packaging of these chips. Structure [Such as 4h] In the method of enlarging and encapsulating the semiconductor wafer of the present invention, the conductive plugs 51 and 71 are passed through the β-phase dielectric adhesive films 60, 80, and 5 to be cured by hot pressing. Phase dielectric layers 61 and 81 do not need to be micro-imaged to form through holes [ν ia] to achieve rapid build-up encapsulation. In addition, Curing and etching I, a vertical dielectric layer with column on column can be made. The conductive plug 51a of the same layer has a vertical relationship with the corresponding conductive plug 71a of the adjacent layer [2 shown in Figure 4h]. Reduce the wiring space and strengthen the electrical effect. ', ° Therefore' As shown in Fig. 4h, the layer encapsulation of the semiconductor wafer of the present invention

515056 Description of the 5 'invention (8) The mounting structure includes a piece of colloid 40 for carrying the wafer 30. The sealant 40 has a surface 41 which does not cover the pads 34 of the wafer 30. A surface 41 of 40 is formed with a first dielectric layer 61, and a plurality of conductive plugs 51 are passed through the first dielectric layer 61 and bonded to the pads 34 of the chip 30 to ensure a good electrical connection, and A circuit layer and a second dielectric layer 81 are formed on the first dielectric layer 61, and the second dielectric layer 81 has a plurality of conductive plugs 71, 1 through, and the second dielectric layer 81 is electrically connected to the first dielectric layer 81. A conductive plug of a dielectric layer 61, a part of the conductive plug 51a of the first dielectric layer 61 is in a vertical relationship with the adjacent second 8, "the remaining layer: a dielectric layer with less line Si and the shortest conductive Adding layers under the path * is H2Si :: as defined in the scope of the attached patent application: What is changed 2: Deviating from the spirit and scope of the present invention. ^ The text belongs to the protection scope of the present invention 515056 Brief description of the diagram [Schematic description 1st picture] Figure: Mejiao maps Figures 4a to 4h. Say H provide 14 thermoset U hot press 18 I insect engraved 30 chip 3 3 side 40 sealant 50 first 52 lead 6 0 first 70 second 72 lead exposed waferized dielectric steel foil copper foil body Steel Foil Board Dielectric Adhesive Copper Foil Board Circuit National Patent Wafer Surface Map National Patent Wafer Structure Invented Layer Seal Invented Layer Seal 12 Insulated Film 17 19 31 34 41 51 53 Film 61 71 73 No. 6 No. 271, 469 "Directly layered in a package already packaged" 'A semiconductor wafer after sealing ^ No. 6, 271, 46 9 "Directly layered in a packaged package", a layer of semiconductor wafer Sectional view; ^ a specific embodiment, a flowchart of a semiconductor wafer method; and a specific embodiment, a sectional view of a semiconductor wafer process. Sealed into a sealing compound 13 Hot-pressed copper is only reversed 15 Etched steel foil heat-cured dielectric adhesive film to form the outer end contact front surface 32 Back pad surface 42 Conductive plug conductive pad First dielectric layer conductive plug conductive pad recess Zone 5 1 a conductive plug 71a conductive plug 515056

Schematic illustration on page 13 80 Second dielectric film 81 Second dielectric layer 91 Solder mask 92 Pin 102 Chip 104 Protective film 106 Front 108 Pad 112 Sealant 114 Back 116 Side 118 First dielectric Layer 124 conductive line 126 second dielectric layer 132 conductive plug 134 conductive pad 136 solder mask 138 conductive bump

Claims (1)

[Scope of patent application] 1. Two types of semiconductor wafers with enhanced packaging methods, including: a) f for at least-the wafer 'which has a plurality of solders formed on the front side of the wafer b) = into a colloid to carry the A chip, wherein the sealing compound has a surface, which is a bonding pad on which the chip is exposed; /, C) thermally bonding a steel foil plate and a thermally cured dielectric adhesive film to the surface of the sealing compound, the copper box plate Has a plurality of conductive plugs corresponding to wafer pads, and the dielectric adhesive film is located between the copper foil plate and the sealing compound; d) thermally curing the dielectric adhesive film; and e) etching the copper foil to form a conductive pad electrically connected to the conductive plug. 2. The method for enlarging a semiconductor wafer as described in item 1 of the scope of the patent application, which further comprises the steps of: a, _ f) hot-pressing another copper foil plate and another non-heat-cured dielectric adhesive film To the thermally cured dielectric adhesive film, the copper box board has a plurality of conductive 2 electrically connected to the conductive pad of the thermally cured dielectric adhesive film, and the non-cured dielectric adhesive film is The copper foil and the thermally cured dielectric adhesive & it is electrically connected to the shoulder g) heat curing the dielectric adhesive film; and h) etching the other copper foil to form a conductive pad, The conductive plug. 3. The method of enlarging and encapsulating a semiconductor wafer as described in item 2 of the scope of patent application, wherein steps f, g and h are repeatedly performed to the number of layers of the electro-adhesive film. amt " Page 14 Scope of patent application 4. The method described in item 丨 of the scope of patent application, which further includes the steps of: forming a layer of a thin film, and encapsulating a lead of another steel foil plate. ^ A plurality of solder balls or pins are used in this method as described in Section (j) of the scope of the patent application, wherein the thermal barrier bonding step and the curing layer are added to the package. Simultaneously. Method, wherein the 4b dielectric dolphin film # body-day film is added in an encapsulation layer. 7. Rushen Zhencai II: epoxy resin or nano composite material. The method described in No. 1 of the German Patent Application, wherein the conductive plugs are layered packaging of gold it conductors 4 and 8, and the layered packaging of semiconductor wafers described in item 1 of the patent scope. /, Which further includes solder or anisotropic conductive adhesive (Anisotropic Conductive Film, ACF) to connect the conductive bolt to the copper box board. 9 The method for increasing the packaging of a semiconductor wafer as described in item 1 of the patent claim% Idui] β jf _κι method, wherein the conductive tethers are bonded to the copper foil by electroplating, printing, or soldering. 10. A layered packaging structure for a semiconductor wafer, comprising: a wafer having a plurality of pads on the front side; a colloid for carrying the wafer, and the sealing system having a surface 'which does not cover the wafer A pad; 4l. A first dielectric layer formed on the surface of the encapsulant; and a plurality of conductive pins passing through the first dielectric layer and bonded to the pad of the wafer. 11. The encapsulation structure of a semiconductor wafer as described in item 10 of the scope of the patent application, which includes a second dielectric layer provided on the first dielectric layer. Page 15 515056 6. The second dielectric layer has a plurality of conductive plugs which pass through the second dielectric layer and are electrically connected to the conductive plugs of the first dielectric layer. 1 2. The layered packaging structure of a semiconductor wafer as described in item 11 of the scope of the patent application, wherein a part of the conductive plugs of the second dielectric layer vertically correspond to the conductive plugs of the first dielectric layer. 1 3. The layered packaging structure for a semiconductor wafer according to item 丨 丨 of the scope of the patent application, which includes a circuit layer between the first dielectric layer and the second dielectric layer. 14. One and a half wafers with one adhesive surface, whose multiple dielectric layers are formally connected to 15. If applying for a mounting structure, neighboring dielectrics 16. If applying for a mounting structure, there is no need for it. A layered package structure for a conductor wafer, comprising: 'has a plurality of pads on the front side; a body for carrying the wafer, and the sealing system has a surface-covered, far-side wafer's pad; and an electrical layer, stacked On the surface of the encapsulant, there are a plurality of conductive plugs in each dielectric, which pass through the corresponding dielectric layer to electrify the pads of the chip. The layer encapsulation of the semiconductor wafer described in the patent scope No. 14 is a part of the conductive plugs of a dielectric layer corresponding to the conductive plugs of the phase layer vertically. The encapsulation of the semiconductor wafer described in item 14 of the patent scope also includes a circuit layer, which is located in the adjacent dielectric layer. The encapsulation of the semiconductor wafer of 17 is located in the outermost dielectric, such as applying for a patent. The structure k ′ described in the scope item 14 further includes a solder resist layer. Say Page 16 515056 6. Application for patent scope 1 8. The layered packaging structure of the semiconductor wafer as described in item 14 for patent scope, which further includes a plurality of solder balls or pins, which are located at the outermost dielectric layer . 19. The layered encapsulation structure of a semiconductor wafer as described in item 14 of the scope of the patent application, wherein the surface of the sealing compound forms a recessed area to embed the wafer so that the front side of the wafer and the sealing compound The surfaces are formed on the same plane. 20. The layered encapsulation structure of a semiconductor wafer as described in item 14 of the scope of the patent application, wherein the dielectric layers are epoxy resin or nano-composite material. # Page 17