TWI242268B - Ball grid array package substrate structure for improving efficiency of heat sink layer and the manufacturing method - Google Patents
Ball grid array package substrate structure for improving efficiency of heat sink layer and the manufacturing method Download PDFInfo
- Publication number
- TWI242268B TWI242268B TW90125967A TW90125967A TWI242268B TW I242268 B TWI242268 B TW I242268B TW 90125967 A TW90125967 A TW 90125967A TW 90125967 A TW90125967 A TW 90125967A TW I242268 B TWI242268 B TW I242268B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- pattern
- layer
- heat dissipation
- ground
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
SS 90125967 1242268 五>、發明說明(1) 發明領域 本發明揭露一種有關於BGA(bal:l-grid array)封襄技 術’特別是指具有散熱層(h e a t s i n k 1 a y e r)的封裝技 術’该散熱層包含電源圖案與接地圖案,分別利用導電貫 孔與電源焊錫球(s〇lder ball for power)與接地焊锡球 (solder ball f〇r ground)相連接。 發明背景: 著積體電路製程之進步,藉由晶元(die)整體尺寸 縮小,降低單位成本,已成趨勢,半導體業者更期待某些 方面的性能,例如執行速度、可因此而獲得顯著改善,^ 厂晶片可以注入更多的功能。然而,晶孓尺寸縮小,而為 增加晶片功能,元件卻不減反增的情況下,導致内連接導 線卻相反的更加密集,因此,衍生的寄生電容與内連線阻 值的增加’都是使晶片性能表現下降的元兇。 為此、,為解決上述問題,半導體製造業,除了利用低 阻值的銅導線取代傳統的鋁導線以降低導線阻值,更 低介電常數介電層解決寄生電容的問題。另一具有對 與性能有直接且關鍵性影響的即是封裝技術。因為可以想 見當晶片兀件增加注入新的功能時,勢必大量增加輪出入 端子以因應和系、統之連接,㈣晶片的功率消耗與散熱問SS 90125967 1242268 Fifth, description of the invention (1) Field of the invention The present invention discloses a BGA (bal: l-grid array) sealing technology 'especially refers to a packaging technology with a heatsink 1 ayer'. The heat dissipation The layer includes a power supply pattern and a ground pattern. The conductive vias are respectively connected to a solder ball for power and a solder ball for ground. Background of the Invention: With the advancement of integrated circuit manufacturing processes, the overall size of the die has been reduced to reduce unit costs. It has become a trend. Semiconductor industry is even looking forward to certain aspects of performance, such as execution speed, which can result in significant improvements. ^ Factory chip can inject more functions. However, the size of the crystal is reduced, and in order to increase the chip function, the components are not reduced and increased, which leads to the denser interconnecting wires. Therefore, the increase in the parasitic capacitance and the resistance of the interconnecting wires are both increased. The culprit of the decline in chip performance. For this reason, in order to solve the above problems, in the semiconductor manufacturing industry, in addition to replacing the traditional aluminum wires with low-resistance copper wires to reduce the wire resistance, the dielectric layer with a lower dielectric constant solves the problem of parasitic capacitance. Another technology that has a direct and critical impact on performance is packaging technology. Because it is conceivable that when the chip components are added with new functions, a large number of wheel in and out terminals will be added to respond to the connection between the system and the system.
第6頁 1242268 ---案號 90125%7_车月曰_修正 五、發明說明(2) . 琴也因此更加突顯。為克服上述問題,即便是新一代的覆 晶封裝技術與球腳陣列(BG A )封裝技術也需要加以檢討。 圖一 a至圖一 m,即為習知包含散熱層的a封裝基板 製程。步驟如下:首先請參考圖一a形成TAB貫通孔 (sprocket hole)i〇於基板5之邊界内,TAB貫通孔1〇係便 利於基板5於輸送帶上之傳輸。基板5可以是βτ或玻璃纖維 強化環氧樹脂或聚醯氨等絕緣性基板其中之一。基板5並 塵合一銅猪8。對Τ-BGA而言,典型的慕板上都只有一層金 屬圖案,銅箱8即是用以定義導線圖案,及錫球之連接圖 #隨後如圖一b所示先去毛邊(desmear)、化學拋光等。 f著’形成光阻(未圖示)於銅箔8上,苹施以微影程序以 二f圖案。經顯影、烘烤定型後’再以光阻圖案做為蝕刻 以蝕刻銅羯以形成電導線圖案及/或焊錫球之連接圖 案20。最後再剝除光阻。 :後,如圖一c所示,再覆蓋一背膠膜25於基板5背 且絕綾=^止防焊綠漆(S〇lder mask)沾粘。隨後再形成 二料、旦防止沾粘焊錫的防焊綠漆30層於銅箱8上。再 = =顯影步驟將銅㈣錫球之連接請。上之Page 6 1242268 --- Case No. 90125% 7_Che Yueyue_ Amendment V. Description of the Invention (2). Qin is also more prominent. In order to overcome the above problems, even the new generation of flip chip packaging technology and ball-pin array (BG A) packaging technology need to be reviewed. Fig. 1a to Fig. 1m are conventional a package substrate manufacturing processes including a heat dissipation layer. The steps are as follows: First, refer to FIG. 1a to form a TAB through hole (sprocket hole) i0 within the boundary of the substrate 5. The TAB through hole 10 is convenient for the substrate 5 to be transported on the conveyor belt. The substrate 5 may be one of an insulating substrate such as βτ, glass fiber-reinforced epoxy resin, or polyurethane. The substrate 5 is combined with a copper pig 8 by dust. For T-BGA, there is only one layer of metal pattern on a typical mu board. The copper box 8 is used to define the wire pattern and the connection diagram of the solder ball. Then, as shown in Fig. 1b, first remove the burrs (desmear), Chemical polishing, etc. A photoresist (not shown) is formed on the copper foil 8 and a lithography process is used to pattern the two f patterns. After development, baking and setting ', the photoresist pattern is used as an etching to etch the copper foil to form an electrical wire pattern and / or a solder ball connection pattern 20. Finally remove the photoresist. : After that, as shown in FIG. 1c, a back adhesive film 25 is covered on the back of the substrate 5 and the solder mask (solder mask) is stuck. Subsequently, a second layer of solder resist green paint 30 is formed on the copper box 8 to prevent solder sticking. Then = = the developing step will connect the copper and tin balls please. Kamiyuki
1242268 修正1242268 fix
號 9Q125967 五1發明說明(3) ,進行電鍍製程,用以在鋼箔8上 緊接著,再去除背膠膜25。 一 請參考圖一 d,接著 依序形成鎳及金膜層35 49上參考圖一e,將基板劃割’隨後,再粘貼-粘著; 42於基板5背®。再對基板核心區域材料切除層 陷區40用以容置晶片。必要時 ’、 乂成凹 件貝穿孔,最後,再將另一銅箔冗粘貼於粘著層42上 以做為散熱層及BGA基板之支撐。 用 網板印刷方式形成於金膜層35上最以如將圖== 、,傳統製程為形成散熱層,需要再將散熱片一片接者一 二ί貝ί亡去。因此,不但耗時,且效果有限。因為散熱片 谨2著一層絕緣基板與正面圖案層的電源電導線或接地 電導線遙對。彼此沒有連接。 圖运及圖一 h為3Μ公司之方法,3Μ公司在TAB貫通孔 10形成後,TAB貫通孔10内再利用無電電鏟電鑛方式使基 ^圊案正面與散熱層導通。不過,上述的連接,也並未充 分使圖案層的散熱效果發揮,畢竟,連接電壓之電導線或 接地之電導線並沒有連接。 因此’習知技術所製作之BGA基板散熱層效果不佳 且’且未加以進一步利用。本發明將提供新的BGA基板架 構改善上述問題,並提供對應之製造方法。No. 9Q125967 Description of Invention of May 1 (3), the electroplating process is performed on the steel foil 8 and then the adhesive film 25 is removed. I Please refer to FIG. 1d, and then sequentially form a nickel and gold film layer 35 49. Referring to FIG. 1e, scribe the substrate ′, and then paste-adhere; 42 on the substrate 5 back®. The material-removed layer depression region 40 is further used for accommodating the wafer. When necessary, the recessed part is perforated, and finally, another copper foil is redundantly pasted on the adhesive layer 42 as a support for the heat dissipation layer and the BGA substrate. The screen printing method is used to form the gold film layer 35. The traditional process is to form a heat dissipation layer, and the heat sink needs to be connected one by one. Therefore, it is not only time consuming, but the effect is limited. Because the heat sink has an insulating substrate and the power or ground wires of the front pattern layer are far away. Not connected to each other. Figure 3 and Figure 1h are the methods of the 3M company. After the 3M company formed the TAB through-hole 10, the TAB through-hole 10 uses the electric power shovel and electric ore method to make the front side of the base case and the heat dissipation layer conductive. However, the above-mentioned connection has not fully exerted the heat dissipation effect of the pattern layer. After all, the electrical wires connected to the voltage or the electrical wires connected to the ground are not connected. Therefore, the heat dissipation layer of the BGA substrate produced by the conventional technique is not effective and is not used further. The present invention will provide a new BGA substrate structure to improve the above problems, and provide a corresponding manufacturing method.
1242268 ____案號90125967_ 年月 曰 鉻π: 五·、發明說明(4) 發明目的及概述: 本發明目的係提供一種改善球腳陣列封裝(BGA)基板 散熱層效率之基板結構及其製造方法。 本發明之再一目的係應用貫通孔作為BGA基板圖案層 與政熱層之接地圖案與電源圖案相連接。藉著散熱層之導 通使BGA基板圖案之接地圖案與電源圖秦分散於散熱層, 進而增加導線佈線面積或可減少BG A基板面積。 本發明揭露一種具有改善球腳陣列封裝(BGA)基板散 熱層效率之基板結構及其製造方法。其中該基板具有 單一圖案層,用以做為焊錫球連接與導碜圖案。一散熱層 於基板之另一面,散熱層提供BGA基板之接地,用以 =散該BGA基板圖案層之接地導電圖案所需面積,其令該 BGA基板之接地銲錫球係利用填滿導電膠之貫穿孔連接。 本發明的方法是先對包含 切割以形成貫通孔與凹陷區。 膜。次填入導電膠於貫通孔中 基板之粘貼。待除去不沾膜後 面。次,形成護膜於基板正反 陷區。接著,在去除其餘護膜 銅’自之基板形成貫通孔及 基板上下兩面各有一不沾 ’利用不沾膜防止導電膠與 ,將散熱層粘貼於基板背 表面,再形成黑氧化層於凹 後’利用微影與姓刻技術在1242268 ____ Case No. 90125967_ Chromium π: Five. Description of the Invention (4) Purpose and Summary of the Invention The purpose of the present invention is to provide a substrate structure for improving the efficiency of a ball-foot array package (BGA) substrate heat dissipation layer and a method for manufacturing the same . Still another object of the present invention is to use a through hole as a ground pattern and a power pattern of a BGA substrate pattern layer and a thermal layer. The ground pattern of the BGA substrate pattern and the power supply pattern are dispersed in the heat dissipation layer by the conduction of the heat dissipation layer, thereby increasing the wiring area of the wires or reducing the area of the BG A substrate. The invention discloses a substrate structure with improved efficiency of a heat dissipation layer of a ball-foot array package (BGA) substrate and a manufacturing method thereof. The substrate has a single pattern layer, which is used as a solder ball connection and conductive pattern. A heat-dissipating layer is on the other side of the substrate. The heat-dissipating layer provides grounding of the BGA substrate, and is used to disperse the area required for the ground conductive pattern of the BGA substrate pattern layer. Through-hole connection. The method of the present invention includes first cutting to form through holes and recessed areas. membrane. Fill the substrate with conductive adhesive in the through hole. After removing the non-stick film. Secondly, a protective film is formed in the front and back depression regions of the substrate. Next, after removing the remaining protective film copper, a through hole is formed on the substrate, and there is a non-stick on the upper and lower sides of the substrate. The non-stick film is used to prevent the conductive adhesive and the heat dissipation layer is pasted on the back surface of the substrate. 'Using lithography and surname engraving technology in
第9頁 1242268 --- 案號 90125967_年月日_§r]L____ 五'、發明說明(5^ ^ -------- 銅箱面形成BGA圖案,包含導線圖案,與形成焊錫球連接 之圖案。並且在散熱層上形成接地圖案與導電圖案。之後 再塗佈黑色油墨於散熱層表面,用以絕緣,而B G a圖案面 則利用微影技術將防焊綠漆覆蓋於導線圖案。最後進行 鎳、金膜電鍍及網板印刷連接焊錫球,及將晶片安置於凹 陷區並作最後晶片,隨後利用引腳與BGA圖案連接,再注 入樹脂封住晶片與引腳等步驟。 發明詳細說明: :Page 9 1242268 --- Case No. 90125967_year month day_§r] L ____ Five ', description of the invention (5 ^ ^ -------- BGA pattern formed on the surface of the copper box, including the wire pattern, and the formation of solder The pattern of ball connection. And the ground pattern and conductive pattern are formed on the heat dissipation layer. Then black ink is applied on the surface of the heat dissipation layer for insulation, and the BG a pattern surface uses lithography technology to cover the solder green paint on the wire. Finally, nickel, gold film plating and screen printing are used to connect solder balls, and the wafer is placed in the recessed area and used as the final wafer. Then, the pins are connected to the BGA pattern, and then resin is used to seal the wafer and the pins. Detailed description of the invention ::
有鑑於如發明背景所述,習知技術中粘貼於基板之散 熱層,係隔著基板與圖案層相對,因此,可以達到的散熱 效果必定有限。傳統BGA基板即使有連接,例如3M公司的 專利,一片基板也約只有8個利用傳送帶上保留之貫穿孔 (sprocket hole)而已,可以增加的散勢效果有限。有鑑 於此,本發明提供一方法,可以解決上述問題。 本發明方法之實施例步驟請參考如圖二a至圖二1所 示。首先請參考圖二a。在包含一層銅箔206之基板2 05之 兩面各先钻貼一層不沾膜層(release f i lm)2i〇a、210b。 不沾膜係選用與導電膠不具親和性之薄膜。例如聚乙烯膜φ (ρ ο 1 y e t h y 1 e n e f i 1 m )、聚丙烯膜(p 0 1 y a c r y 1 i n e f i 1 m ) 、聚醋膜(PET)或亞克力樹脂其中之一種皆可。隨後,以 C〇2雷射鑽孔,以形成貫穿孔2丨5,及切割基板以形成凹陷 區2 2 0於基板2 0 5之中。請注意貫穿孔21 5位置係設於預定In view of the background of the invention, in the conventional technology, the heat dissipation layer attached to the substrate is opposed to the pattern layer through the substrate, and therefore, the heat dissipation effect that can be achieved must be limited. Even if the traditional BGA substrate is connected, for example, 3M's patent, there are only about 8 sprocket holes on a substrate, which can increase the scattered effect. In view of this, the present invention provides a method that can solve the above problems. For the steps of the method of the present invention, please refer to FIG. 2a to FIG. 21. Please refer to Figure 2a first. On both sides of the substrate 205 including a layer of copper foil 206, a non-stick film layer (release film) 2ioa, 210b is drilled and pasted. The non-stick film is a thin film that has no affinity with the conductive adhesive. For example, a polyethylene film φ (ρ ο 1 y e t h y 1 e n e f i 1 m), a polypropylene film (p 0 1 y a c r y 1 i n e f i 1 m), a polyester film (PET), or an acrylic resin may be used. Subsequently, a C02 laser is used to drill holes to form through-holes 2 and 5 and cut the substrate to form a recessed region 2 2 0 in the substrate 2 05. Please note that the through-hole 21 5 position is set at the scheduled
第10頁 1242268 案號 90125967 年月曰 Y冬if i、發明說明(6) _之球腳接地(bal 1 - grid for ground)位置及預定之球腳 電源(ball-grid for power)位置。接著,如圖二c所 示,將導電膠225以滾筒印刷方式或刮刀擠入貫穿孔2 15 内。由於基板205上、下兩面分別含不沾膜層2i〇a 、 2 1 0 b,因此只有貫穿孔2 1 5及其附近沾附導電膠2 2 5,而形 成如圖二c所示之鉚釘狀。 IW後’以刮板移除南於基板2 〇 5表面之導電膠。緊接 著,再去除不沾膜層210b, 210a,結> 如圖所示' 請參考圖二e,隨後利用熱壓合法,在基板上形成另 一較厚的銅箔230,以做為散熱層2 3〇。接著, 之銅綱靡層230上各枯貼一護膜‘。。板1 2再°5 •黑乳化層235塗佈於凹陷區22〇表面,黑氧化層235係做為 ,絕基板2 05和晶片(未圖示)之接觸,同時,也具有粘: 晶片並使其固定於凹陷區之功能。 y者 請參考圖二f ’接著,在 熱層230及銅箔206上塗佈备荆丄蔓臈* “別於散 曰 文师負型光阻245再以光罩圖幸 及250b做為微影罩幕,再姑ε I 丹兀早口茶25〇a 立4, 冉&以曝光程序以定義圖案。請、、拿 思,光罩250a的圖案係包含電源圖案/接地圖案。, 1 5 0 b係包含訊號的導線圖宋 " 罩 2 闯案及電源/接地圖案。 1242268 案號 90125967 ^-L· 弓___修正 玄、發明說明(7) 2 45a、245b。在散熱層23 0上之光阻圖案245a,係定義電 源圖案與接地圖案。而銅箔2 〇 6 a上之光阻圖荦2 4 5 b則定義 了信號連接之導電圖案,以及連接焊錫球 地圖案。 隨後以光阻圖案245a、245b為罩幕,施以蝕刻製程。 換言之,利用本發明的方法,可將BGA圖案層中所需之電 源圖案與接地圖案移至散熱層230,由散熱層23〇a去承 擔。而銅箔20 6a只安排訊號層及連接厚錫球必要之圖案即 可。如此,由於訊號導線在基板一面,而接地、及電源等 導電圖塊在基板另一面,不但可縮小整個BGA所需的面 ❶ 積,且也可降低雜訊。 如圖一h所示,將殘留之光阻圖案剝除,隨後再塗佈 黑色油墨252於散熱圖案層23〇&上以做為絕緣層。請注意 形成黑色油墨於該散熱層之前可選擇性地先在散熱層“Μ 鍍上鎳層。緊接著,再塗佈防焊綠漆(s〇ldef mask) 255 於圖案層206a上。 —二參考圖二1,再以光罩圖案260a、26 Ob為罩幕,進 $曝光及顯影等微影程序,以裸露錫球所要連接之銅箔 處。稞露之銅箱206a係用以與電源及接地錫 接 再以防焊綠涑乃g^ ^ ^ +及…色油墨為罩幕,轭以電鍍製程,依序鍍 上錄及金膜層」270其結果如圖二j所示。 1242268 i、發明說明 案號 (8) 90125967 年月曰_修正 請參考圖二k,將錫球以網板印刷方式接種於鍍有金 的膜層上。晶片2 7 5安置於凹陷區2 2 0,並將晶片上之接觸 墊以導線2 80連接於圖案層2〇 6a上。最後,再以樹脂285將 晶片2 7 5及導線包覆而得到如圖所示之結構。 、 本發明具有以下優點: 1 ·將基板上接地及接電源之導電錫球利用貫穿孔盥 熱片連接,因此,有助於散熱。 〜 一月 ,2·上述連接基板正反面之貫穿孔係利用擠入導電膠 方式、’比一般貫穿孔採用電鍍的方式形成方法更加方 其中為防止不需要連接的部分沾上導電膠,係使用不 層防止。因此勿需擔心,銅箱正面沾上不沾膜層。彳、 • 3·由於散熱層係以熱壓合方式將半導體基板上所右曰 •二:氣呵成。不需要將散熱片以一片片的粘著方式粘著: 同時可作為接地圖案 案層所需要之接地 4·本發明之散熱層不僅是散熱層 及電源圖案,因此,可分散BGA基板圖 及電源圖案所需之面積。 -大二上所ί僅為本發明之較佳實施例而6,並非用以I? 定本發明之申請專利笳囹· 儿非用以限 鈐神下所—土、夕發 圍,凡其匕未脫離本發明所揭示之 等效改變或修飾,均應包含在下述 專利範圍内。 π广现之甲晴Page 10 1242268 Case No. 90125967 Y winter if i, description of the invention (6) _ the position of the ball 1-grid for ground and the predetermined position of the ball-grid for power. Next, as shown in FIG. 2c, the conductive adhesive 225 is squeezed into the through hole 2 15 by a roller printing method or a scraper. Since the upper and lower sides of the substrate 205 contain non-stick film layers 2i0a and 2 10b, respectively, only the through hole 2 1 5 and the vicinity thereof are coated with the conductive adhesive 2 2 5 to form a rivet as shown in FIG. 2c. shape. After IW ’, the conductive adhesive on the surface of the substrate 2 05 is removed by a scraper. Then, remove the non-stick film layers 210b, 210a, as shown in the figure. 'Please refer to Figure 2e, and then use hot pressing to form another thicker copper foil 230 on the substrate for heat dissipation. Layer 2 30. Then, a protective film is applied on each of the copper-plated layer 230 ′. . Plate 1 2 ° 5 • Black emulsified layer 235 is coated on the surface of the recessed area 22 °, and the black oxide layer 235 is used as the contact between the insulating substrate 2 05 and the wafer (not shown). The function of fixing it in the recessed area. y please refer to Figure 2f '. Next, apply the coating on the hot layer 230 and the copper foil 206. * "Different from the negative photoresist 245, and then use the photo mask and 250b as micro Shadow mask curtain, εI Danwu early mouth tea 25〇a 4, Ran & use the exposure program to define the pattern. Please, Nath, the pattern of the mask 250a contains the power pattern / ground pattern., 1 5 0 b is a wire diagram containing the signal Song " Cover 2 Breakthrough case and power / grounding pattern. 1242268 Case number 90125967 ^ -L · Bow ___ Correction mystery, invention description (7) 2 45a, 245b. In the heat dissipation layer 23 The photoresist pattern 245a on 0 defines the power supply pattern and the ground pattern. The photoresist pattern on copper foil 2 06 a 荦 2 4 5 b defines the conductive pattern for signal connection and the pattern for connecting the solder balls. The photoresist patterns 245a and 245b are used as a mask and an etching process is performed. In other words, by using the method of the present invention, the required power pattern and ground pattern in the BGA pattern layer can be moved to the heat dissipation layer 230, and the heat dissipation layer 23oa To bear. And the copper foil 20 6a can only arrange the signal layer and the necessary pattern for connecting thick solder balls. The signal wires are on one side of the substrate, and the conductive blocks such as ground and power are on the other side of the substrate, which not only reduces the area required for the entire BGA, but also reduces noise. As shown in Figure 1h, the remaining light The resist pattern is peeled off, and then a black ink 252 is applied on the heat dissipation pattern layer 23 ° as an insulating layer. Please note that before forming the black ink on the heat dissipation layer, the heat dissipation layer “M can be plated with nickel. Floor. Next, a solder mask 255 is applied on the pattern layer 206a. -Refer to Figure 2 and take the mask patterns 260a and 26 Ob as the mask, and then perform lithography procedures such as exposure and development to expose the copper foil where the solder ball is to be connected. The exposed copper box 206a is used to connect to the power supply and grounding tin, and to prevent soldering. The green ink is g ^ ^ ^ + and ... color ink is used as the screen. The yoke is electroplated, and the recording and gold layers are sequentially plated. " The result of 270 is shown in Figure 2j. 1242268 i. Description of the invention Case number (8) Month 90125967 _ Amendment Please refer to Figure 2k, and inoculate the tin balls onto the gold-plated film layer by screen printing. The chip 2 7 5 is disposed in the recessed area 2 2 0, and the contact pads on the chip are connected to the pattern layer 206a with a wire 2 80. Finally, the wafer 275 and the wires are covered with a resin 285 to obtain the structure shown in the figure. The present invention has the following advantages: 1 The conductive solder balls that are grounded on the substrate and connected to a power source are connected by through-hole heat sinks, thus helping to dissipate heat. ~ January, 2 · The through holes on the front and back sides of the connection substrate are extruded with conductive adhesive, which is more elegant than the general method of forming the through holes by electroplating. Among them, in order to prevent parts that do not need to be connected from getting conductive adhesive, it is used. No layers prevent. So don't worry, the non-stick film layer is on the front of the copper box.彳, • 3 · Because the heat-dissipating layer is formed on the semiconductor substrate by thermocompression bonding method • Two: gas. There is no need to stick the heat sink in a piece-by-sheet manner: at the same time, it can be used as the ground pattern for the ground pattern. 4 · The heat sink of the present invention is not only a heat sink layer and a power supply pattern, so it can disperse the BGA substrate map and power The area required for the pattern. -The sophomore is only a preferred embodiment of the present invention and is not intended to be used to determine the patent application of the present invention. Erfei is not used to limit the place of God's undertakings—earth and evening hair. All equivalent changes or modifications that do not depart from the present invention should be included in the scope of the following patents. Jia Qing
12422681242268
_案號 90125967 圖式簡單說明 本發明的較佳實施例將於往後之說明文 圖形做更詳細的闡述: 又予中輔以下列 圖一 a至圖一 f顯示傳統BGA基板之形成程_Case No. 90125967 Brief description of the drawings The preferred embodiment of the present invention will be explained in more detail in the following explanatory texts: Zhongzhong is supplemented with the following Figures 1a to 1f show the formation process of the traditional BGA substrate
與BGA圖案層並沒有連接。 #…I 圖一 g至圖一 h顯示另一種習知技術所製作之bga基 板,基板之BGA圖案層僅藉由TAB貫通孔連接散熱層。土 圖二a至圖二k顯示依據本發明之方法,第一實施例所 製作之BGA基板步驟,BGA圖案層中,接地焊錫球及電源焊 錫球藉由貫通孔而分別連接至散熱板接地圖案層與電源圖 案層。 5 銅箔 8 10 貫穿孔 15 球之連接圖案 20 25 30 錄及金膜層 35 40 枯著層 42 45 散熱層 55 205 銅箔 206 210 貫穿孔 215 220 導電膠 225 圖號對照表 基板 TAB貫通孔 電導線圖案 背膠膜 防焊綠漆 凹陷區 焊錫球 基板 不沾膜層 凹陷區It is not connected to the BGA pattern layer. # ... I Figure 1g to Figure 1h show bga substrates made by another conventional technology. The BGA pattern layer of the substrate is only connected to the heat dissipation layer through TAB through holes. Figures 2a to 2k show the steps of the BGA substrate produced in the first embodiment of the method according to the present invention. In the BGA pattern layer, the ground solder balls and the power solder balls are connected to the heat sink ground pattern through through holes, respectively. Layer and power pattern layer. 5 Copper foil 8 10 Through-hole 15 Ball connection pattern 20 25 30 Recording and gold film layer 35 40 Dead layer 42 45 Heat-dissipating layer 55 205 Copper foil 206 210 Through-hole 215 220 Conductive glue 225 Drawing reference table Substrate TAB through-hole Electrical wire pattern, adhesive film, solder mask, green paint, recessed area, solder ball substrate, non-sticking layer, recessed area
第14頁 2005.10.13.014 1242268 案號 90125967 年 月 曰 修正 —圖式簡單說明 散熱層 230 護膜 232 黑氧化層 235 圖案層 206 光阻24 5c 、245a 、24 5b 光罩 2 5 0a 、25 0b 防焊綠漆 255 黑色油墨 252 光罩圖案 260 鎳及金膜 270 晶片 275 導線引腳 280 樹脂 285Page 14 2005.10.13.014 1242268 Case No. 90125967 Revised—Schematic description of heat dissipation layer 230 Protective film 232 Black oxide layer 235 Pattern layer 206 Photoresistor 24 5c, 245a, 24 5b Photomask 2 5 0a, 25 0b Solder green paint 255 black ink 252 mask pattern 260 nickel and gold film 270 chip 275 wire pin 280 resin 285
第15頁Page 15
Claims (1)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW90125967A TWI242268B (en) | 2001-10-19 | 2001-10-19 | Ball grid array package substrate structure for improving efficiency of heat sink layer and the manufacturing method |
US10/083,105 US6569712B2 (en) | 2001-10-19 | 2002-02-27 | Structure of a ball-grid array package substrate and processes for producing thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW90125967A TWI242268B (en) | 2001-10-19 | 2001-10-19 | Ball grid array package substrate structure for improving efficiency of heat sink layer and the manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
TWI242268B true TWI242268B (en) | 2005-10-21 |
Family
ID=37021515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW90125967A TWI242268B (en) | 2001-10-19 | 2001-10-19 | Ball grid array package substrate structure for improving efficiency of heat sink layer and the manufacturing method |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI242268B (en) |
-
2001
- 2001-10-19 TW TW90125967A patent/TWI242268B/en not_active IP Right Cessation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20080006936A1 (en) | Superfine-circuit semiconductor package structure | |
JP2008270810A (en) | Semiconductor device package for improving functional capability of heat sink, and grounding shield | |
TW200917395A (en) | Semiconductor device and manufacturing method thereof | |
JPH10178028A (en) | Reprocessable assembly for directly fitting chip | |
WO2007063954A1 (en) | Circuit device and method for manufacturing circuit device | |
JP2010245280A (en) | Method of manufacturing wiring board and wiring board | |
CN111029332A (en) | Fan-out type packaging structure with high heat dissipation and electromagnetic shielding performance and preparation method thereof | |
CN104966677A (en) | Fan out type chip package device and preparation method thereof | |
TWI429043B (en) | Circuit board structure, packaging structure and method for making the same | |
JP4058443B2 (en) | Semiconductor device and manufacturing method thereof | |
JP5007164B2 (en) | Multilayer wiring board and multilayer wiring board manufacturing method | |
JP2009016377A (en) | Multilayer wiring board and multilayer wiring board manufacturing method | |
JP2004296562A (en) | Substrate with built-in electronic components, and its manufacturing method | |
TWI242268B (en) | Ball grid array package substrate structure for improving efficiency of heat sink layer and the manufacturing method | |
JP2005019937A (en) | High-density chip scale package | |
JPH1140940A (en) | Structure and method for soldering ball grid array semiconductor package | |
JP2004071946A (en) | Wiring substrate, substrate for semiconductor package, semiconductor package, and their manufacturing method | |
TWI322491B (en) | Bumping process | |
TWI234857B (en) | Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same | |
JP3780688B2 (en) | CSP substrate manufacturing method | |
JP4372434B2 (en) | Semiconductor device and manufacturing method thereof | |
KR20030011433A (en) | Manufacturing method for hidden laser via hole of multi-layered printed circuit board | |
JP2004296565A (en) | Method for manufacturing package for housing semiconductor element | |
TW533518B (en) | Substrate for carrying chip and semiconductor package having the same | |
CN1591805A (en) | Method for mfg. heat reinforced ball grid array IC packaging substrate and packaging substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |