TWI234248B - Method for bonding flip chip on leadframe - Google Patents

Method for bonding flip chip on leadframe Download PDF

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Publication number
TWI234248B
TWI234248B TW093126914A TW93126914A TWI234248B TW I234248 B TWI234248 B TW I234248B TW 093126914 A TW093126914 A TW 093126914A TW 93126914 A TW93126914 A TW 93126914A TW I234248 B TWI234248 B TW I234248B
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Taiwan
Prior art keywords
flip
lead frame
chip
bumps
oxide layer
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TW093126914A
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English (en)
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TW200610111A (en
Inventor
Chien Liu
Meng-Jen Wang
Sheng-Tai Tsai
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Advanced Semiconductor Eng
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Priority to TW093126914A priority Critical patent/TWI234248B/zh
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Publication of TWI234248B publication Critical patent/TWI234248B/zh
Priority to US11/217,573 priority patent/US20060051894A1/en
Publication of TW200610111A publication Critical patent/TW200610111A/zh

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

1234248 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於導線架上覆晶接合（flip Chip bonding on leadframe)技術，特別係有關於一種在導線 架（oxidized ieadi，rame)上覆晶接合方法。 【先前技術】
習知覆晶封裝係將一覆晶晶片（fl ip chip)接合於一 基板（電路板）上，但基於低成本考量，一種低成本封裝方 式係將一覆晶晶片直接覆晶接合於一具有複數個導腳之導 線架（lead frame)上，但由於該覆晶晶片之該些凸塊在回 銲時容易擴散至該導線架之該些導腳之任意位置而使凸塊 潰縮，造成覆晶晶片與導線架之導腳亦過於貼近，導致抵 抗應力之特性衰弱，凸塊易於斷裂。請參閱第1圖，習知 一覆晶晶片1 0係具有一主動面11及一背面丨2，在該主動面 1:1上没有複數個凸塊13，如錫錯凸塊或其它可回銲凸塊， 當該覆晶晶片1 0覆晶接合於一導線架20時，該些凸塊i 3係 被加熱回鮮’以銲接於該導線架2 〇之複數個導腳2丨，然而 由於該些凸塊13具有良好濕潤性，因此容易造成該些凸塊 13擴散至該些導腳21之任意位置，而無法維持該些凸塊13 之覆aa接合南度，導致凸塊潰縮與抗應力特性衰減之問 曰s
^ ° 為了解決此一問題，我國專利公告第49851 7號「具控 制潰縮量功能之導線架及具備該導線架之覆晶型半導體封 裝件」則k出在一供覆晶接合之導線架除了具有多數導腳 之外’另具有一晶片座，該晶片座之高度係大於該些導腳
1234248 五、發明說明（2) 之厚度，以托揮該 之凸塊潰縮量，但 腳上之濕潤擴散區 容易斷裂，此外， 言十 〇 覆晶晶片之主動命 此一方式仍無法界 域，該些凸塊在 該晶片座亦限制了 ’以控制該覆晶晶片 定該些凸塊在該些導 銲後會有頸部型態而 該導線架之導腳設 我國專利公告第540 1 23號 覆晶式半導體封裝件」則揭示 包含戋一覆晶晶片、一導線架 接合於該導線架並以該封膠體 腳在適當處（上表面）設置有一 之端部間形成一銲接區，該覆 该些導腳之銲接區，以防止該 擴散，但該止擋件係為膠片或 該止擋件係為額外裝設於導線 腳在其上表面可供凸塊銲接之 並無防止該些凸塊在回銲時之 塊亦有可能擴散至該些導腳之 會增加該導線架之製造成本及 【發明内容】 以導線架為晶片承載件之 一種覆晶封裝構造，其主要 f 一封膠體，該覆晶晶片係 密封之，其中該導線架之導 止擋件，由該止擔件至導腳 晶晶片之錫鉛凸塊係接合於 些凸塊在回銲時之不當濕潤 以印刷形成之樹脂攔壩，故 架之元件，僅能界定該些導 區域，對於該些導腳之側面 不當濕潤擴散，因此該些凸 侧面，此外，設置該止擋件 對位等問題。 本發明之主要目的係在於提供一種導線架上覆晶接合_ ^其係提供一經氧化處理之導線架’該導線架之複數 導，之上表面係形成有一氧化層，且每一導腳係具有一 ^: Ϊ化1覆蓋之覆晶接合部，當以一覆晶晶片覆晶接合 Μ 線架’一助銲劑（f lux)係形成於該些凸塊並去除在
1234248
ϊ = = = =化層？得該些凸塊能回 導腳之J： ^ μ ί被去除虱化層抑制而不會擴散至該歧 於考t本ϊ明之導線架上覆晶接合方法，其係提供一經氧 处ί之、線架，該導線架係包含有複數個 聊=表面係形成有一氧化層，每一導腳係具有一被： t覆晶接合部；提供一覆晶晶片，繼晶片 1，、有稷數個凸塊，如錫鉛凸塊等可回銲凸塊；形成一助 銲劑（flux)於該些凸塊；當覆晶接合該覆晶晶片至該導線 架時^該助銲劑係去除僅在該些覆晶接合部上之氧化層、， ，利該些凸塊回銲連接於該些導腳之覆晶接合部，並且以 該些覆晶接合部外未被去除之該氧化層抑制該些凸塊擴散 以防止泫些凸塊潰縮，而維持該些凸塊之覆晶。 【實施方式】
參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之導線架上覆晶接合方法，請參閱第2圖， 首先提供一氧化處理之導線架1 1 0，該導線架i丨〇係可供覆 晶接合並經氧化處理而呈黑化或棕化，該導線架丨丨0係包 含有複數個導腳111，每一導腳111係具有一上表面112、 一下表面113以及複數個在該上表面112與該下表面113之 間之側面11 4，在該些導腳1 1 〇之上表面11 2係形成有一包 含有該導線架110金屬成份（Cu)之氧化層116，例如依處理
第9頁 1234248
條件不同，該氧化層116係可為一黑化層或一棕化層，較
ΐ二^ η導腳i11之下表面113與側面114亦形成i該氧 化層11 6，在本貫施例中，該導線架丨丨〇係銅質，可將該導 線架11 0浸泡於一亞氣酸鈉之氧化液之方式或者放置一〃氣 化氣氛之烘烤爐，以形成上述例如氧化銅或氧化亞銅之氧 化層11 6，作為一低成本之導線架保護膜，以取代膠片、 防銲層、樹脂攔壩等外加止擋件，該些導腳丨u係具有一 覆晶接合部1 1 5，其係被該氧化層11 6所覆蓋，在本實施例 中，該些覆晶接合部11 5係被定義在該些導腳1丨丨之内端且 藏於该上表面11 2之氧化層1 1 6下，不需要以特殊形狀或額 外元件界定其區域，此外，該導線架丨丨〇係可不需要晶片 座故可有利於該些導腳1 1 〇之配置設計。
請參閱第3圖，提供一覆晶晶片t 2 〇，該覆晶晶片1 2 〇 係具有一主動面121及一背面122，並具有複數個凸塊 123，如錫鉛凸塊等可回銲凸塊，該些凸塊123係設於該覆 晶晶片1 2 0之該主動面1 2 1 ;此外，在覆晶接合之前，以印 刷或沾塗方式形成一助銲劑130 (flux)於該些凸塊丨23 ,在 本實施例中’該助銲劑130係可為SENJU METAL INDUSTRY 公司提供之Sparkle Flux 385助銲劑，其對於金屬表面氧 化層具有優異之去除功效。請參閱第3及4圖，當覆晶接合 該覆晶晶片120至該導線架110時，在該些凸塊123上之該 助銲劑13 0係先接觸該上表面11 2之氧化層11 6，並快速去 除僅在该些覆晶接合部1 1 5上之氧化層1 1 6，使得該些凸塊 123接合至該些導腳ill之覆晶接合部115，並且以該些覆
第10頁 1234248 五、發明說明（5) f曰接合部11 5外未被該助銲劑丨3〇去除之該氧化層2丨6抑制 該些凸塊1 23擴散以防止該些凸塊丨2 3潰縮，而維持該些凸 塊123之覆晶接合高度。 由於該氧化層11 6對於該些凸塊丨23有抑制擴散效果以 保護該導線架110，且該些凸塊123不會擴散污染至該些導 腳ill之除了該些覆晶接合部115之外之上表面112、側面 11 4與下表面11 3，以達到低成本控制該些凸塊丨23在該導 ，木11 〇上之銲接面積，因此，該些凸塊丨23能在
(I 片⑽與該些導腳U1之間保有足夠的體積而接合良好，並 確保该些凸塊1 2 3抵抗應力之特性。 請參閱第5圖，在覆晶接合之後，可以壓模 (:二卿方式形成-封膠趣，該 封=140係密封該些凸塊123與該覆晶晶叩 = 4，=封膠體140係、密封該些導腳111之上表面 ::114而顯露出該些導腳"κ下表面ιΐ3，以形成一無 加11 〇腳之之矣覆晶-封裝構造’ &外，用該M氧化處理之導線 木11 0之表面氧化層11 6 ’亦可辦你 、、、 體140之結合。 TT、強该導線架110與該封膠
為準本保護範圍當視後附之申請專利範圍所界定者 為準，任何熟知此項技藝者，在 丨疋I 圍内所作之任何變化與修改， =明，精神和範 J屬於本發明之保護範圍。
1234248
圖式簡單說明 【圖式簡單說明】 示意圖； ’一導線架 第1圖·習知覆晶晶片接合於一導線架之戴面 第2圖：依據本發明之導線架上覆晶接合方法 之截面示意圖； 第3圖：依據本發明之導線架上覆晶接合方法， 架上之覆晶晶片之截面示意圖； /導線 第4圖：依據本發明之導線架上覆晶接合方法， 曰 片在覆晶接合於該導線架之後之截面示意圖；及Λ曰曰曰曰 第5圖：依據本發明之導線架上覆晶接合方法， 曰 片在形成一封膠體後之截面示意圖。 ^ Ba曰曰
元件符號簡單說明 10 覆晶晶片 13 凸塊 11 0導線架 111 導腳 11 4 側面 120覆晶晶片 123 凸塊 11 主動面 2〇 導線架 11 2上表面 11 5覆晶接合部 121主動面 1 3 0 助鲜劑 12 背面 21 導— 113 下表面 11 6氧化層 122背面 140封膠體
第12頁

Claims (1)

  1. 六 申請專利範圍. 申晴專利範圍】 包含： 、一種導線架上覆晶接合方法 提供一氧化處理之導線架，該導線架係包含有複數個 導卿，每一導腳係具有一上表面，該些導腳之上表面係形 成有一氧化層，該些導腳係異有一被該氧化層覆蓋之覆晶 Α 议日日 母合部； 提供一覆晶晶片，該覆晶晶片係具有複數個凸塊； 形成一助録劑（f 1 UX )於該些凸塊；及 覆晶接合該覆晶晶片至該導線架，以使該些凸塊係對 應接合於該些導腳之該些覆晶接合部，其中該助銲劑係去 除在該些覆晶接合部上之該氧化層，以利回銲連接該些凸 塊與該些導腳之覆晶接合部。 第1 項所述 為錫鉛凸塊 第1項所述 成一封膝體 第3項所述 顯露出該些 第1 項所述 形成於該些 第1項所述 為一黑化層 苐1 項所述 為一掠化層 2、如申請專利範圍 法’其中該些凸塊係 3 '如申請專利範圍 法，其另包含有：形 4、 如申請專利範圍 法’其中該封膠體係 5、 如申請專利範圍 法’其中該氧化層更 6、 如申請專利範圍 法’其中該氧化層係 7、 如申請專利範圍 法’其中該氧化層係 之導線架上覆晶接合方 〇 之導線架上覆晶接合方 ’以密封該些凸塊。 之導線架上覆晶接合方 導腳之下表面。 之導線架上覆晶接合方 導腳之下表面與娜面。 之導線架上覆晶接合方 〇 之導線架上覆晶接合方
    第13頁 1234248 六、申請專利範圍 8、 一種導線架上覆晶接 一氧化處理之導線架 導腳係具有一上表面，該 層，且該些導腳係具有一 一覆晶晶片，其係具 晶接合至該導線架，以使 之該覆晶接合部； 其中，在該些覆晶接 使該些凸塊回銲連接於該 晶接合部外未被去除之該 9、 如申請專利範圍第8 造’其中該些凸塊係為錫 1 0、如申請專利範圍第8 造，其另包含有一封膠體 11、如申請專利範圍第1 〇 造，其中該封膠體係顯露 i 2、如申請專利範圍第8 造，其中該氧化層更形成 1 3、如申請專利範圍第8 造’其中該氧化層係為一 1 4、如申請專利範圍第8 造，其中該氧化層係為一 合構造，包含： ，其係包含有複數個導腳，每一 些導腳之上表面係形成有一氧化 覆晶接合部；及 有複數個凸塊，該覆晶晶片係覆 該些凸塊係對應接合於該些導腳 合部上之該氧化層係被去除，以 些導腳之覆晶接合部，在該些覆 氧化層係抑制該些凸塊之擴散。 項所述之導線架上覆晶接合構 鉛凸塊。 項所述之導線架上覆晶接合構 ，以密封該些凸塊。 項所述之導線架上覆晶接合構 出該些導腳之下表面。 項所述之導線架上覆晶接合構 於該些導腳之下表面與側面。 項所述之導線架上覆晶接合構 黑化層。 項所述之導線架上覆晶接合構 標化層。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112219637A (zh) * 2020-10-23 2021-01-15 谭虎成 一种导根塑形器及其导根塑形方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8361899B2 (en) * 2010-12-16 2013-01-29 Monolithic Power Systems, Inc. Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing
US20130025745A1 (en) * 2011-07-27 2013-01-31 Texas Instruments Incorporated Mask-Less Selective Plating of Leadframes
JP2014146704A (ja) * 2013-01-29 2014-08-14 Fuji Electric Co Ltd 半導体装置
EP2966677A1 (en) * 2014-07-07 2016-01-13 Nxp B.V. Method of attaching electronic components by soldering with removal of substrate oxide coating using a flux, corresponding substrate and corresponding flip-chip component
JP6653139B2 (ja) * 2015-07-24 2020-02-26 株式会社三井ハイテック リードフレーム及びその製造方法
US11233031B2 (en) * 2015-12-09 2022-01-25 Texas Instruments Incorporated Flip-chip on leadframe having partially etched landing sites
IT201900009585A1 (it) * 2019-06-20 2020-12-20 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3750277A (en) * 1970-10-23 1973-08-07 Texas Instruments Inc Method of making lead frames for semiconductor devices
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
US5459103A (en) * 1994-04-18 1995-10-17 Texas Instruments Incorporated Method of forming lead frame with strengthened encapsulation adhesion
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
EP1796446B1 (en) * 1996-11-20 2011-05-11 Ibiden Co., Ltd. Printed circuit board
US5909057A (en) * 1997-09-23 1999-06-01 Lsi Logic Corporation Integrated heat spreader/stiffener with apertures for semiconductor package
US6510976B2 (en) * 2001-05-18 2003-01-28 Advanpack Solutions Pte. Ltd. Method for forming a flip chip semiconductor package
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
US6780751B2 (en) * 2002-10-09 2004-08-24 Freescale Semiconductor, Inc. Method for eliminating voiding in plated solder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112219637A (zh) * 2020-10-23 2021-01-15 谭虎成 一种导根塑形器及其导根塑形方法

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