TW439238B - Flip chip packaging method for preventing flux from remaining on the conductive bumps by the side of the chip - Google Patents

Flip chip packaging method for preventing flux from remaining on the conductive bumps by the side of the chip Download PDF

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Publication number
TW439238B
TW439238B TW88123390A TW88123390A TW439238B TW 439238 B TW439238 B TW 439238B TW 88123390 A TW88123390 A TW 88123390A TW 88123390 A TW88123390 A TW 88123390A TW 439238 B TW439238 B TW 439238B
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Taiwan
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flux
wafer
conductive bumps
packaging method
chip packaging
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TW88123390A
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Chinese (zh)
Inventor
Wei-Jung Wang
Ching-Shan Jiang
Chi-Jr Shen
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Advanced Semiconductor Eng
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Priority to TW88123390A priority Critical patent/TW439238B/en
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Publication of TW439238B publication Critical patent/TW439238B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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Abstract

The present invention relates to a flip chip packaging method for preventing flux from remaining on the conductive bumps by the side of the chip. In performing an IR reflow to bond the conductive bumps of the chip and the circuit connection points predefined on the substrate in a reflow furnace, the capillary effect of the flux in reflow period is depressed by controlling the wettability of the flux, so as to prevent the flux from climbing along the surface of the conductive bump to aggregate on the side of the chip, which may result in flux remaining on the chip to influence the reliability of the subsequent process. The practical skill is to make the reflow furnace to have an oxygen ratio more than 1000 ppm, and control the density of the solid contents of the flux to be 40 to 75%. Because the ratio of the oxygen in the reflow furnace is increased, the purity requirement for the inert gas (nitrogen) is decreased, thereby the manufacturing cost is reduced.

Description

經濟部智慧財產局員工消費合作杜印製 本發明係關於-種防止在晶片側導電凸塊上殘 劑之覆晶封裝方法m可有效解決晶㈣之導電凸 塊殘留助焊劑並得進—步降低成本之覆晶封裝方法。 按,覆晶封裝方法中包括有一倒裝接合方法(Fi chip bonding),主要係於晶片(7 〇 )表面植設導電凸 塊(Metalb⑽p)(7〇1)(如第二圖入所示),再將晶 片(70)翻面(表面朝下)沾上助焊劑(7〇2)(如 第二圖B所示)後覆設於基板(71)上(如第二圖c所 示),經過回焊作業,使晶片(7〇)表面各導電凸塊( 701)與基板(71)上預設的線路接點(711)接 合。在已知的覆晶封裝製程中,進行回焊作業前,係於晶 片(70)上導電凸塊(701)先沾上助焊劑(7〇2 )(如第二圖B所示),並覆設於基板(71)上,再進 行紅外線回焊(IR refl〇w),以確保導電凸塊 與基板(7 1 )上線路接點(7 1 1 )間良好之焊接性 (Solderabi lity)。而在回焊爐中透過助焊劑反應之導電 凸塊(7 0 1 )表面業已還原,為防止該表面再度氧化, 目前大部分的回焊爐中均配備惰性氣體產生設備,以便在 回焊作業進行時’於回焊爐中充滿惰性氣體,並同時儘可 能保持最低的含氧比例,避免氧化再度發生進而得以確保 晶片(70)之導電凸塊(701)與基板(71)預設 的線路接點之間接合效果。而前述作法雖有助於接合可靠 度(reliability)之提升,但亦衍生嚴重的助烊劑殘留問 題》 3 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -- ‘ K-----------------線 c靖先閱讀背面之注意事項再填寫本頁) A7 B7________ 五、發明說明(少)The present invention relates to a flip-chip packaging method for preventing residues on conductive bumps on the wafer side. The invention can effectively solve the residual soldering flux of conductive bumps on the wafer and make progress. Flip-chip packaging method for reducing cost. According to the flip chip packaging method, there is a flip chip bonding method (Fi chip bonding), which is mainly implanted with a conductive bump (Metalb (p) (701) on the surface of the chip (70) (as shown in the second figure) Then, the wafer (70) is turned over (the surface is facing down) with flux (702) (as shown in the second figure B), and then the substrate (71) is overlaid (as shown in the second figure c). After the reflow operation, the conductive bumps (701) on the surface of the wafer (70) are bonded to the preset circuit contacts (711) on the substrate (71). In the known flip-chip packaging process, before the reflow operation, the conductive bump (701) on the wafer (70) is first coated with a flux (702) (as shown in the second figure B), and Cover on the substrate (71), and then perform infrared reflow (IR refl0w) to ensure good solderability between the conductive bumps and the circuit contacts (7 1 1) on the substrate (7 1) (Solderabi lity) . In the reflow furnace, the surface of the conductive bump (7 0 1) reacted by the flux has been reduced. In order to prevent the surface from being oxidized again, most reflow furnaces are currently equipped with inert gas generating equipment to facilitate reflow operations. During the process, the reflow furnace is filled with inert gas, and at the same time, the lowest oxygen content is kept as much as possible to prevent re-oxidation from occurring, thereby ensuring the predetermined wiring of the conductive bumps (701) of the wafer (70) and the substrate (71). Joint effect between contacts. Although the aforementioned method helps to improve the reliability of the joint (reliability), it also causes serious problems of residual aids. 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)-' K ----------------- line c Jing first read the notes on the back before filling out this page) A7 B7________ V. Description of invention (less)

III!----— — IV · I I-----I I ---I-- (請先閱讀背面之注意事項再填寫本頁) 前述晶片(70)之導電凸塊(701)係在進行回 焊作業前先沾上助焊劑(702)以提升其與基板(71 )之焊接度,此種方式儘管有效’但回烊作業完畢後未完 經濟部智慧財產局貝工消f合作社印製 A7 -----BZ_ 五、發明說明(>) 的毛細現象。 二·回焊爐内氣體之含氧比例過度抑制:在回焊爐中 透過助焊劑反應之導電凸塊表面業已還原並保有其可接合 性’為防止該表面再度氡化,傳統製程中乃刻意壓低回焊 爐中氣體之含氧比例(300~ 1000 ppm),在這種的狀況下 ’即使晶片上導電凸塊與基板上線路接點已完成接合,剩 餘之助焊劑遂利用毛細現象而沿導電凸塊表面向晶片側攀 攸’進而附著聚集於晶片與導電凸塊界面處造成殘留現象 。事實上,過度抑制回焊爐内氣體之含氧比例除將造成助 焊劑殘留問題外’亦使回焊爐中氮氣之消耗量及純度需求 相對提高,而增加了製造成本。 由上述可知’傳統助焊劑免清洗(]Y〇_cleannjng)製程 t基於破保導電凸塊焊接可靠度之需要,而採用低固含物 比重的免清洗助焊劑’並儘量壓低回焊爐中之含氧比例, 惟此舉已造成嚴重的助焊劑殘留於晶片側之問題,故有待 進一步檢討,並謀求解決之道。 因此’本發明主要目的即在提供一種防止助焊劑殘留 於晶片與導電凸塊交界處的覆晶封裝方法,以能有效確保 覆晶封裝物之耐久可靠度。 為達成前述目的採取的技術手段係令前述方法包括有 一選擇免清洗助焊劑而具有高固含物比重之步驟: 一由表面上具導電凸塊之晶片沾附前述免清洗助焊劑 之步驟; 5 本紙張尺度咖㈣@家標準(CNS)A4規格(210 X 297公爱) (請先閲讀背面之注意事項再填寫本頁) 裝 I---- I訂—--------線 叫 923 8 五、發明說明(/ ) . 將郎片以表面具導電凸塊朝下覆設於基板上之步驟 -將覆設晶片之基板送入回焊爐中,並提高爐内氣體 其含氧比例之步驟; 一進行紅外線回焊之步驟; 一不需經助焊劑清洗隨即進行下填膠(underf丨】1)充 填於晶片與基板之間的步驟; 前述方法經提高免清洗助焊劑之固含物比重,可降低 其沾附能力而有助於遲滞毛細作用,又經適度提高回谭作 業中氣體含氧比例,可使原未沾附助焊劑之導電凸境表面 (703)得以氧化,而經氧化之表面將使多餘之助焊劑不易 攀附其上,遂能有效防止其沿導電凸塊表面向上攀爬至晶 片側造成殘留= 前述助焊劑的固含物比重為4〇〜75%。前述回焊作業中 氣體的含氧比例高於WOO pp(n以上β 為使貴審查委員進一步瞭解前述目的及本發明之技 術特徵’茲附以圖式詳細說明如后: (一)圖式部分: 第一圖:係本發明完成回焊步驟後之結構剖視圖。 第二圖Α〜C :係回焊作業的流程示意圖。 第二圖:係晶片完成回焊作業產生助焊劑殘留之示意圖。 (一)圖號部分: (7 0 )晶片 (7 Ο 1 )導電凸塊 (7 0 2)助焊劑 (7 1 )基板 本紙張尺度適用争國國家標準<CNS)A4規樁(210x297公釐) 線 經 濟 部 智 慧 財 產 局 消 費 合 作 钍 印 製 經濟部智慧財產局員工消費合作社印製 3 -: >< w A7 "" ---—87_ 五、發明說明(5-) (703)導電凸塊上未沾附助焊劑之表面 (7 0 4)導電凸塊上已沾附助焊劑之表面 (7 1 1 )線路接點 。有關本發明之技術内容主要著重於覆晶封裝過程中的 回焊(Reflow)製程及相關條件、參數的控制設定,其中 該回焊製程包括有以下步驟: ^ 一沾附助焊劑步騾,係由晶月以表面植設之導電凸塊 沾附削述助焊劑,而沾附高度一般設定於1/3〜1/2之凸塊 尚度為宜,又晶片表面植設導電凸塊為比例呈63/3?的共 晶錫鉛凸塊; ~ 一倒裝接合步驟,係將晶片以表面具導電凸塊朝下覆 設於基板上: 一回焊步驟,係利用紅外線(IR)對基板及其上覆設晶 片進行回焊,以便接合二者並使其構成電氣連接; 一下填膠(underfill)步驟,係於回焊步驟完成後, 不需清洗助焊劑即將膠體注滿於晶片與基板間之空隙。 前述步驟與傳統製程大致相同,且非本發明主要技術 特徵所在,容不進一步詳述各個實施步驟之細節。 又為避免在回焊作業期間,助焊劑沿導電凸塊表面向 上攀爬,以致附著殘留於與晶片表面交界處,故本發明乃 針對回焊作業中的相關條件、參數進行調.整。 首先’在助焊劑(F1 ux)本身部分,以往係採沾附能力 較高的易揮發溶劑’意即該溶劑中的固含物比重極低,因 此提供良好的表面沾附能力狀況下,容易產生毛細現象, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ^ Μ-----------------線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(fe) 為此,可適度的調整助焊劑中所含固含物比重,其可行的 比例範圍為40〜75%,據此可抑制其表面沾附能力。 調整助焊劑固含物比重,主要在降低其沾附能力,如 前揭所述,由於助焊劑活性高、易於揮發,再加上本身具 沾附能力,十分容易產生毛細現象,今若適當的降低其沾 附能力’將有助於避免助焊劑沿導電凸塊表面向上攀爬殘 留至與晶片表面交界處。 除調整助焊劑之固含物比重外,另一防止助焊劑附著 殘留於與晶片表面交界處之解決方案在於:適度的提高回 焊爐中氣體的含氧比例。在既有的回焊爐均可分別控制氮 氣與氧氣之含量’惟在確保焊接可靠度的前提下,均盡可 能的壓低回浑爐中的含氣比例’部分業者甚至將含氧比例 控制至500 ppm以下,在含氧量極低的狀況下,助燁劑呈 現極高度的活性,且易於揮發,因此,雖然能確保晶片與 基板接合良好,但在此狀況下助焊劑即十分容易向上攀附 在晶片表面。今若適度的調高回焊作業環境中之含氧量, 則在助焊劑完成焊接後,較高含氡的環境將使導電凸塊( 70 1)已暴露的表面(7 0 3)易於氧化(請參閱第一 圖所示)’而經氡化之表面(7 0 3 )將使多餘之助焊劑 不易攀附其上,故可使助焊劑停留在導電凸塊) 原先沾塗助焊劑(7 0 2 )的表面(7〇4),而不虞助 焊劑(702)沿著導電凸塊(7〇1)暴露之表面(7 〇 3)向上攀附於晶片侧。 根據實際試驗的结果,前述回焊作業環境中的較佳含 &紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -- - ------1 I ^ ·11!11111 (請先閱讀背面之注意事項再填寫本頁> A7 B7 五、發明說明(7) 氧量為lOOOpptn以上。當含氧量提高時,作業環境中的氮 氣則顯著的降低其消耗量3 經利用前述的技術手段對回焊作業中的相關條件、參 數進行調整後,完成回焊作業的基板與晶片係如第一圖所 不者’晶片(7 0)係以其踢球(7 〇丄)透過助焊劑( 7 〇 2 )與基板(7 1 )上對應的線路接點(7丄丄)接 合;由圖中可明顯看出,該助焊劑(7〇2)只集中在錫 球(7 0 1 )的下球面與基板(7丄)的線路接點(7工 1)之間,並未向上攀爬,或甚至附著於晶片表 面’具體而言,助烊劑(7 〇 2)被控制而停滞在錫球( 701)的1/2球面以下’因此,助焊劑(7〇2)與 曰曰片(7 0 )間仍存在一相當的安全空隙,而有效的對晶 片(7〇)表面構成隔離。 由上述了知本發明採行的技術手段碑實有助於避免 助谭劑殘留於晶片側,並可防止晶片因受助焊劑污染而遭 破壞,雖本發明達成如是卓著之成效,惟前提是晶片與基 板之焊接可靠度並未受是項調整而產生負面影響。 由上述說明可看出本發明之具趙技術手段與原理功效 ,是以該等設計至少具備以下優點: 一·有效解決晶片側殘留助谭劑問題:透過本發明對 回详作業中相關條件之調整改變,可在助輝劑完成助谭目 的後,有效的抑制其活性與揮發現象,藉以在不影響焊接 可靠度的前提下,防止助痒劑向上攀附於晶片表面由於 晶片殘留助焊劑問題不復存在,因而可有效避免其衍生的 本紙張尺度適用__冢標準(CNS)A4_規格⑽x29 - ^ 1--------^---------i (請先閲讀f面之注意事頌再填寫本頁)III! ----— — IV · I I ----- II --- I-- (Please read the precautions on the back before filling out this page) The conductive bump (701) of the aforementioned chip (70) is Before performing the reflow operation, first apply flux (702) to improve the solderability between the substrate and the substrate (71). Although this method is effective, it is not completed after the rework operation is completed. System A7 ----- BZ_ 5. Capillary phenomenon of the invention (>). 2. The oxygen content of the gas in the reflow furnace is excessively suppressed: the surface of the conductive bump that has reacted through the flux in the reflow furnace has been reduced and retains its bondability. To prevent the surface from being re-converted, the traditional process is deliberate Reduce the oxygen content of the gas in the reflow furnace (300 ~ 1000 ppm). Under this condition, even if the conductive bumps on the wafer and the circuit contacts on the substrate have been joined, the remaining flux will be drawn using the capillary phenomenon. The surface of the conductive bump climbs to the side of the wafer, and then adheres to the interface between the wafer and the conductive bump to cause a residual phenomenon. In fact, excessively suppressing the oxygen content of the gas in the reflow furnace not only causes the problem of flux residues', but also relatively increases the nitrogen consumption and purity requirements in the reflow furnace, which increases the manufacturing cost. From the above, it can be known that the “traditional flux no-clean (] Y0_cleannjng) process t is based on the need for reliability of the conductive bump welding, and the low-solid-content no-clean flux is used, and the reflow furnace is as low as possible. The oxygen content ratio, but this has caused serious problems of flux residue on the wafer side, so it needs to be further reviewed and a solution is sought. Therefore, the main purpose of the present invention is to provide a flip-chip packaging method for preventing the flux from remaining at the interface between the wafer and the conductive bump, so as to effectively ensure the durability and reliability of the flip-chip package. The technical means adopted to achieve the foregoing purpose is to make the method include a step of selecting a no-cleaning flux with a high solid content: a step of attaching the no-cleaning flux to a wafer having a conductive bump on the surface; 5 This paper size coffee ㈣ @ 家 standard (CNS) A4 specifications (210 X 297 public love) (Please read the precautions on the back before filling this page) Install I ---- I order ---------- The line is called 923 8 V. Description of the invention (/). Steps of placing the wafer on the substrate with conductive bumps facing down-Send the substrate with the wafer into the reflow furnace, and increase the gas in the furnace. Oxygen-containing step; one step for infrared reflow; one step for filling the wafer and the substrate without flux cleaning without flux cleaning; the foregoing method is improved without cleaning flux The specific gravity of solid content can reduce its adhesion ability and help to delay capillary action, and by appropriately increasing the oxygen content of the gas in the back-to-tan operation, it can make the conductive bump surface of the original unattached flux (703) Can be oxidized, and the oxidized surface will cause excess flux Easy to cling thereto, which then can be effectively prevented from climbing up along the surface of the conductive bumps to the wafer side caused by the residual solids = the specific gravity of the flux composition is 4〇~75%. The oxygen content of the gas in the aforementioned reflow operation is higher than WOO pp (n is greater than β, in order to make your review committee better understand the aforementioned purpose and the technical characteristics of the present invention 'are detailed with drawings as follows: (1) Schematic part : The first diagram: a cross-sectional view of the structure after the reflow step is completed in the present invention. The second diagrams A to C are schematic diagrams of the flow of the reflow operation. The second diagram: the schematic diagram of the flux residue generated by the reflow operation of the wafer. 1) Part of drawing number: (7 0) Wafer (7 Ο 1) Conductive bump (7 0 2) Flux (7 1) Substrate This paper applies the national standard of the country < CNS) A4 gauge (210x297 mm) ) Consumption Cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs 钍 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3-: > < w A7 " " ---— 87_ V. Description of Invention (5-) (703) ) Flux-free surface (7 0 4) on the conductive bump. Flux-covered surface (7 1 1) on the conductive bump. The technical content of the present invention mainly focuses on the control of the reflow process and related conditions and parameters in the flip-chip packaging process. The reflow process includes the following steps: ^ A step of attaching a flux, Jing Yue uses the surface-embedded conductive bumps to attach the cutting flux, and the adhesion height is generally set to 1/3 to 1/2 of the bumps. It is advisable to use the bumps on the surface of the wafer. It is a eutectic tin-lead bump of 63/3 ?; ~ a flip-chip bonding step, the wafer is placed on the substrate with the conductive bump facing down: a reflow step, which uses infrared (IR) to the substrate And the overlying wafer is re-soldered so as to join the two and form an electrical connection; the next underfill step is after the re-soldering step is completed, no cleaning flux is needed to fill the gel to the wafer and the substrate The gap between. The foregoing steps are substantially the same as the traditional processes, and are not the main technical features of the present invention. It is not possible to further elaborate the details of each implementation step. In order to prevent the flux from climbing up along the surface of the conductive bump during the reflow operation, so that the adhesion remains at the interface with the wafer surface, the present invention adjusts and adjusts the relevant conditions and parameters in the reflow operation. First of all, “in the flux itself (F1 ux), in the past, a volatile solvent with high adhesion ability was used” means that the solid content of the solvent is extremely low, so it is easy to provide a good surface adhesion ability. Capillary phenomenon occurs, this paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ^ Μ ----------------- line (Please read the note on the back first Please fill in this page again) A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Note (fe) To this end, the proportion of solids in the flux can be adjusted appropriately, and the feasible ratio range is 40 ~ 75%, which can suppress its surface adhesion ability. Adjusting the proportion of the solid content of the flux is mainly to reduce its adhesion ability. As mentioned earlier, due to the high activity and easy volatility of the flux, coupled with its own adhesion ability, it is very easy to produce capillary phenomena. Decreasing its adhesion ability will help to prevent the flux from climbing up the conductive bump surface and remaining at the interface with the wafer surface. In addition to adjusting the specific gravity of the solid content of the flux, another solution to prevent the flux from adhering at the interface with the wafer surface is to moderately increase the oxygen content of the gas in the reflow furnace. In the existing reflow furnaces, the content of nitrogen and oxygen can be controlled separately. "On the premise of ensuring the reliability of the welding, the gas content in the recirculation furnace is reduced as much as possible." Some operators even control the oxygen content to Below 500 ppm, the flux exhibits extremely high activity under the condition of extremely low oxygen content, and is easy to volatilize. Although it can ensure good bonding between the wafer and the substrate, the flux is very easy to climb up under this condition. On the wafer surface. If the oxygen content in the reflow operation environment is moderately increased today, after the soldering flux is completed, the high hafnium-containing environment will make the conductive bump (70 1) exposed surface (7 0 3) easy to oxidize. (Please refer to the first picture) 'and the hardened surface (7 0 3) will make it difficult for the excess flux to cling to it, so the flux will stay on the conductive bumps. 0 2) surface (704), while the flux (702) climbs up to the wafer side along the exposed surface (703) of the conductive bump (701). According to the results of actual tests, the preferred paper size in the reflow operation environment mentioned above applies to China National Standard (CNS) A4 (210 X 297 mm)-------- 1 I ^ · 11 ! 11111 (Please read the precautions on the back before filling this page> A7 B7 V. Description of the invention (7) The oxygen content is above 1000pptn. When the oxygen content is increased, the nitrogen in the working environment will significantly reduce its consumption 3 After adjusting the relevant conditions and parameters in the reflow operation by using the aforementioned technical means, the substrate and wafer to complete the reflow operation are as shown in the first figure. The wafer (7 0) is based on its kick (7 〇 丄) The flux (7 〇2) is connected to the corresponding circuit contact (7 丄 丄) on the substrate (71); it can be clearly seen from the figure that the flux (708) is concentrated only in tin Between the lower spherical surface of the ball (7 0 1) and the line contact (7 workers 1) of the substrate (7 丄), it did not climb upwards, or even adhered to the wafer surface. 'Specifically, the auxiliary agent (7 〇 2) It is controlled and stagnates below 1/2 spherical surface of the solder ball (701). Therefore, the flux (702) and the wafer (70) are still In a fairly safe space, it effectively isolates the surface of the wafer (70). From the above, it is known that the technical means adopted by the present invention can help to prevent the aid from remaining on the wafer side and prevent the wafer from being damaged. Damaged by flux contamination. Although the present invention achieves such outstanding results, the premise is that the soldering reliability of the wafer and the substrate has not been negatively affected by this adjustment. From the above description, it can be seen that the present invention has the Zhao technology. Means, principle and effect are that these designs have at least the following advantages: 1. Effectively solve the problem of residual tanners on the wafer side: Through the adjustment and change of the relevant conditions in the review operation according to the present invention, the tanner can be completed with the aid of tanners After that, it can effectively inhibit its activity and volatilization, so as to prevent the itching agent from climbing up on the surface of the wafer without affecting the reliability of the solder. Since the problem of residual solder flux on the wafer no longer exists, it can effectively avoid its derived paper. Applicable standards __tsuka standard (CNS) A4_ specifications ⑽x29-^ 1 -------- ^ --------- i (please read the note on the f side before filling out this page)

五、發明說明(s) 破壞晶片情事。 一.降低製造成本:前述回焊作業係在免清洗(N0_ Cl_lng)的製程中進行,所謂免清洗(Heanning)製 程在回焊作業而言,係指完成回焊後不需經過清除助焊 劑步驟’即可維持成品良率,惟當晶片殘留助焊劑的問題 依然存在時,一則必須考慮是否經過清除助焊劑步驟,二 則必須接受成品良率的可能降低;而前述問題均牵涉成本 問題,本發明予以解決後,其製造成本自然可予降低;另 ,值得一提的是:當吾人適度的提高回焊作業環境中的含 氧量’將使惰性氣體的消耗量相對銳減,此亦有助於成本 的降低。 綜上所述’本發明確可獲致前列各項優點,其相較於 傳統製程確已具備顯著功效增進,遂已兼具產業上利用性 及進步性,並符合發明專利要件,爰依法提起申請β (請先閱讀背面之注意事項再填寫本頁) --------訂----- 線 經濟部智慧財產局員X消費合作社印製 10 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公爱)V. Description of the Invention (s) Destruction of the wafer. I. Reduce manufacturing costs: The aforementioned reflow operation is performed in a no-clean (N0_Cl_lng) process. The so-called no-clean (Heanning) process refers to the reflow operation without the need to remove the flux after the reflow is completed. 'You can maintain the yield of the finished product, but when the problem of residual flux on the wafer still exists, one must consider whether to go through the step of removing the flux, and the other must accept the possible reduction in the yield of the finished product; and the aforementioned problems are all related to cost issues. After the invention is solved, its manufacturing cost can naturally be reduced. In addition, it is worth mentioning that: when we moderately increase the oxygen content in the reflow operation environment, the consumption of inert gas will be relatively sharply reduced. Help reduce costs. In summary, the present invention can indeed achieve the aforementioned advantages. Compared with the traditional process, it has achieved significant effects. It has both industrial applicability and progress, and meets the requirements of invention patents. β (Please read the precautions on the back before filling out this page) -------- Order ----- Member of the Intellectual Property Bureau of the Ministry of Online Economics XConsumer Cooperative Co., Ltd. Printed on 10 This paper size applies to Chinese National Standards (CNS) A4 specifications (210x297 public love)

Claims (1)

238 六、申請專利範圍 1 · 一種防止在晶片側導電凸塊上殘留助焊劑之覆晶 封裝方法,其包括有: 一提高助焊劑固含物比重之步驟; 一由晶片表面導電凸塊沾附前述高固含物比重助焊劑 之步驟; —將晶片翻面覆設於基板上之步驟; 一對覆設晶片基板進行回烊作業之步驟。 2 如申請專利範圍第1項所述防止在晶片側導電凸 塊上殘留助焊劑之覆晶封裝方法,該助焊劑的固含物比重 為 40、75%。 1Τ 3 .如申請專利範圍第j項所述防止在晶片側導電凸 塊上殘留助焊劑之覆晶封裝方法,該晶片表面植設導電凸 塊係由比例為63/37的共晶錫鉛凸塊構成B 線 4 .如申請專利範圍第丄項所述防止在晶片側導電凸 塊上殘@助焊社覆晶封裝方法,㈣作業㈣完成後不 需經助焊劑清洗即進行-勝體注滿於晶片與基板間空隙之 下填耀·( under f i 11)步驟。 5.—種防止在晶片側導電凸塊上殘留助焊劑之覆晶 封裝方法’其包括有: Μ 一由晶片表面導電凸塊沾附助焊劑之步驟; 一將晶片表面朝下覆設於基板上之步驟; 一對覆設晶片基板進行Θ焊作業,並提高回焊作 境中爐内氣體含氧比例之步驟。 6.如申請專利範圍第5項所述防止在晶片側導電凸 11 X 297^¾ ) 本紙張尺度剌巾國“準(CNS)A伐格(25 經濟部智慧財產局員工消費合作杜印製 A8 B8 C8 D8 、申請專利範圍 ,上殘留助焊ma封裝方法,回焊作業中爐内氣體含 氧比例為鬲於1000 ppm以上。 7 .如申請專利範圍第5項所述防止在晶片側導電凸 塊上殘留助焊劑之覆晶封裝方法,該晶片表面植設導電凸 塊係由比例為63/37的共晶錫鉛凸塊構成。 8 如申請專利範圍第5項所述防止在晶片側導電凸 塊上殘留助’焊劑之覆晶封裝方法,回焊作業步冑完成後不 需經助焊劑清洗即進行—膠體注滿於晶片與基板間空隙之 下填膠(underfill)步驟。 9 ·—種防止在晶片側導電凸塊上殘留助焊劑之覆晶 封裝方法,其包括有: 一提高助焊劑固含物比重之步驟; 一由晶片表面導電凸塊沾附前述高固含物比重助焊劑 之步驟; 一將晶片表面朝下覆設於基板上之步驟: 一對覆設晶片基板進行回焊作業,並提高回焊作業環 境氣體中含氧比例之步驟。 1 0 .如申請專利範圍第g項所述防止在晶片側導電 凸塊上殘留助焊劑之覆晶封裝方法,該助焊劑的固含物比 重為40〜75%。 1 1 ·如申凊專利範圍第g項所述防止在晶片側導電 凸塊上殘留助焊劑之覆晶封裝方法,回焊作業中該爐内氣 體含氧比例高於10 0 0 ppm以上。 1 2,如申請專利範圍第9項所述防止在晶片側導電 12 木紙張尺度適用中國國家標準(CNS)A4規格(210x297公》 I I — — — — — — — . ! I ---I * IHIIIII ί請先閲讀背面之注意事項再填寫本頁) 醫08 六、申請專利範圍 凸塊上殘留助焊劑之覆晶封裝方法,該晶片表面植設導電 凸塊係由比例為63/37的共晶錫錯凸塊構成9 1 3 ’如申請專利範圍第9項所述防止在晶片侧導電 凸塊上殘留助焊劑之覆晶封裝方法,回焊作業步驟完成後 不需經助焊劑清洗即進行一膠體注滿於晶片與基板間空隙 之下填膠(underfill)步驟。 (請先閱讀背面之注意事項再填寫本頁) ^--------^---- II 1 I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用申國國家標準(CNS)A4規格(210 X 297公« )238 6. Application Patent Scope 1 · A flip-chip packaging method for preventing the flux from remaining on the conductive bumps on the wafer side, comprising: a step of increasing the specific gravity of the flux solid content; a sticking of the conductive bumps on the surface of the wafer The aforementioned step of high solid content specific gravity flux;-the step of flipping the wafer over the substrate; the step of rewinding a pair of wafer substrates. 2 As described in item 1 of the scope of the patent application, a flip-chip packaging method for preventing the flux from remaining on the wafer-side conductive bumps, the solid content of the flux is 40, 75%. 1T 3. A flip-chip packaging method for preventing flux from remaining on the conductive bumps on the wafer side as described in item j of the scope of the patent application. The conductive bumps on the surface of the wafer are eutectic tin-lead bumps with a ratio of 63/37. The block constitutes the B line 4. As described in item (1) of the scope of the patent application, the method of preventing residues on the conductive bumps on the wafer side is used to help the chip-on-chip packaging method. It is filled with the under fi 11 step under the gap between the wafer and the substrate. 5. A flip-chip packaging method for preventing the flux from remaining on the conductive bumps on the wafer side, which includes: Μ a step of attaching the flux to the conductive bumps on the wafer surface; a wafer surface facing down on the substrate The above steps; a step of performing a Θ soldering operation on a pair of overlying wafer substrates and increasing the oxygen content of the gas in the furnace in the reflow operation. 6. Prevent conductive bumps on the wafer side as described in item 5 of the scope of patent application 11 X 297 ^ ¾) This paper size is printed on the national standard "CNS" A Vague (25 Intellectual Property Bureau, Ministry of Economic Affairs, employee consumption cooperation Du printed A8 B8 C8 D8, patent application scope, upper residual flux encapsulation method, the oxygen content of the gas in the furnace during reflow operation is more than 1000 ppm. 7. Prevent conduction on the wafer side as described in item 5 of the patent application scope Chip-on-chip packaging method for residual flux on bumps, the conductive bumps planted on the surface of the wafer are composed of eutectic tin-lead bumps with a ratio of 63/37. 8 Prevent on the wafer side as described in item 5 of the scope of patent application The flip-chip packaging method for the residual flux on the conductive bumps, after the reflow operation step is completed, it is performed without flux cleaning-the gel is filled under the gap between the wafer and the substrate underfill step. 9 · A flip-chip packaging method for preventing the flux from remaining on the conductive bumps on the wafer side, comprising: a step of increasing the specific gravity of the solid content of the flux; Solder step A step of placing the wafer surface downward on the substrate: a step of re-soldering a pair of overlying wafer substrates and increasing the oxygen content of the ambient gas in the reflow operation. In the flip-chip packaging method for preventing the flux from remaining on the conductive bumps on the wafer side, the proportion of the solid content of the flux is 40 to 75%. 1 1 · Preventing on the wafer side as described in item g of the patent application scope Chip-on-chip packaging method for residual flux on conductive bumps, the oxygen content of the gas in the furnace during reflow operations is more than 100 ppm. 1 2. Prevent conduction on the wafer side as described in item 9 of the scope of patent applications. 12 Wood paper scales are applicable to Chinese National Standard (CNS) A4 specifications (210x297) II — — — — — — —.! The scope of the patent application is a flip-chip packaging method of residual flux on the bump. The conductive bumps on the surface of the wafer are composed of eutectic tin fault bumps with a ratio of 63/37. 9 1 3 ' On the wafer-side conductive bumps For the flip-chip packaging method of residual flux, after the reflow operation step is completed, a colloid is filled under the gap between the wafer and the substrate without the need for flux cleaning. (Please read the precautions on the back first (Fill in this page again) ^ -------- ^ ---- II 1 I Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size applies to the national standard (CNS) A4 (210 X 297) «)
TW88123390A 1999-12-31 1999-12-31 Flip chip packaging method for preventing flux from remaining on the conductive bumps by the side of the chip TW439238B (en)

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