1234220 九、發明說明： 本發明係關於一種裝置及方法以偵測應力轉移性質及特別是 關於一種裝置及方法以偵測最後裝設於產品相關外框的半導體模 組的應力轉移性質。 、 “積體電路一般以許多經圖案化金屬化或互連平面製造，這些 平面由介電中間絕緣層彼此電隔離。為實現在該經圖案化金屬化 j互連層之間或互連層與基材之間的電連接，一般稱的接觸洞或 貫孔在經選擇位置被形成於該絕緣層。 ,就提出集成密度而論，為實現改良的性能特徵如增加的速度 及ΐ加ί電路功能性每單位面積，該特徵尺寸及特別是該接觸洞 或貫孔變得愈來愈小，基於此原因，他們變得愈來愈特別易於受 到一般稱的應力轉移。 ^與一般稱的電子轉移相反，電子轉移為互連材料的質體輸送 係因存在的直流電及特別是在非常高的電流密度而產生。於本發 明所敘述的應力轉移係關於特顧機械應力或應力梯度而在互^ 層或接觸洞產生的質體傳送。此種機械應力源自如互連層或位於 之間的絕^體層與其他傳導及非傳導巾間層的熱膨縣數之不匹 =及不同彈性模數的不匹配，於是，導致類似的物質傳輸，依壓 縮或拉伸應力或交替應力而定，此引触電傳導材射空隙的形 成’其結果為在轉體餘的互連之電阻被增加或甚至互連 可能發生。 若-種製造方法被考慮，做為實例，其中，在於半導體基材 或介電層上所形成互連層⑷、銅等）上，進—步絕緣體層如藉由 CVD方法(化學氣相沉積)在度㈤溫度被沉積，在該互連層及相 鄰絕緣層間不_膨脹係數已彳丨起機械應力，其如做為拉伸應 力，產生在該互連層的應力轉移。在以Gu貫孔賴金屬化的情況 下，如因熱不匹配所產生的應力梯度魅空穴成為貫孔之傳送（空 1234220 隙之形成）。 更精確說，為減少在該互連層的應力能量的空穴擴散，其結 果為，在特定時間後，一般數月或數年，在該互連層或貫孔的此 質量傳送產生空隙，其影響該半導體模組的電子性質及可甚至導 致互連的中斷。 、 弟1A至1C顯示間化的區段圖以說明债測應力轉移性質之習知 裝置。 、 根據第1A圖，特徵化互連及特別是在積體電路或半導體模組 1C的金屬化的上述應力轉移性質的可靠度檢查被直接在晶圓或在 該晶圓位準上進行。在此情況下，形成於半導體模組1(：的各種應 力轉移測試結構SMT的電阻在固定間隔被測量（如每小時、每天或 每週一次)及與起始值的偏差被評估。在這些測量間，晶圓被儲存 於溫度超過150度C的爐子，其結果為這些可靠度檢查的期間可被 顯著減少至約1000至2000小時以涵蓋約15年的產物使用壽命。 然而，在此種型式測試裝置的情況下，缺點為所得到結果完 全為不足的因缺乏在外框的最後裝設，及在此方面，無法具在接 近該產物的環境的半導體模組的應力轉移性質的足夠準確價測。 根據第1B圖，此種型式的測試依此亦可於最後裝設的測試外 框TG進行，半導體模組1C藉由接合電線或焊接連接b被裝設於模組 載體T ’例如，熱穩定陶瓷測試外框被用做外框。雖然以此方式可 能不僅偵測及評估該半導體模組1C的内部應力σ。亦债測及評估由 該裝設或該焊接連接Β及該測試外框TG的模组載體τ所引起的應力 〇TG ’此種型式的檢查結果再次不產生在具產品外框的半導體模組 的互連系統之應力轉移性質的正確敘述，特別是因與產品相關外 框偏差的該測試外框TG。 進一步地，根據第1C圖，要被檢查的半導體模組π亦可再次 猎由焊接連接B及模組載體T被植入於產品相關塑膠外框g，但在此 1234220 =况下所產生的問題區域為在相對應加熱至大於150度c的溫度Te 能下，圍繞互連系統的層之熱不匹配引起在產品相關應力狀 =的變化，基於此原因，關於在以此方式封裝的半導體模組1C之 亦轉私性貝的正確敘述未被獲得。此外，該外框G的塑膠組合物 解或軟化，其結果為由此塑膠外框G的所引起的應力同樣地造 成減少的應力σ/。 產’、、:而'又有這些大於150度C的高溫，其較佳為由外部加熱eh ，此種型式的可靠度檢查無法被經濟地進行，因為他們會花 賈數月及常是甚至數年。 彦。Γίί，本發哪基於提供—鐵置及方法以伽彳最後裝設於 =相關外框的半導體模組的應力轉移性質之目的，由此，應力 ，生質的足夠準確評估在相當短的時間被獲得。 Μ 徵及ίίΐΐΓ ’此目的係藉由中請專利範圍第1項關於裝置的特 敌及精由申請翻細第η棚於方法的方法達到。 層的力τ測赌構包括至少—個形成於第一互連 至少-個形成於互料=成連於接 模組，力轉，質的高程度測i值，關於在半導體 區域二灣積及/或該第二互連 大於為互連s域的表面及/或體積，其結果為已知 1234220 的配置，可靠度檢查的時間期間的進一步顯著 穴的數：相對地絲面的應力及在體積内可擴散的空 計重ii—應力轉移性質的檢查期間的測量準確性及統 =由多測試結構可能具多重的第-及第二互連區 猎由夕重連魏域以連財讀此連接。 互連=連==被形成為在該至少-個第-或第二 區域。要被檢查的結構之;別、J!J力流電流經該加熱互連 轉移的影響====制’及電子 關於偵測應力轉移性質的方、去，卓又机“日寸 加執f置及^二9f外框’及最後加熱電流被施用於該整合 施用於該應力轉移測試結構及流經該 $構 = «。以此方式’對第—次，該相對應應力皮 本U進-步有利細特徵化於進—步子 文。本發日肢麻難體實施淑參考相__細敘述於下 第調赫裝置的難_賴崎職 考數字表示與在第1A至1C圖的元件相同 <對 貝相问翏 於下文被免除。 謂應的轉且重複敘述 根據第2圖，根據本發明特徵化在最 外框G封裝後的半導體模組IC(積體電路)的=轉:在=相關 金屬化）的可靠度檢查被進行。 ％、專移丨生貝（特別是 在一議覆晶外框G之情況下，特別是，機械應力在半導體 1234220 基 於此原因，它們構成增加的可靠度風險。盔法 估的此種影響係根據第2圖被跡藉由整:於該ί導二 2轉_^試結構餅具崎喊是直接鄰近於其輕合加熱裝 感f直接進般稱的塊材材料的屈服應力之區域， 置IH，其可就地地產生大於15(^C的内部溫度Τι，於是，外^ 可為如在T:T_的操作溫度，其低於至多15G度G_膠相容溫^ 以此種方式，用於產品相·齡_膠材料可以不被改變 於該半導__仙及亦於該模組載或該焊接連接^ 球B及以不被改變的方式於該半導體模組亿引起它們的相對應機 械應力cjg。而且，在該應力轉移測試結構SMT外部，在該半導^材 料或電線連接及/或絕緣體層駐要基本應力轉在不被改變的 值⑺，使得可由該應力轉移測試結構SMT偵測的應力或者該相 應力(J結果為： σ=σ〇+σ〇 该應力轉移測試結構SMT的就地加熱至大於150度(:的!^依然可 藉由整合加熱裝置ΙΗ產生，在自225度C至300度C的範圍之溫度較 佳為被設定。以此方式，關於最後裝設於產品相關外框的半導體 模組1C的應力轉移性質之敘述可在相當短的時間被進行，如1〇〇至 2000小時。 與爐子中具產品相關外框G的半導體模組ic之習知儲存相 反，該外框應力狀態以一種不欲的方式流動被改變，如此才可能 第一次進行近似產品的測試以特徵化特別是積體電路的，金屬化的 應力轉移性質。 第3Α圖顯示一種簡化平面視圖及第3Β圖顯示根據第3Α圖的根 據第一示例具體實施例以偵測應力轉移性質的裝置沿區段卜！的 透視區段視圖，再次相同參考符號表示相同或對應的元件且重複 敘述於下文被免除。 1234220 根據第3A及3B圖，該應力轉移測試結構SMT在第一互連層或金 屬，平面L1具兩個第-互連區域}，其以具相當大表面之導體板形 成最適地以接收機械應力及/或形成或提供空穴的體積。三個第二 互連區域2形成於第二互連層或金屬化平面L2，該_藉由在 稱的接觸孔洞或貫孔的連接區域3將該第一互連區域j彼此電^ 接，因此該連接區域3經由在位於該互連層u&L2i間的第一絕緣 層II之相對應接觸孔洞或貫孔連接該第一及第二互連區域丨及2: 、為改良該應力轉移測試結構SMT的敏感性，至少該第一互連區 域1的表面及/或體積顯著大於該連接區域3的表面及/或體積，其 結果為由應力轉移所引_物質傳輸，或者 遠^ 域3的空隙作用。因應力轉移結果而形成的空隙以在該連接m 的V表示（空隙）。 在依據根據第3A及3B圖的第-示例具體實施例的該應力 =結構SMT中’該第-互連區域丨具較該第二互連區域織著為大 的表面及/或體積，在此情況下，該第二互連區域亦可具相對應的 大的表面及/或體積。然而，在所說明的示例具體實施例中，該第 -互連區域錢著地適合舰於概敘述_部加齡置。 根據第财_，該應力轉侧試結構SMm是包括 及許多第二互連區域2,其藉由許多連接區域似連鎖方 連接’該連鎖結構產生_在半導體餘應力轉移性質的 統计重要性之進一步改良。 、 就地加熱該應力轉移測試結獻_目的，在根據第3a 崎施例中’以互連結構型式的整合加熱裝 接區域3^ 一互連區域1及該第二互連區域2或該連 導體據第3細’做為實例’以曲折型式結構化的 MWIH1軸於低於該第—互連區和的第二互連層^及在該 10 1234220 流電或直流魏/DC。 °加熱衣置麗的加熱電流可為如交 成，1由裳根，^圖’上方整合加熱裳置IH2亦可於互連層L3形 可再次以曲折型式結構化。在此情況下，加 ί流電方整合加錄置IH1的情況下相同的方式藉由直或 曰夕幸=為:該整合加熱裝置IH1及IH2具多晶半導體材料及特別 以相同方式被使用。在該下方及上方内部加熱裝置皿及 ⑽斤Λ生的溫度一般高於15G度c及較佳為在自225度㈤⑽度。 楚二又feu ’其絲為該應力轉移可被最適地加速，制是在該 牲=連區域1，且不需在會引起在該半導體模組1c的應力α及 特別由此轉外框㈣所引起的應力關顯賴化之方法。 特別疋§使用石夕做為該半導體模組ic的半導體材料時，石夕的 :的熱傳導性質產生觸的局部加熱，其僅受限於直接在該應力 轉移測試結構SMT附近的非常小的區域。 =4Α圖顯示簡化平面視第4β_示沿在第侧根據第二 具體實施例以彳貞測應力轉移性f的裝置之區段π—η的簡化透視 固相同參考符號表示與在第3Α及3Β圖的元件相同或對應於之元 件且重複敘述於下文被免除。 ^ 根據第4Α及4Β圖，該應力轉移測試結構再次具與根據第一示 例體貝把例的该應力轉移測試結構相同的結構，但是現在該整 合加熱裝置直接形成於該應力轉移測試結構SMT上或其内。更精確 也”兒，根據弟一具體貫施例的該加熱裝置具内部加熱互連區域π 於"亥至少第一互連區域1或該第二互連區域2或該連接區域3，加熱 11 Ϊ234220 件，且加熱電獄較佳為具高交流電組 :=二電:度轉移’此電子轉移會損壞在所 以連，勤7 _就储㈣倾域歧接施用於 娀？，t ^ 應力轉御m結構smt的最外則二互連區 4第#別是£它們的相當小表面及/或體積的 二二^域的城明結構化及已知該相同型式的互連材料 ir錄ΐ加熱原則上在該第二互連區域2發生，及該第一互連 區或1鮮父貝獻該加熱，而是經由熱傳導被加熱。 情況’造成連接的中斷。因 鏟銘根f第侧’空隙ν再一次因在特別是在該連接區域3的應力 ^以此方式發生，若合適，造成該電導性的懸，或者在極端 弟一不例具體實施例，加熱 ^流亦流㈣賴區域3 ’該加熱電就隸可能不包含任何直^ 電組件，以避免因電子轉移造成的損害。 …第5圖顯不根據第二不例具體實施例應力轉移測試結構厦的 ，化平面涵，相同參考魏再絲讀在第級姻的元件相同 或對應之元件且重複敛述於下文被免除。 在此情況下’根據第5圖的裝置基本上對應於根據第二示例具 體貫施例的裝置，_部加齡置職切成⑽應力轉移測試 結構内或做為其一部份。 然而’與第4Α及侧相反，現在此不域整個應力轉移測試 結構SMT載有加熱電流AC及由此經由焦耳加熱之情況，❿是僅位於 該第-互連區域1間的第二互連區域2藉由連接區域Α被連接至該 加熱電H。結果’该結構僅在位於該第_互連區域1間的此第二 互連區域2被加熱’其絲為誕接區域或貫孔⑽電載人可被避 免。因足夠的熱傳導，這些直接相鄰的互連區域3由下方或第二互 12 1234220 連層L2被足夠地加熱’使得足夠加速的應力轉移被得到，該加熱 電流AC應再-次儘可能不包含任何直流電組件以避免因 造成的損害。 、分別触於半輯歡㈣互連或金屬化·可湘做個別 互連層及連接區朗材料，在此情;兄下，制是銅及/或銘可被用 做互連層的材料及銅、鋁或鎢可被用做連接區域的材料。 關於偵測最後裝設於產品相關外框的半導體模組的應力轉移 性質之方法，假設魏上述具直接在附近形成的它們個^内部加 熱裝置’或者整合加絲置的應力轉移結構形成_半導體 組，該半導體模組後續被裝設於模組載體τ，其較佳為構成覆晶外 框的導線架，之後’該產品相·框較佳為藉_膠射出成型方 法而形成’及之後該塑膠被冷卻及硬化，該實際可靠度檢 最後裝設狀態進行。在此情況下，首先加熱電流被制於雜二 加熱裝置及進-步’為啦該半導體模組的應力轉移性 二 於該應力轉移測試結構及流經該應力轉移測試結二 以此方式，加熱電流的施用及測量電壓的施用可被 ^或者暫雜齡驗行，纽制朗試方法及加速的進一 少间I Ci 而 框 ^明已基於封裝於覆晶外框的半導體模組被敛述於上，秋 ，本舍明秘於此及_同方式包括所有進_ 陽、 。以相同方式，該應力轉移測試結構不限於 =卜 是以相同方式包括所有替代型式及結構，在，而 内或直接在其附近的整合加熱裝置產生就^。轉移如結構 【圖式簡單說明】 轉移性質之 第1Α至1C圖顯示簡化的區段視圖以說明偵 習知裝置及習知方法。 力 13 1234220 第2圖顯示簡化的區段視圖以說明偵測最後裝設於產品相關 外框的半導體模組的應力轉移性質之裝置及方法。 第3A圖顯示根據第一具體實施例裝置的簡化平面視圖以債 應力轉移性質。 、、 第3 B圖顯示根據第3 A圖沿區段I -1裝置的簡化透視圖。 第4A圖顯示根據第二具體實施例裝置的簡化平面視 應力轉移性質。1234220 IX. Description of the invention: The present invention relates to a device and method for detecting stress transfer properties and, in particular, a device and method for detecting stress transfer properties of a semiconductor module finally installed on a relevant frame of a product. "Integrated circuits are generally manufactured with a number of patterned metallized or interconnected planes, which are electrically isolated from each other by a dielectric intermediate insulating layer. In order to achieve this or between the patterned metallized interconnect layers The electrical connection with the substrate is generally called a contact hole or a through-hole is formed in the insulating layer at a selected position. In terms of the proposed integration density, in order to achieve improved performance characteristics such as increased speed and increase The circuit functionality per unit area, the characteristic dimensions and especially the contact holes or vias have become smaller and smaller, and for this reason they have become more and more susceptible to stress transfer in general terms. In contrast to electron transfer, mass transfer of electron transfer to interconnected materials is caused by the existence of direct current and especially at very high current densities. The stress transfer described in the present invention is based on special consideration of mechanical stress or stress gradient. Interstitial layer or contact hole generated mass transmission. This mechanical stress comes from, for example, the interconnection layer or the insulation layer between it and other conductive and non-conductive interlayers of thermal expansion counts = and Mismatch with the modulus of elasticity, which results in similar material transport, depending on the compressive or tensile stress or alternating stress. The formation of the voids induced by this electrically conductive material will result in the interconnections in the rest of the body. Resistance may be increased or even interconnection may occur. If a manufacturing method is considered, as an example, in which an interconnect layer (such as an interconnect layer (⑷, copper, etc.) formed on a semiconductor substrate or a dielectric layer) is further advanced If the CVD method (chemical vapor deposition) is deposited at a temperature of ㈤, the mechanical coefficient of the expansion coefficient between the interconnect layer and the adjacent insulating layer has been generated. If it is used as a tensile stress, it is generated in the The stress transfer of the interconnect layer. In the case of Gu through hole metallization, if the stress gradient generated by the heat mismatch, the cavities become the transmission of the through hole (the formation of the empty 1234220 gap). More precisely, it is The hole diffusion of the stress energy in the interconnect layer is reduced. As a result, after a certain time, generally months or years, voids are generated in this mass transfer in the interconnect layer or via, which affects the semiconductor mode. Electronic properties Leading to the interruption of the interconnections. 1A to 1C show interstitial block diagrams to illustrate a conventional device for measuring the nature of stress transfer of debt. According to Figure 1A, the interconnections are characterized and especially in integrated circuits or semiconductors. The reliability check of the above-mentioned stress transfer properties of the metallization of the module 1C is performed directly on the wafer or at the wafer level. In this case, various stress transfer test structures SMT formed in the semiconductor module 1 (: The resistance is measured at regular intervals (such as hourly, daily, or weekly) and the deviation from the starting value is evaluated. During these measurements, the wafer is stored in an oven with a temperature of more than 150 degrees C. The results are these The period of the reliability check can be significantly reduced to about 1000 to 2000 hours to cover a product life of about 15 years. However, in the case of this type of test device, the disadvantage is that the results obtained are completely insufficient due to the lack of a frame The final installation, and in this respect, the stress transfer properties of the semiconductor module in an environment close to the product cannot be measured with sufficient accuracy. According to Figure 1B, this type of test can also be performed on the test frame TG installed last. The semiconductor module 1C is mounted on the module carrier T 'by bonding wires or soldering connections. For example, thermally stable A ceramic test frame was used as the frame. Although it is possible to detect and evaluate not only the internal stress σ of the semiconductor module 1C in this way. Also test and evaluate the stress caused by the installation or the solder connection B and the module carrier τ of the test frame TG. TG 'This type of inspection results again do not produce a semiconductor module with a product frame. The correct description of the stress transfer properties of the interconnect system, especially the test frame TG due to product-related frame deviations. Further, according to FIG. 1C, the semiconductor module π to be inspected can also be re-installed by soldering the connection B and the module carrier T into the plastic frame g of the product, but in this case 1234220 = The problem area is the change in the product-related stress state = caused by the thermal mismatch of the layers surrounding the interconnect system at a temperature Te energy corresponding to a temperature greater than 150 degrees c. For this reason, regarding semiconductors packaged in this way, The correct narrative of Module 1C is also not available. In addition, the plastic composition of the outer frame G is decomposed or softened, and as a result, the stress caused by the plastic outer frame G similarly causes a reduced stress σ /. There are high temperatures above 150 ° C, which are preferably externally heated. This type of reliability check cannot be performed economically because they take months and often even Years. Yan. Γίί, the present is based on the provision-iron installation and method for the purpose of stress transfer properties of the semiconductor module that is finally installed on the = relevant frame, so that the stress and biomass can be evaluated accurately enough in a relatively short time given. Μ 征 and ίίΐΐΓ ′ This objective is achieved by applying the first item of the patent application on the characteristics of the device and the essence of the method by applying the method of fine-tuning the nth shelf. The force τ measurement structure of the layer includes at least one formed in the first interconnection and at least one formed in the interconnect = connected to the connection module, the force transfer, and the high-quality measurement of the i value. And / or the second interconnect is larger than the surface and / or volume of the interconnect s domain, the result is a known configuration of 1234220, the number of further significant cavities during the time of the reliability check: the stress on the ground surface and Empty weights that can be diffused in the volume ii—Measurement accuracy and uniformity during the inspection of stress transfer properties = Multiple test structures may have multiple first and second interconnected areas Read this connection. Interconnection = connection == is formed in the at least one-th or second area. The structure to be inspected; Do not, the influence of the J! J force current flowing through the heating interconnect ==== system 'and the electronic method for detecting the nature of stress transfer. The f frame and the 9f frame 'and the last heating current are applied to the integration applied to the stress transfer test structure and flow through the $ struct = «. In this way' for the first time, the corresponding stress U Advance-step is advantageous and characterized in advance-step-by-step. The reference phase of the implementation of the Japanese paralysis paralysis body __ detailed description of the difficulty in the lower tone device _ Lai Qi vocational examination digital representation and in Figures 1A to 1C The components of the same < Beijing phase will be waived in the following. The repetition and repeated description According to the second figure, according to the present invention, the semiconductor module IC (integrated circuit) packaged in the outermost G package is characterized. = Turn: in = relevant metallization) reliability checks were performed.%, Special move 丨 green shell (especially in the case of a flip chip frame G, in particular, mechanical stress in the semiconductor 1234220 for this reason, they This poses an increased reliability risk. This effect estimated by the helmet method is traced by adjusting according to Figure 2: The guide structure 2 turns _ ^ The test structure cake is called directly adjacent to the area of the yield stress of the block material, which is directly adjacent to its light-weight heating feeling f. If IH is set, it can generate more than 15 in situ. (^ C's internal temperature Tm, so the outer temperature can be the operating temperature as at T: T_, which is lower than at most 15G degrees G_ gum compatible temperature ^ In this way, it is used for product phase The material may not be changed in the semiconducting semiconductor and the module or the solder connection ^ B and the corresponding mechanical stress cjg in the semiconductor module 100 million in a way that is not changed. Moreover, Outside of the stress transfer test structure SMT, the basic stress at the semiconducting material or wire connection and / or insulator layer is changed to a value that is not changed, so that the stress detectable by the stress transfer test structure SMT or the The corresponding force (J result is: σ = σ〇 + σ〇 The stress transfer test structure SMT is heated in place to more than 150 degrees (:! ^ Can still be generated by the integrated heating device 1Η, from 225 degrees C to 300 The temperature in the range of degree C is preferably set. In this way, regarding the final installation outside the product The description of the stress transfer properties of the semiconductor module 1C can be performed in a relatively short time, such as 100 to 2000 hours. In contrast to the conventional storage of semiconductor module ic with a product-related frame G in the furnace, this external The stress state of the frame is changed in an undesired manner, so that it is possible for the first time to perform an approximate product test to characterize the stress transfer properties of the integrated circuit, especially the metallization. Figure 3A shows a simplified plan view and Fig. 3B shows a perspective section view of the device according to Fig. 3A according to the first embodiment of the embodiment for detecting stress transfer properties. The same reference symbols denote the same or corresponding components and are described repeatedly below. Was exempted. 1234220 According to Figures 3A and 3B, the stress transfer test structure SMT is on the first interconnect layer or metal, and the plane L1 has two -interconnect areas}, which is formed optimally by a conductor plate with a relatively large surface to receive the machinery Stress and / or volume forming or providing voids. The three second interconnection regions 2 are formed on the second interconnection layer or the metallization plane L2, and the first interconnection regions j are electrically connected to each other by the connection regions 3 called the contact holes or through holes. Therefore, the connection region 3 connects the first and second interconnection regions via corresponding contact holes or through holes of the first insulating layer II between the interconnection layer u & L2i and 2: to improve the stress transfer. To test the sensitivity of the structure SMT, at least the surface and / or volume of the first interconnect region 1 is significantly larger than the surface and / or volume of the connection region 3, and the result is a material transfer induced by stress transfer, or a distant region 3 void effect. The void formed as a result of stress transfer is represented by V at the connection m (void). In the stress = structure SMT according to the first-example specific embodiment according to FIGS. 3A and 3B, the “the first-interconnected area” has a larger surface and / or volume than the second interconnected area, and In this case, the second interconnection region may also have a correspondingly large surface and / or volume. However, in the illustrated example embodiment, the -interconnected area is suitable for landing on the ship. According to the first financial report, the stress transfer side test structure SMm includes and many second interconnecting regions 2 which are connected by many connecting regions like a chain. The chain structure produces statistical significance of the property of semiconductor residual stress transfer. Further improvement. 2. The in-situ heating of the stress transfer test is provided for the purpose of “integrated heating of the mounting area 3 in the form of an interconnect structure in the embodiment according to the 3a-Ki 3 ^ an interconnect area 1 and the second interconnect area 2 or the The MWIH1, which is a zigzag-type structure of the conductor according to the third detail, is taken as an example. The MWIH1 axis is lower than the first interconnecting area and the second interconnecting layer ^ and the current is 1234220 galvanic or DC Wei / DC. ° The heating current of the heating clothes can be as follows, 1 is from the root, and the integrated heating clothes IH2 can be shaped on the interconnect layer L3. It can be structured in a zigzag pattern again. In this case, the same way as in the case of the integration of the galvanic side and the installation of IH1 is straight or said. For the integration heating devices IH1 and IH2 have polycrystalline semiconductor materials and are used in the same way. . The temperature of the internal heating device and the heating device at the lower and upper sides is generally higher than 15G degrees c and preferably at 225 degrees. Chu Erfei's wire is that the stress transfer can be optimally accelerated, and the system is in the region = 1, and does not need to cause the stress α which will cause the semiconductor module 1c, and especially the outer frame. The resulting stress depends on the method used. In particular, when using Shi Xi as the semiconductor material of the semiconductor module IC, Shi Xi's thermal conduction properties cause local heating, which is limited only by a very small area directly near the stress transfer test structure SMT. . Figure 4A shows the simplified plane view 4β_ shows the simplified perspective of the section π-η along the side according to the second embodiment of the device for measuring stress transferability f according to the second specific embodiment. Elements in the 3B diagram are the same or correspond to elements and repeated descriptions are omitted below. ^ According to Figures 4A and 4B, the stress transfer test structure again has the same structure as the stress transfer test structure according to the first example, but now the integrated heating device is directly formed on the stress transfer test structure SMT Or within. More precisely, according to a specific embodiment of the heating device, the internal heating interconnection area π is heated at least at the first interconnection area 1 or the second interconnection area 2 or the connection area 3. 11 Ϊ 234,220 pieces, and the heating electric prison is preferably a high AC power group: = Secondary electricity: degree transfer 'This electronic transfer will be damaged, so Qin 7 _ on the storage and dumping area divergence applied to 娀?, T ^ stress The outermost part of the transfer structure is the second interconnection area. The other is their relatively small surface and / or volume. The structure of the city and the known types of interconnection materials are recorded. ΐHeating occurs in principle in the second interconnecting area 2 and the first interconnecting area or 1 is provided with the heating, but is heated via heat conduction. The situation 'causes the interruption of the connection. The side gap ν occurs again due to the stress ^ especially in the connection area 3, which, if appropriate, causes the conductivity to hang, or in extreme embodiments, the heating flow also flows Lai area 3 'The heating power may not contain any direct electrical components to avoid power Damage caused by transfer.… Figure 5 shows the structure of the stress transfer test structure according to the second embodiment. The same reference is made to the same or corresponding element read by Wei Zaisi in the first marriage and repeated. The following is exempted. In this case, the device according to FIG. 5 basically corresponds to the device according to the second embodiment, which is cut into the stress transfer test structure or made part of it. However, in contrast to Section 4A and the side, now the entire stress transfer test structure SMT does not carry the heating current AC and is thus heated via Joules. It is the second one located only between the first-interconnect area 1. The interconnection region 2 is connected to the heating electrode H through the connection region A. As a result, the structure is heated only in the second interconnection region 2 located between the _th interconnection region 1 and its wire is a junction region or Through-holes can be prevented from carrying people. Due to sufficient heat conduction, these directly adjacent interconnecting areas 3 are heated sufficiently from below or the second mutual layer 12 2420, so that sufficiently accelerated stress transfer is obtained, which Heating current AC should -As far as possible, do not include any direct current components to avoid the damage caused by them.. Touch the semi-series interconnection or metallization. Kexiang can make individual interconnection layers and connection area materials, in this case; brother, The material is copper and / or a material that can be used as an interconnect layer and copper, aluminum, or tungsten that can be used as a material for the connection area. Regarding the detection of the stress transfer properties of the semiconductor module finally installed on the relevant frame of the product Method, it is assumed that the above-mentioned Wei has the internal heating device directly formed nearby or integrated stress transfer structure formed by a wire-forming semiconductor group. The semiconductor module is subsequently installed on the module carrier τ, which is preferred. In order to form the lead frame of the flip-chip outer frame, afterwards, 'the product phase and frame are preferably formed by a plastic injection molding method' and then the plastic is cooled and hardened, and the actual reliability check is performed in the final installation state. In this case, the heating current is first produced in a hybrid heating device and the step-by-step is the stress transferability of the semiconductor module. The stress transfer test structure and the stress transfer test junction flow in this way. The application of heating current and the application of measuring voltage can be performed by ^ or temporary mixed age test, New Zealand test method and accelerated I Ci. The frame ^ indicates that the semiconductor module packaged on the flip-chip outer frame has been converged. As mentioned in the above, Qiu, Ben She's secret here and the same way include all the yang, yang. In the same way, the stress transfer test structure is not limited to: = All alternative types and structures are included in the same way, and integrated heating devices within or directly adjacent to it are generated ^. Transfer as structure [Simplified illustration of the figure] Figures 1A to 1C of the transfer property show simplified section views to illustrate the detection device and method. Force 13 1234220 Figure 2 shows a simplified section view to illustrate the device and method for detecting the stress transfer properties of the semiconductor module finally installed in the relevant frame of the product. Figure 3A shows a simplified plan view of the device according to the first embodiment in terms of debt stress transfer properties. Figure 3B shows a simplified perspective view of the device along section I -1 according to Figure 3A. Fig. 4A shows a simplified plane apparent stress transfer property of the device according to the second embodiment.
第4β圖顯示根據第4A圖沿區段II-II裝置的簡化透視圖。 應力根據第三具體實施例裝置的㈣^ 【主要元件符號說明】 1第一互連區域 3連接區域 IC半導體模組 T模組载體 G產品相關外框 IH、IH卜IH2整合加熱 V空隙 L1 ' L2 ' L3互連層 2弟·一互連區域 SMT應力轉移測試結構 B焊接連接 TG測試外框 EH外部加熱 AC/DC加熱電流 A連接區域 II、12絕緣層Figure 4β shows a simplified perspective view of the device along section II-II according to Figure 4A. Stress according to the third embodiment of the device [Description of the main component symbols] 1 The first interconnection area 3 The connection area IC semiconductor module T module carrier G Product related frame IH, IH BU IH2 Integrated heating V gap L1 'L2' L3 interconnect layer 2 Brother · One interconnect area SMT stress transfer test structure B solder connection TG test outer frame EH external heating AC / DC heating current A connection area II, 12 insulation layer
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