TW565901B - Interconnect layer structure for stress migration test and stress migration test method of interconnect layer - Google Patents

Abstract

A kind of interconnect layer structure for stress migration test is provided in the present invention, in which the amount of resistance variation generated due to the stress migration of conduction line and dielectric layer is measured. The interconnect layer structure includes the followings: the first and the second conduction lines located on the first metal layer; the third conduction line located on the second metal layer; the first and the second dielectric layers located between the first and the second metal layers, in which the first dielectric layer is connected between the first end of the first conduction line and the first end of the third conduction line, the second dielectric layer is connected between the first end of the second conduction line and the second end of the third conduction line, and the first and the second conduction lines, respectively, are electrically connected to the third conduction line; and the first, the second, the third and the fourth bonding pads, which are connected to the first and the second ends of the third conduction line, the second end of the first conduction line and the second end of the second conduction line, respectively.

Description

565901 V. Description of the invention (l) This month is about a test structure and method for stress migration of interc0nnect layer (S5 :: grati〇n), especially about-used for stress migration test The structure of the interconnect layer can simultaneously change the resistance (1 ine) and the via (via) under the stress migration phenomenon. Yu Yu

Integrated circuits usually have multiple interconnecting layers to provide electrical connections between components. These interconnecting layers are filled with insulating materials to insulate each other, and multiple dielectric layers are made in these insulating materials. Used to make the necessary electrical connection of the wires of each layer. As the density of components in integrated circuits continues to increase, the width and size of these wires and interlayers are also getting narrower and narrower, which makes them extremely vulnerable to some adverse effects and cannot provide the required electrical connectivity. 'Such as electromigration (e 1 e C tr omigrati 〇n) and stress migration and so on.

Stress migration refers to the phenomenon of metal atoms moving in an environment where there is no current but only thermal stress. When a thermal stress is applied to an integrated circuit device ', stress is generated between different material layers due to the difference in thermal expansion coefficients. Affected by this stress, metal atoms are pulled and migrated. For metal thin films, this stress is usually the tension concentrated at the grain boundary of the metal. Therefore, as metal atoms migrate by diffusion, voids (VO i d) will be generated along the grain boundaries until a break occurs in the metal layer. The insulation layer adjacent to the metal layer and having high shrinkage force increases the tension in the metal film and makes the phenomenon of stress migration more serious. There are two main factors affecting stress migration, one is temperature and the other is the structure of the metal layer. ^

565901 V. Description of the invention (2) Researchers have different views on the temperature factor. Some people think that a large stress migration phenomenon will occur at a certain temperature point, and some people think that the stress migration phenomenon will follow the temperature. Increase and strengthen, some people even think that temperature has little effect on the stress migration phenomenon. As for the factors of the metal layer structure, the following table summarizes the influence of some main metal layer structures on the stress migration phenomenon. Metal film thickness The thinner the thickness, the higher the relative defect density, which also means that the lifetime of the metal layer is shorter. The narrower the width of the metal layer, the greater the effect of the defect, which also means that the life of the metal layer is shorter. 0 The longer the length of the metal layer, the higher the probability of containing defects, and the shorter the life of the metal layer. The green layer with a high shrinkage force will increase the tension in the metal film, which also means that the life of the metal layer is shorter. Therefore, as described above, due to the increasing component density of integrated circuits, the width of the interconnect layer becomes narrower and narrower, which causes the adverse effects caused by the stress migration phenomenon to become larger and larger. For example, in a process of depositing an insulating layer on a wire made of aluminum, the insulating layer is usually deposited by a chemical vapor deposition (CVD) method at a temperature of at least 350 degrees Celsius. After the deposition step is completed, as the temperature of the entire structure is gradually reduced to room temperature, the wires with a higher expansion coefficient than the insulating layer will begin to shrink faster than the insulating layer. And stick tightly to the wire

0503-8454TWF; TSMC2002-0345; Vincent.ptd Page 5 565901

The insulation prevents the wire from shrinking and creates a force in the wire. This tension is stronger at the edges of the wire and gradually decreases in the center of the guide wire. Therefore, there is a stress gradient across the width of the wire. In order to reduce the energy generated by this stress imbalance, after a long time (months or years), the wire will migrate and migrate due to the diffusion of metal atoms. A void is generated, and finally the electrical connection is interrupted, and the integrated circuit cannot operate normally. In order to improve the adverse effects caused by stress migration, the stress migration phenomenon of the interconnect layer structure is measured and evaluated when manufacturing integrated circuits. In these measurement methods, the product-related interconnect layer test structure is used for measurement under certain temperature conditions. Figure 1 shows a Kelvin structure used for the change in resistance caused by the stress migration of the interlayer. A via 11 connects four wires 1 2 1 to 1 2 4 located in the two metal layers M1 and M2. By providing the currents through the wires 1 2 1 (located in the metal layer M 2), the interlayer 11 and the wires 12 2 (located in the metal layer M 1), the leads 123 (located in the metal layer M 1) and the leads 124 (located in the metal layer) A voltage difference is measured between layers M 2) to obtain the resistance change of the structure before and after a certain temperature.

Figures 2A, 2B, and 3 show another stress migration measurement structure provided in the EIAJ ED-4704-1 test standard B-102, which uses four bars located in Figures 2A and 2B. Conduction stress test of the conducting wire structure of the four metal layers M1 to M4 (the conducting wires 2 1 to 24), and the interlayer consisting of a plurality of interlayers 31 and 32 between the two metal layers M1 and M2 in FIG. 3 The chain (via chain) performs the stress migration test of the interlayer. In Figures 2A and 2B, the wires 21 and 23 of the odd layers are staggered by fingers, and the wires 22 and 24 of the even layers are also fingers.

0503-8454TWF; TSMC2002-0345: Vincent.ptd Page 6 565901 V. Description of the invention (4) '----', and the direction of the finger wires of the odd layer and the even layer is perpendicular. However, in the traditional stress migration measurement, it is necessary to use a separate inner wire layer structure to measure the resistance change of the wire and the dielectric layer due to stress migration. -Λ > g or 疋 Use the same interconnect layer. Structure to measure the resistance change caused by the wire and the dielectric layer due to force migration. It is not possible to use the same interconnect structure to simultaneously obtain the resistance change caused by the wire and the dielectric layer due to stress migration.

^ In order to solve the above problems, the present invention provides an interconnect layer structure for stress migration measurement #, which can simultaneously measure the resistance changes caused by the wires and the dielectric layer under the stress migration phenomenon.

It is an object of the present invention to provide an interconnect layer structure for stress migration testing, which measures the resistance change of a plurality of wires and interlayers due to stress migration. The interconnect layer structure includes: a first and A second wire is located at a metal layer; a third wire is located at a second metal layer; and a second interposer is located between the first and second metal layers, and the first layer is connected to the first metal layer. A first end of a wire and a first end of the third wire; a second interlayer is connected between a first end of the second wire and a second end of the third wire; The first and second wires are electrically connected to the third wire; and a first, second, third, and fourth pad are respectively connected to the first, second ends, and the first of the third wire. A second end of the wire is connected to a second end of the second wire. _ Another object of the invention is to provide a stress migration test method of the interconnecting layer. The method includes the following steps: providing an interconnecting layer structure; placing the interconnecting structure under an environmental condition and interconnecting the interconnected layer. A stress in the line structure

0503-8454TW; TSMC2002-0345; Vincent.ptd page 7 565901 V. Description of the invention (5) " ~~ migration phenomenon; and obtain the first and second pads, first and third pads and the first 2. The multiple resistance values between the fourth pad before and after the stress migration phenomenon occurs. The interconnect layer structure includes: a first and a second wire located on a first metal layer; a third wire on a second metal layer; a first and second interposer on the first And the second metal layer, the first interlayer is connected between a first end of the first wire and a first end of the third wire, and the second interlayer is connected to one of the second wires Between the first end and a second end of the second wire, and electrically connecting the first and second wires to the second wire respectively; and a first, second, third and fourth welding pad And are respectively connected to the first and second ends of the third wire, a first end of one of the first wires, and a second end of the second wire. Therefore, the present invention can measure the resistance value between different pad combinations by using the above-mentioned special interconnect structure, and can separately calculate the resistance change amount of the interlayer and the wire, which improves the traditional stress migration test. Disadvantages of the variation of resistance between the interlayer and the wire cannot be obtained for the interconnect layer. Example FIG. 4 shows the structure of the interconnect layer used for stress migration test according to an embodiment of the present invention. The resistance before and after stress migration of the interconnect structure test structure 4 using a prober (pr) 4 6 Change measurement.

The interconnect layer test structure 4 has the wires 42a and 42b located in a metal layer M1, the wires 41 located in a metal layer M2, a dielectric layer 43, four bright pads 45d and 45d, and a buffer pad 44. The interposer 43 is located between the metal layers M1 and M2. One interposer 43 is connected between a first end of the conductive line 42a and one of the first end of the conductive line 41, and the other interlayer 43 is connected to a first end of the conductive line 42b. And wire

0503-8454TW; TSMC2002-0345; Vincent.ptd Page 8 565901 V. Description of Invention (6) ----- 41 Between the second end, the wires 42a and 42b are electrically connected to the wires ... 45a to 45d are respectively connected to the first and second ends of the lead 41, the second end of the lead 42a, and the second end of the lead 4b. Two buffer pads 44 are respectively connected between the pad 45a and the first end of the lead 41 and between the pad 45d and the second end of the lead 41, and have a ladder-like line width, and are connected by the lead 4 ^ The direction of the bonding pads 45a or 45d is gradually increased as a buffer between the wire 41 having a smaller line width and the bonding pads 45a and 45d having a larger width to eliminate the factor of the two-dimensional effect. The pads 45a to 45d are respectively connected to the detector 46 to measure the resistance values of different combinations among the pads 45a to 45d. In the above-mentioned interconnect layer structure 4, the wires 42a and 42b have a line width w 3 that is much larger than the wire 41 to simplify the calculation of the resistance value of the interlayer 43. The wire length 13 of the wires 42a and 42b may be about 8 to 3.2. The line width wl of the wire 41 is determined according to design rules, and the wire length 11 may be 250 / zm, and the wire length 12 may be About 1 // m. The metal layers M1 and M2 are copper metal layers, and an insulating layer is filled therebetween for isolation. The metal layer M2 is located above the metal layer M1. This structure can also be used for exchanging the relative positions of the metal layers, so that the metal layer M1 is located above the metal layer M2. FIG. 5 shows a flowchart of a method for testing stress migration of an interconnect layer according to an embodiment of the present invention. First, in step 51, the above-mentioned interconnect layer structure is provided for testing. Then, in step 52, a voltage difference is provided between the pads 45a, 45d, between the pads 45a, 45b or 45d, 45c, and between the pads 45b, 45c, respectively. This voltage can be set between 〇 · 丨 ~ 〇 · 2 Volts, and its value is also

0503-8454TWF; TSMC2002-0345: Vincent.ptd Page 9 565901 V. Description of the invention (7) It can be determined according to the test requirements, but it should not directly cause damage to the interconnection layer structure. Furthermore, in step 53, the measurements are made between the fresh pads 45a, 45d, the pads 4 5a, 4 5b or 45d, 4 5c, and the pads 45b, 45c. The current generated by the voltage difference is provided to obtain the resistance value before the stress migration phenomenon occurs between the pads 45a, 45d, between the pads 45a, 45b or 45d, 45c, and between the fresh pads 45b, 45c. Next, in step 54, the interconnect layer structure is placed under an environmental condition for a period of time to generate a stress migration phenomenon in the interconnect layer structure. In this step, the tester can determine the environmental conditions according to his needs. For example, the above-mentioned interconnection structure can be stored in a chamber at 50 ° C, 200 ° C, or 250 ° C. The storage time can be set to 168, 504, Cool down to room temperature after 10 8 or 20 16 hours. In this way, the above-mentioned structure of the interconnect layer may begin to cause the phenomenon that the contraction speed of the wire and the insulation is different due to different expansion coefficients, and tension is generated in the conductor, so that stress migration occurs in the metal layer. . This kind of stress migration phenomenon will cause the resistance values of the wires and interlayers to change before and after high temperature storage. Then 'in step 55', when the interconnect layer structure is cooled to room temperature, it is between the pads 45a, 45d, the pads 45a, 451) or 45001, 45c, and the pads 45b, A voltage difference is provided between 45c. This voltage value can be set between 0 · 1 ~ 0 · 2 volts. Its value can also be determined according to test requirements, but it should not directly cause damage to the interconnect layer structure. Finally, in step 56, the measurements are made between the pads 45a, 45d,

0503-8454TWF; TSMC2002-0345: Vincent.ptd Page 10 565901 V. Description of the invention (8) Between pads 45a, 45b or 45d, 45c, and between pads 4 5b, 4 5c, as described in step 53 The current generated by the voltage difference provided to determine the stress migration phenomenon between pads 45a, 45d, between pads 45a, 45b or 45d, 45c, and between pads 4 5 b, 4 5 c. resistance. In the above-mentioned test method for stress migration of the interconnect layer, if rSad is used to represent the sheet resistance between the pads 42a and 42d obtained through measurement, and RAB and RCD are used to represent the pad 42a obtained through measurement. , 4 2 b, and pads 4 2 c and 4 2 d. RBC represents the resistance between pads 42b and 42c measured through measurement, and the line width w3 ^ of the wires and 42b is larger than the wire 41. In the case of the line width wi, the resistance value Rvia of the interlayer 43 can be obtained by the following formula: RVia = RAB-RsADx 12 or Rvia = RCD-rSadX 12; and the sheet resistance value of the lead 41 is equal to RSad. Therefore, by using the above-mentioned structure and test method of the interconnect layer, it is possible to obtain the resistance change amount of the conductor and the dielectric layer under the stress migration phenomenon, respectively. To sum up, the present invention can measure the resistance value between different pad combinations by using the above-mentioned special interconnect structure, and can separately calculate the resistance change amount of the interlayer and the wire, which improves the traditional stress migration test used. Disadvantages of the variation of resistance between the interlayer and the wire cannot be obtained for the interconnect layer. At the same time, the present invention can also cascade the above test structures into a chain, which can increase the sensitivity when measuring the resistance change of the interlayer, and can even be further applied to the study of the three-dimensional stress migration phenomenon. Although the present invention has been disclosed as above with a preferred embodiment, it also limits the present invention to anyone skilled in the art without departing from the spirit of the present invention.

565901

0503-8454TW; TSMC2002-0345; Vincent.ptd Page 12 565901 Brief description of the drawings In the following, an embodiment of the structure and method of the interconnect layer used in the stress migration test of the present invention is explained with drawings. Figure 1 shows a Kelvin structure for the change in resistance due to stress migration in the interlayer; Figures 2A, 2B, and 3 show the EI AJ ED-4704-1 test standard B-1 02 Stress migration measurement structure; FIG. 4 shows the structure of the interconnecting layer used for stress migration test in an embodiment of the present invention; FIG. 5 shows the method of stress migration testing of the interconnecting layer in an embodiment of the present invention flow chart. [Symbol Description] 11, 31, 43 ~ Interlayer; 12, 124, 2, 24, 32, 41, 42a, 42b ~ Wire; 4 ~ Interconnect layer structure; 4 4 ~ Buffer pad; 45a-45d ~ Fresh塾; 4 6 ~ detector; M1-M4 ~ metal layer. #

0503-8454TWF; TSMC2002-0345; Vincent.ptd page 13

Claims (1)

565901 VI. Scope of patent application 1. A layer structure for a plurality of conductors and interlayer lines includes: a first and first third conductors, a first and first interlayers connected to a first end, and The wire of the third wire is electrically connected to the first, the first, the second, and the second end of the second wire. 2. If applying for a dedicated interconnect layer structure, the first ends of the first and third wires In between, there is a second solder pad side 3. If the inner wiring layer is laminated with the second wire width 4. If you apply for a special inner wiring layer structure, please ask for the structure of each one, each of the first and second The wire has an interconnect layer structure that is much larger than the stress migration test to measure the change in resistance due to stress migration. The interconnect two wires are located in a first metal layer; and are located in a second metal layer; Two interposer layers are located between the first and second metal layers, and the second interposer layer at a first end of the first conductive line and the third conductive line is connected to a first end of a second conductive line. Between the two ends, and respectively leading the first and second leads to the third lead; and The third and fourth pads are respectively used for the stress migration test described in item 1 of the third lead end, a second end of the first lead, and the second lead, and further include: The buffer pads are respectively connected between the first pad and the second and the second end line width of the second pad and the third wire, and the line widths are gradually increased from the third wire to the first and gradually. . The first range and the second metal layer are copper metal layers. The first range and the second metal layer are copper metal layers. 0503-8454TWF; TSMC2002-0345: Vincent.ptd Page 14 565901 6. Scope of patent application 5. If applying for the structure of the interconnect layer. 6. If applying for the interconnection layer structure side. 7 · If you apply for an interconnect layer structure layer. 8. If applying for a range of patents for a plurality of resistors with an interconnect layer structure connected to a probe, wherein the scope of the patent, wherein the first metal layer for stress migration test described in the first item is located on the second metal layer The first metal layer for stress migration test described in item 1 is located under the second metal layer for stress migration test described in item 1 of the patent scope, wherein an insulation is filled between the first and second metal layers. The first, second, third, and fourth pads for stress migration test described in item 1 measure the patent scope of the first, second, third, and fourth pads, respectively. value. 9. A stress migration test method for an interconnect layer, comprising the steps of: providing an interconnect layer structure, the interconnect layer structure comprising: a second wire line, located at a second interlayer, the first interlayer being connected to Between the first first end, a second line of one of the second and the third conductive lines is electrically connected to the third conductive first and a first and the third conductive Pt7--, and is located in a first metal layer; A second metal layer; located between the first and second metal layers, a first end of a wire and a via of the third wire connected between a first end of the second wire, and The first and second wires, respectively; and the third and fourth pads, respectively, with the third wire 0503-8454TWF; TSMC2002-0345; Vincent.ptd Page 15 565901 Sixth, the first of the patent application scope will be found in the four test pads 10 test squares first, poor, and third. First, the second end, one end of the first wire is connected, and the interconnect structure is placed in a stress migration phenomenon; to obtain the stress migration phenomenon between the first and second pads. The ninth method, wherein the resistance values of the third pad, the third, the first end, and the second wire are in the interconnect structure and the first and third pads and the plural numbers before and after the generation resistance. The stress migration of the interconnect layer described in the above item is because the first, third, and fourth voltages are respectively measured on the first, fourth, and fourth pads by providing a plurality of voltages between the first, second, and four pads. The multiple currents generated between the pads due to the voltage differences are calculated as 11. The 9th test method of the scope of the patent application, wherein the interconnect layer includes a first and a second cushion pad, between the first ends of the three wires, and the The second ones have a plurality of line widths, and the directions of the second pads gradually increase. 1 2. According to the ninth test method of the scope of the patent application, wherein the interconnecting layer has a wire much larger than the third wire. 1 3. According to the ninth test method of the patent scope, the interconnecting layer is a copper metal layer. The stress transfer structure of the interconnect layer described in the item further includes: a second end line width connected to the first pad, the second pad, and the third wire from the third wire to the first and Each of the first and second wires of the stress transfer structure of the interconnect layer described in the item has a width. The first and second metal layers of the stress transfer structure of the interconnect layer described in the item 0503-8454TWF; TSMC2002-0345; Vincent.ptd Page 16 565901 6. Application for patent scope 1 4. Stress migration test method for interconnecting layer as described in item 9 of the scope of applying for patent, wherein the interconnecting layer structure The first metal layer is located above the second metal layer. 15. The stress migration test method for an interconnecting layer as described in item 9 of the scope of the patent application, wherein the first metal layer of the interconnecting layer structure is located below the second metal layer. 16. The stress migration test method for an interconnecting layer as described in item 9 of the scope of the patent application, wherein an insulating layer is filled between the first and second metal layers of the interconnecting layer structure. 0503-8454TWF; TSMC2002-0345; Vincent.ptd page 17