TWI232633B - Temperature and voltage compensated Hall sensor circuit - Google Patents

Abstract

A temperature-compensated and supply-voltage independent Hall sensor circuit is disclosed. The magnetic detection characteristics of the sensor can be made less dependent on temperature as well as supply voltage by the use of epitaxial resistors.

Description

1232633 Case No. 92124405 V. Description of the Invention (1) Technical Field The present invention relates to a Hall magnetic field sensor circuit, and particularly to the application of temperature and voltage characteristics of epitaxial (epita X ia 1) resistors in integrated circuits. The magnetic field sensitivity of the sensor is affected by temperature and power supply voltage. Prior Art Republic of China July 21, 1990 Republic of China Patent Bulletin 28 Volume 21 No. 4477 1 5 discloses a temperature compensation circuit for a hysteresis circuit. Although this patent can achieve the purpose of temperature compensation, it cannot solve the problem of hysteresis characteristics. Problems affected by power supply voltage. U.S. Patent Publication No. uS4, 521, 72, June 4, 985, discloses a type of magnetic field sensing circuit with temperature compensation. Although the hysteresis characteristic is temperature compensation, it cannot be protected from the power supply voltage. 8. Creative background Generally, if analog products have a wide operating temperature range, they must include temperature.

Based on the silicon magnetic induction integrated circuit. The number is very small, regardless of whether it is sensitive or not, it has its characteristics, so if it is not restricted. Based on the principle of Hall sensing, ^ has been gradually replaced by compound magnetic induction II 1232633 «J2124405. V. Description of the invention (2) Yueyi said the correction trend, whether it is a compound or how to reduce the Hall element changes with temperature. Hundreds of Schmitt devices have long faced the characteristic drift produced by Ruhua. The degree of magnetic induction is short and small, and the induction device is operated badly, and its induction becomes worse, which causes the wind to reach the magnetic field. Figure 1 shows a hall feeling crying ^ diagram), Hall element; = function block Figure (funCtion poles are biased with a fixed voltage source in the external magnetic field, in microvolts). After this voltage is generated by a # degree / minimum Hall voltage (approximate trigger (Schmitt Trf amplifier, large line amplification, and then Hall Hall induction principle shown in Figure 2), the voltage is combined to the characteristics of an output sensor. The most important is the sensitivity of the second-best-width device. In recent years, two mm directly reflects the development trend of the product being light, thin, and 'the use of Hall sensor DC brushless fans also has strict volume restrictions'. The coil of the magnetic field is reduced, and its field strength is also weakened. In order to make the DC brushless fan smooth, the requirements for the sensitivity of the magnetic field sensor are relatively increased. The 3A and 3B diagrams show a Huo without temperature compensation. The qualitative graph of the hysteresis width of the induction sensor as a function of temperature. Figure 3A shows that the hysteresis width of the device becomes wider with increasing temperature, that is, its sensitivity is such that the Hall sensor cannot detect the change in magnetic field polarity, and the fan No. Figure 3B shows that the hysteresis width of the sensor is increased and narrowed, that is, the sensitivity is so high that it is very susceptible to interference from field changes, which causes the fan to run abnormally. 4 A qualitative graph showing the hysteresis width versus terminal voltage change of a Hall sensor without voltage compensation. The hysteresis width of its sensor becomes wider as the voltage increases. Also 1232633 —- ^-^ 124405 βyear—September Amendment 2 on the 5th, the description of the invention (3) '~~ That is, the sensitivity has deteriorated. In view of the above-mentioned shortcomings, the inventor has proposed a solution after research and improvement, which is based on the application of silicon epitaxial resistors in semiconductor processes. Temperature and voltage characteristics (please refer to Figures 5A and 5B), for example, the / m degree coefficient of P-type ion implantation resistance is about 0.2% / ° c, and the temperature coefficient of N-type silicon epitaxial resistance is about 0 · 72% / ° C, and the temperature coefficient of the transistor base-to-emitter voltage (Vbe) is -1 · 8 mV / C. The voltage coefficient of the P-type ion implantation resistor is about 0 · 15% / V 'N type The voltage coefficient of a silicon epitaxial resistor is about .38%, c. Through the design of the circuit, the combination of components with different combinations of temperature coefficient and the opposite sign is integrated, so that the temperature coefficient and the offsetting Effect, can achieve its magnetic induction characteristics in a certain temperature application range It is not affected by temperature changes. Figure 5b shows that the silicon epitaxial resistance is different from the ordinary resistance only by the terminal voltage difference. Its resistance value is affected by the voltage values V (A) and V (B) at the ends of the resistor. Due to the influence of the width of the layer 32 (depletion layer), the resistance of the resistance conduction region 3 is not good, and V (A) is also affected by V (B). Therefore, the circuit design can be achieved by the combination of different resistors. The embodiment is shown in FIG. 1 'A Hall induction circuit includes an operating voltage source 18, and a fixed voltage source 24 to a Hall element 12 is provided through a power stabilizer 10. The Hall voltage induced by the external magnetic field is coupled to a differential amplifier 1232633. Amendment_Case No. 92124405 V. Description of the invention (4) 1 4 After that, a Schmitt trigger 16 with temperature and voltage compensation will be used. After the signal is processed and a hysteresis is generated, it is transmitted to an output device 17. FIG. 6 shows a preferred embodiment of the differential amplifier 14 according to the present invention. The fixed voltage source 24 is coupled to ground through a resistor 120 and an NPN transistor 108 connected to a collector and a base. A current source is formed and a current mirror is formed with the transistors 103, 104, and 105. The Hall voltages induced by the Hall element 12 are input by the bases of the front-end NPN transistors 1 06 and 107 of the differential amplifier 14 respectively, and the tiny differential signals are respectively provided by the resistors 1 4 0 and 16 0 and transistor 1 0 6 and resistor 1 3 0,

1 50 and the transistor 10 7 jointly achieve the effect of differential amplification through a current source 105. The amplified differential signals are respectively connected to the common contact point B (1 1 1) and the common contact point A (1 1 2) of 10, 10 and 4 through the NPN transistor 1 0, 1 0 3, respectively. The input terminal of the Schmitt actuator 16 of the next stage. FIG. 7 shows a preferred embodiment of the Schmitt contactor 16 with temperature and voltage compensation according to the present invention. The fixed voltage source 24 is connected to a collector and a base n through a resistor 2 2 0. The emitter of the PN transistor 2 07 is coupled to the ground to form a current source, and a current mirror is formed with the transistors 2 0 3 and 2 06. The two output terminals of the differential amplifier 14 are respectively input by the collectors of the NPN transistors 209 and 210, and the collector of the transistor 209 is connected to the NPN transistor connected to the base at the same time.

2 1 0 and 2 1 1 are connected, and the collector of the transistor 2 1 0 is also connected to the npn transistor 2 08 and 2 9 which are commonly connected to the base. The emitter of transistor 2 0 8 passes resistor 2 3 0, the emitter of transistor 2 0 9 passes resistor 2 4 0, the emitter of transistor 2 1 0 passes resistor 2 5 0, transistor 2 11 The emitter is coupled to one end of the alternative resistor 310 through the resistor 260, and the other end of the resistor 310 is coupled to one end of the resistor 270, and the other end of the resistor 270 is coupled to the ground. Base

Page 9 1232633 _ Case No. 92124405 Amended on January 2, 2015 V. Description of the invention (5) The common emitter of the PNP transistor 2 0 4 and 2 0 5 is connected to the fixed voltage source 2 4 and the transistor 2 0 5 The base is connected to its collector and then to the collector of NPN transistor 206. The base of transistor 2 0 6 is connected to the base of transistor 2 0 7 current mirror to form a current source. The emitter of transistor 2 6 is lightly connected to the ground, and the transistor 2 0 8

The collector is coupled to the collector of the transistor 204. The common emitter of the base PNP transistor 20 and 20 2 is connected to a fixed voltage source 24. The base of the transistor 201 is connected to its collector and then coupled to the collector of the NPN transistor 2 0. The base of crystal 203 is connected to the base of transistor 207 current mirror and forms a current source. The emitter of transistor 203 is coupled to ground. The collector of the transistor 2 1 1 is coupled to the collector of the transistor 2 0 2 and is connected to the output terminal 2 1 2. Transistors 2 0 8, ^ 09, 210, 211 and resistors 2 3 0, 240, 25 0, 2 6 0 together form a post trigger special trigger, and its hysteresis width is determined by resistors 3 1 0, 2 7 〇 Joint decision. Resistor 3 1 0 is Shi Xijing crystal resistance, the rest are ion implanted resistors. The resistance temperature coefficient of Shi Xi stupid crystal resistor 3 1 〇 is different from the temperature coefficient of Shi Peng ion implanted resistors, so it is appropriate. The resistors 31 and 27 are selected, and the resistance value can be offset with the effect of temperature Vbe of the transistor to achieve the goal that the magnetic induction parameter is not affected by temperature.

—In addition, the resistance value of the two ends of the Shi Xi stupid crystal resistor 310 can be adjusted to generate a resistance value, and this resistance value is different from the characteristic that the ordinary resistor is only affected by the voltage difference between the two ends. Influence of terminal voltage. Adjusting the characteristics of the end-of-line voltage effect ’The fixed voltage source 24 can be subjected to a fall response = response cancellation’ to achieve a magnetic induction with a hysteresis width that is not affected by the operating voltage

Page 10 1232633 Case No. 92124405% Year "Month and month correction diagram Simple description Element symbol description Operating voltage source 18 Power stabilizer 10 Fixed voltage source Hall element 12 Differential amplifier 14 Schmitt trigger with temperature and voltage compensation Device 16 output device 17 depletion layer 32 conduction region 34 hysteresis width 11 PNP transistor 201 > 2 0 2 > 2 0 4, 205 NPN transistor 101 ^ 102 ~ 103 ~ 104, 105, 106 ~ 108 > 2 0 3 to 2 0 6, 207, 2 0 8, 2 0 9 ^ 211 resistors 120, 130, 140, 150, 160, 2 2 0 > 230, 24 0, 2 5 0, 260 > 270 alternative resistance Figure 310 shows the Hall sensor function: block diagram < 0 Figure 2 shows the hysteresis characteristic of the Hall sensor. Figure 3A is the hysteresis width affected by temperature. Figure 1 Figure 3B is hysteresis] 1: Degree of temperature affected by degree. Figure 2 is a characteristic diagram of hysteresis width affected by operating voltage. Figure 5A is a graph showing the effect of temperature on the silicon epitaxial resistance. Figure 5B is a graph showing the effect of the terminal voltage on the resistance of a chip. Fig. 6 is a preferred embodiment of the differential amplifier. 24 107 210 The figure shows one of the Schmitt triggers with temperature and voltage compensation.

Page 11 1232633 _ Case No. 92124405_ Foreign years? Month < Z-day_correction The diagram briefly explains the embodiment.

IIHII Page 12

Claims (1)

1232633 Case No. 92124405 Amendment 6. Scope of patent application 1. A Hall sensor circuit with temperature and voltage compensation, the circuit includes: an operating voltage source, and the inductor circuit operation station is provided through two input terminals of the voltage source. The required power supply is used to sense the change of the external magnetic field and convert it into a small voltage differential signal that is proportional to the output signal. The device receives the above differential voltage signal and puts a Hall element magnetic field intensity to generate dynamic amplification. There is a big difference; a component management, which is delayed by the power that is transmitted one by one. 2. Such as the application of the secret. 3. As stated, the first temperature and resistance pairs will be adjusted by the hysteresis effect to the device pressure level. Into less good. The patented special trigger is patented. The Schmitt actuator with temperature-input voltage compensation uses the different temperature and voltage characteristics of each semiconductor to compensate each other. The original differential signal amplified by the differential amplifier is added to the output after processing. A digital signal; After adjusting the above digital signals to the application requirements, output to the load end; The resistance value of the alternative resistor in the Schmitt actuator can be affected by the hysteresis characteristic of the Hall sensor with temperature and voltage. The Hall sensor circuit according to item 1, wherein the alternative resistor in the device is a silicon epitaxial resistor. The Hall sensor circuit described in the first item of the range, wherein the Schmitt contactor of the voltage compensation and the voltage compensation includes the following elements: two inputs Page 13 I Case No. 92124405 Amendment VI. Patent application scope-an output terminal; a first NPN transistor, wherein the first base is coupled to the first input terminal, and the first emitter is connected to a first resistor One terminal; a second NPN transistor, wherein the second base is coupled to the first base of the first transistor and is commonly connected to the first input terminal, and the second collector of the second transistor Coupled to the second input terminal, the second emitter of the second transistor is connected to one terminal of a second resistor; a third NPN transistor, wherein the third base is coupled to the second transistor The second collector, the third collector of the third transistor is coupled to the first input terminal, and the third emitter of the third transistor is connected to one terminal of a third resistor; a fourth NPN A transistor, wherein the fourth base is coupled to the third base of the third transistor and is commonly connected to the second collector of the second transistor; the fourth emitter of the fourth transistor is connected To one end of a fourth resistor; an alternative resistor, one end of which is connected in common to the first resistor The other end of the second, the third, the fourth resistor; a fifth resistor, one of the resistors is connected to the other end of the silicon epitaxial resistor, and the other end of the fifth resistor is coupled To ground; a first current mirror, in which a fifth PNP transistor and a sixth PNP transistor have a common emitter coupled to a fixed voltage source, the fifth base and the sixth base in common and The sixth emitter is coupled to the seventh collector of a seventh NPN transistor, the seventh emitter is coupled to ground, the fifth collector is connected in common with the first collector and coupled to an output terminal; Page 14 2005. 03. 07.014 1232633 \ X r -i Heart., Guang, i No. 92124405 Revised March 7th of the year _ '1--I Ύ I · I --------- Sixteenth, the scope of patent application is a second current mirror, in which a common emitter of an eighth PNP transistor and a ninth PNP transistor is coupled to the fixed A voltage source, the eighth base and the ninth base in common and coupled with the ninth emitter to the tenth collector of a tenth NPN transistor, the tenth emitter is coupled to ground; a current source , Wherein the fixed voltage source passes through a sixth resistor, the other end of the resistor is connected to an eleventh NPN transistor, the eleventh collector and the eleventh base are connected in common and coupled to the seventh The base and the tenth base form a first and a second current mirror. Page 15 2005. 03. 07.015