TWI231509B - Solid-state inductor and method for producing the same - Google Patents

Solid-state inductor and method for producing the same Download PDF

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TWI231509B
TWI231509B TW092103011A TW92103011A TWI231509B TW I231509 B TWI231509 B TW I231509B TW 092103011 A TW092103011 A TW 092103011A TW 92103011 A TW92103011 A TW 92103011A TW I231509 B TWI231509 B TW I231509B
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cmr
solid
film
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TW200305895A (en
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Wei Pan
Sheng Teng Hsu
Wei Wei Zhuang
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Sharp Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/24—Magnetic cores
    • H01F27/245—Magnetic cores made from sheets, e.g. grain-oriented
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F10/00—Thin magnetic films, e.g. of one-domain structure
    • H01F10/08—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers
    • H01F10/10—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition
    • H01F10/18—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition being compounds
    • H01F10/193—Magnetic semiconductor compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F21/00—Variable inductances or transformers of the signal type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/14—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates
    • H01F41/24—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates from liquids
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/4902—Electromagnet, transformer or inductor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Hall/Mr Elements (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method for producing a solid-state inductor according to the present invention is a method for producing a solid-state inductor, comprising: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin film; and applying an electrical field treatment to the CMR thin film and, in response to the electrical field treatment, converting the CMR thin film into a CMR thin film inductor.

Description

1231509 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於一種固態電感器及其製造方法，尤指一 種電感器，諸如一種供類比積體電路（integrated circuit ，簡稱1C)之固態電感器及其製造方法。 【先前技術】 一種習知之固態電感器（一種1C整合之固態電感器 稱爲1C整合之電感）係自一金屬線形成，設計成螺旋形 式，覆蓋一在矽基板上之厚層之絕緣體。如此所形成之電 感器之電感値很低，因而形成一切合實際之電感器需要大 矽面積。除了使用大量有價値之1C面積外，大型電感器 與靠近，覆蓋該電感器或在其下面之諸組件產生寄生電抗 及非預計之相互電感。 而且，1C整合電感器爲一種被動組件，意爲其一旦 形成在1C，便無法改變電感値。因此，無法使用電感器 供頻率調諧。在電路諸如濾波器，天線，及振盪器少數幾 種實例之製造，將宜有一種電感器供頻率調諧。 在如以上所說明之先前技藝，難以完成一種具有大電 感値以減低其大小之電感器。而且，無法改變IC整合電 感器之電感値，而藉以使用一電感器供頻率調諧。 【發明內容】 根據本發明之一方面提供一種製造固態電感器之方法 -6 - (2) 1231509 ，該方法包含：形成一底電極；形成一巨大磁阻（ colossal magnetoresistance，簡稱 CMR)薄膜覆蓋底電極 ;形成一頂電極覆蓋CMR薄膜；以及施加一種電場處理 至CMR薄膜，並且響應該電場處理，將CMR薄膜轉變爲 一 CMR薄膜電感器。 在本發明之一種實施例，一種製造固態電感器之方法 另包含在頂與底電極之間施加一偏壓，以及，響應所施加 之偏壓，在頂與底電極之間造成電感。 在本發明之一種實施例，一種製造固態電感器之方法 另包含改變所施加之偏壓；以及響應在所施加之偏壓之變 化而改變電感。 在本發明之一種實施例，形成一巨大磁阻（CMR)薄 膜覆蓋底電極包括使用一種選自包括PrQ.3Cac).7Mn03 ( PCM0 ) ，La〇.7Ca〇.3Mn〇3 ( LCMO ) ，Yi.xCaxMn03 ( YCMO )，及高溫超導體（high-temperature super conductor簡稱（HTSC)材料之類組之材料，作爲巨大磁 阻（CMR)薄膜材料。 在本發明之一種實施例，形成一巨大磁阻（CMR)薄 膜覆底電極包括形成一巨大磁阻（CMR )薄膜具厚度約 2000 埃。 在本發明之一種實施例，形成一巨大磁阻（CMR)薄 膜覆蓋底電極包括：旋塗一有厚度約670埃之第一層；使 第一層在溫度約65〇度攝氏退火約30分鐘之期間；旋塗 一有厚度約6 70埃之第二層，覆蓋第一層；使第二層在溫 (3) (3)1231509 度約550度攝氏退火約30分鐘之期間；旋塗一有厚度約 67 0埃之第三層，覆蓋第二層；以及使第三層在溫度約 5 5 0度攝氏退火約3 0分鐘之期間。 在本發明之一種實施例，其中形成一底電極包括自一 種選自包括 Al，Au，Ti，Ta，Pt，Cu，W，Ir，AlSi 及其 他貴金屬之類組之材料形成一底電極。 在本發明之一種實施例，形成一頂電極包括自一種選 自包括 Al，Au，Ti，Ta，Pt，Cu，W，Ir，AlSi 及其他貴 金屬之類組之材料形成一頂電極。 在本發明之一種實施例，施加一種電場處理至CMR 薄膜包括在〇·4至1百萬伏/公分（MV/cm )之範圍，而脈 衝寬度在100毫微秒（ns)至1毫秒（ms)之範圍施加電 在本發明之一種實施例，在頂與底電極之間施加偏壓 包括施加一選自包括：一 dc (直流）電壓在〇. 5至5伏之 範圍以內；及一 dc (直流）電壓在-0.5至-5伏之範圍以 內之類組之偏壓。 在本發明之一種實施例，在頂與底電極之間造成一電 感’包括造成一在大於0.01微亨利（//H)至少於1//H 之範圍之電感。 在本發明之一種實施例，饗應在所施加之偏壓之變化 而在頂與底電極之間改變電感，包括在選自包括+1 dc伏 及伏之類組之偏壓造成最大電感。1231509 (1) Description of the invention [Technical field to which the invention belongs] The present invention relates to a solid-state inductor and a method for manufacturing the same, particularly an inductor, such as a solid-state for an integrated circuit (referred to as 1C) Inductor and manufacturing method thereof. [Prior technology] A conventional solid-state inductor (a 1C-integrated solid-state inductor is called 1C-integrated inductor) is formed from a metal wire and designed in a spiral shape to cover a thick layer of insulator on a silicon substrate. The inductance 値 of the inductor thus formed is very low, so a large silicon area is required to form all practical inductors. In addition to using a large amount of valuable 1C area, large inductors close to, cover the inductor or the components below it produce parasitic reactance and unintended mutual inductance. Moreover, 1C integrated inductor is a passive component, which means that once it is formed in 1C, the inductance 値 cannot be changed. Therefore, inductors cannot be used for frequency tuning. In the manufacture of a few examples of circuits such as filters, antennas, and oscillators, it would be desirable to have an inductor for frequency tuning. In the prior art as described above, it is difficult to complete an inductor having a large inductance to reduce its size. Moreover, the inductance of the IC integrated inductor cannot be changed, and an inductor is used for frequency tuning. [Summary of the Invention] According to an aspect of the present invention, a method for manufacturing a solid-state inductor is provided. The method includes: forming a bottom electrode; forming a colossal magnetoresistance (CMR) film covering the bottom Forming a top electrode to cover the CMR film; and applying an electric field treatment to the CMR film, and in response to the electric field treatment, transforming the CMR film into a CMR film inductor. In one embodiment of the present invention, a method of manufacturing a solid-state inductor further includes applying a bias voltage between the top and bottom electrodes, and inducing an inductance between the top and bottom electrodes in response to the applied bias voltage. In one embodiment of the present invention, a method of manufacturing a solid-state inductor further includes changing the applied bias voltage; and changing the inductance in response to a change in the applied bias voltage. In one embodiment of the present invention, forming a giant magnetoresistive (CMR) film to cover the bottom electrode includes using a material selected from the group consisting of PrQ.3Cac) .7Mn03 (PCM0), La0.77Ca0.3MMn3 (LCMO), Yi .xCaxMn03 (YCMO), and materials such as high-temperature super conductor (HTSC) materials, as a giant magnetoresistive (CMR) thin film material. In one embodiment of the present invention, a giant magnetoresistive ( CMR) thin-film bottom electrode includes forming a giant magnetoresistive (CMR) film with a thickness of about 2000 Angstroms. In one embodiment of the present invention, forming a giant magnetoresistive (CMR) film covering the bottom electrode includes: The first layer of 670 angstroms; the first layer was annealed at a temperature of about 65 ° Celsius for about 30 minutes; a second layer with a thickness of about 6 70 angstroms was spin-coated to cover the first layer; (3) (3) a period of about 30 minutes at 1231509 degrees and about 550 degrees Celsius annealing; spin-coated a third layer with a thickness of about 670 angstroms to cover the second layer; and the third layer at a temperature of about 550 degrees Annealing for about 30 minutes. In one embodiment of the invention, Forming a bottom electrode includes forming a bottom electrode from a material selected from the group consisting of Al, Au, Ti, Ta, Pt, Cu, W, Ir, AlSi, and other precious metals. In one embodiment of the present invention, forming a bottom electrode The top electrode includes a top electrode formed from a material selected from the group consisting of Al, Au, Ti, Ta, Pt, Cu, W, Ir, AlSi, and other precious metals. In one embodiment of the present invention, an electric field treatment is applied. The CMR film includes a range of 0.4 to 1 million volts per centimeter (MV / cm), and a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms). For example, applying a bias voltage between the top and bottom electrodes includes applying a component selected from the group consisting of: a dc (direct current) voltage in the range of 0.5 to 5 volts; and a dc (direct current) voltage in the range of -0.5 to -5 volts Within a range of such a bias voltage. In one embodiment of the present invention, causing an inductance between the top and bottom electrodes' includes causing a range greater than 0.01 microhenry (// H) to be less than 1 // H In one embodiment of the present invention, the Changing the inductance between the top and bottom electrode, comprising +1 dc bias from the group comprising V and V group or the like caused by the maximum inductance.

在本發明之一種實施例，施加一種電場處理至CMR (4) (4)1231509 薄膜包括施加電場，而同時使CMR薄膜退火。 根據本發明之另一方面，提供一種製造固態電感器之 方法，包含：形成一底電極；形成一巨大磁阻（CMR)薄 膜覆蓋底電極；形成一頂電極覆蓋CMR薄膜；以及在0.4 至1百萬伏/公分（MV/cm)之範圍，而脈衝寬度在100 毫微秒（ns)至1毫秒（ms)之範圍，施加一種電場處理 至CMR薄膜，並且響應該電場處理，將CMR薄膜轉變爲 一 CMR薄膜電感器；在頂與底電極之間施加一偏壓；響 應所施加之偏壓，在頂與底電極之間造成電感；以及改變 所施加之偏壓及響應改變偏壓而改變電感。 根據本發明之又一方面，提供一種固態電感器，該電 感器包含：一底電極；一巨大磁阻（CMR)薄膜覆蓋底電 極；以及一頂電極覆蓋CMR薄膜。 在本發明之一種實施例，一種固態電感器另包含一裝 置’用於在頂與底電極之間施加一偏壓，並且響應所施加 之偏壓，在頂與底電極之間造成電感。 在本發明之一種實施例，電壓施加裝置改變所施加之 偏壓；以及在頂與底電壓間之電感響應在所施加之偏壓之 變化而改變。 在本發明之一種實施例，巨大磁阻（CMR)薄膜包括 Pr〇.3Ca〇.7Mn03PCMO ) ，La0 7Ca0 3MnO3 ( LCMO )，In one embodiment of the invention, applying an electric field treatment to the CMR (4) (4) 1231509 film includes applying an electric field while annealing the CMR film. According to another aspect of the present invention, a method for manufacturing a solid-state inductor is provided, including: forming a bottom electrode; forming a giant magnetoresistive (CMR) film covering the bottom electrode; forming a top electrode covering the CMR film; and between 0.4 and 1 In the range of millions of volts / cm (MV / cm) and the pulse width is in the range of 100 nanoseconds (ns) to 1 millisecond (ms), an electric field process is applied to the CMR film, and the CMR film is responded to the electric field process Into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; causing inductance between the top and bottom electrodes in response to the applied bias voltage; and changing the applied bias voltage and responding to the change in bias voltage Change the inductance. According to another aspect of the present invention, a solid-state inductor is provided. The inductor includes: a bottom electrode; a giant magnetoresistive (CMR) film covering the bottom electrode; and a top electrode covering the CMR film. In one embodiment of the present invention, a solid-state inductor further comprises a device 'for applying a bias voltage between the top and bottom electrodes, and inducing an inductance between the top and bottom electrodes in response to the applied bias voltage. In one embodiment of the invention, the voltage applying means changes the applied bias voltage; and the inductance between the top and bottom voltages changes in response to a change in the applied bias voltage. In one embodiment of the present invention, the giant magnetoresistive (CMR) film includes Pr 0.3 Ca 0.0 7 Mn 03 PCMO), La 0 7 Ca 0 3 MnO 3 (LCMO),

Yi-xCaxMn03 ( YCMO )，及高溫超導體（HT S C )材料。 在本發明之一種實施例，巨大磁阻（CMR)薄膜具厚 度約2 0 〇 〇埃。 (5) (5)1231509 在本發明之一種實施例，其中形成一底電極包括一種 選自包括 Al，Au，Ti，Ta，Pt，Cu，W，Ir，AlSi 及其他 貴金屬之類組之材料。 在本發明之一種實施例，頂電極係以一種選自包括 Al，Au，Ti，Ta，Pt，Cu，W，lr，AlSi 及其他貴金屬之 類組之材料所形成。 在本發明之一種實施例，電場處理之CMR薄膜已曝 露至一電場在0.4至1百萬伏/公分（MV/cm)之範圍，而 脈衝寬度在1〇〇毫微秒（ns)至1毫秒（ms)之範圍。 在本發明之一種實施例，偏壓施加裝置在頂與底電極 之間施加一選自包括：一 dc (直流）電壓在〇.5至5伏之 範圍以內；及一 dc (直流）電壓在- 0.5至-5伏之範圍以 內之類組之偏壓。 在本發明之一種實施例，在頂與底電極間之電感，有 一値在大於0.01微亨利（//H)至少於1//H之範圍。 在本發明之一種實施例，響應選自包括+ ldc伏及- ldc 之類組之所施加之偏壓，在頂與底電極間之電感爲一最大 値。 利用上述結構，可提供一種固態電感器，其具有相對 高電感値，需要很小晶片面積，並適於整合至習知積體電 路（其可爲一種互補金屬氧化物半導體或一種在矽上，或 在化合物半導體基板上所製成之雙極電路，及其一種製造 方法。再者，由於在1C電路可改變電感値，故可較容易 進行調諧。 -10- (6) 1231509 医!此’在本文所述之發明，使可能具有下列優點：( 1 )提供一種固態電感器，具有大電感値，以減低其大小 及其一種製造方法，以及（2)提供一種固態電感器，其 可容易改變在1C電路之電感値而藉以供調諧使用，及其 一種製造方法。 精於該項技藝者參照附圖閱讀及瞭解下列詳細說明， 將會明白本發明之此等及其他諸多優點。 【實施方式】 現在，將參照圖式說明本發明之一種固態電感器（在 下文簡稱電感器）及其一種製造方法。 圖1爲示意圖，示一根據本發明之電感器之槪括結構 〇 在圖1中，電感器100包含一底電極i 02，一電場處 理之巨大磁阻（CMR)薄膜104覆蓋底電極102，及一頂 電極106覆蓋CMR薄膜104。 CMR薄膜1〇4係自一種材料諸如Pr() 3Ca〇.7Mn03( PCMO ) ，La〇.7Ca〇.3Mn〇3 ( LCMO ) ，Y^^axMnOa ( YCMO)，及高溫超導體（HTSC )材料作成。不過，依需 求而定，其他同等材料也可切合實際。CMR薄膜104有 一厚度約2000埃。 如現在更詳細解釋，將C MR薄膜1 〇 4曝露至一在0.4 至1百萬伏/公分（MV/cm )之範圍，而脈衝寬度在1 〇〇 毫微秒（n s )至1毫秒（m s )之範圍之電場。此僅只爲一 -11 - (7) (7)1231509 種例證性處理。依CMR材料，插入材料，及希望之電感 而定，其他處理手段爲切合實際。 電感器1〇〇之底電極102係自一種選自包括aj,Au ，Ti，Ta，Pt，Cu，W，Ir，AlSi或其他貴金屬之類組之 材料所形成。不過，也可使用在1C之製造上所熟知之其 他導體材料。同樣，頂電極106 —般係自一種選自包括 Al，Au，Ti，Ta，Pt，Cu，W，Ir，AlSi 或其他貴金屬之 類組之材料所形成。 提供一電壓施加裝置112，用以在電感器1〇〇之頂電 極106與底電極102之間施加一偏壓。一般爲，電感器 1〇〇包括一較大，較複雜電路之一部份，並且偏壓及相對 地零電位通過其他組件，諸如電晶體（未示）予以連接。 在CMR薄膜104在頂與底電極106/102之間，響應自電 壓施加裝置112所加之偏壓，而造成電感器之一電感或電 感値 L ( 1 1 4 )。 在有些方面，電壓施加裝置112可改變將行加至電感 器1〇〇之偏壓。頂與底電極106/1 02間之電感値L ( 1 14 )響應在所加之偏壓之變化而改變。吾人曾開發若干實用 偏壓範圍作爲實例。在有些方面，電壓施加裝置112在頂 與底電極106/102之間在0.5至5dc伏，或-0.5至- 5dc伏 之範圍以內施加一電壓。不過，供特定電路應用，也可使 用一 ac (交流）電壓。而且，可使用其他dc電壓範圍供 CMR材料，CMR容積，及電場處理之不同變化。 使用上述偏壓値，依CMR材料，及CMR薄膜104之 -12· (8) (8)1231509 幾何結構（容積，直徑108，及厚度）而定，在頂與底電 極106/102之間之電感114可爲在大於〇·〇1微亨利（//H )至少於1 A Η之範圍。一般爲，在頂與底電極1〇6/1〇2 間之電感値L ( 1 14 )，響應+ ldc伏或- ldc伏之外加電壓 而爲一最大値。不過，最大電感與偏壓間之關係，再次依 CMR材料及CMR幾何結構而定。 圖2爲一裝置結構之剖面圖，其中二根據本發明之電 感器施加至一實際1C積體電路。 如圖2中所示，根據本發明之電感器100爲一種二端 子柱狀結構。電感器可製成爲一單一通道孔，而有底 電極至一 pn接合處，或在一局部互相連接金屬線。在完 成處理之前端後，可將電感器1〇〇整合至1C 〇在裝置A 200，將電感器1〇〇整合至一汲極接合處2 02。在裝置B 204，將另一電感器1〇〇整合至一閘電極206。可使用習 知之敷著方法，諸如旋塗，噴濺及CVD (化學蒸敷）法 ，將（諸）電感器1〇〇敷著至半導體基板。而且，電感器 100具有很高電感，使用一種偏壓控制，其可改變二個量 級。電感器1〇〇爲其一部份之任何LC電路，其調諧可藉 調整越過電感器1〇〇之偏壓達成。 例如，根據本發明之電感器100可使用一種使用旋塗 法製成巨大磁阻（CMR)薄膜作成。CMR材料可爲PCMO (Pr〇.3Ca〇.7Mn〇3 ) 。CMR薄膜予以塗布三次，以供總厚 度約200亳微米（nm)至鉑基板。在首次塗布後使c MR 薄膜在650°C退火30分鐘，以及在第二及第三次塗布後 -13- (9) 1231509 在5 5 0 °C退火30分鐘。頂電極106也爲鉑，但也可使用 若干其他金屬諸如Al，Cu，W，Ir，A1SI，或其他貴金屬 。緊接在製造後或如所製成之CMR薄膜1 04據測量具有 由於電阻組件之電阻R及由於電容組件之電容C。 圖3例示在電場處理前，一例證性CMR薄膜之電抗 〇 圖3中所示之所有測量，均爲與電感値串聯之電阻。 測量頻率爲1 MHz。所示之實測電感爲負，並因此爲電容 性。 圖3也示此CMR薄膜之電容値及電阻値實際獨立於 在既定測量部位之偏壓値。 圖4例示在電場處理後，該例證性CMR薄膜之電抗 〇Yi-xCaxMn03 (YCMO), and high temperature superconductor (HT S C) materials. In one embodiment of the invention, the giant magnetoresistive (CMR) film has a thickness of about 2000 angstroms. (5) (5) 1231509 In one embodiment of the present invention, forming a bottom electrode includes a material selected from the group consisting of Al, Au, Ti, Ta, Pt, Cu, W, Ir, AlSi, and other precious metals. . In one embodiment of the present invention, the top electrode is formed of a material selected from the group consisting of Al, Au, Ti, Ta, Pt, Cu, W, lr, AlSi, and other precious metals. In one embodiment of the present invention, an electric field-treated CMR film has been exposed to an electric field in the range of 0.4 to 1 million volts / cm (MV / cm), and the pulse width is 100 nanoseconds (ns) to 1 The range of milliseconds (ms). In one embodiment of the present invention, the bias applying device applies a voltage between the top and bottom electrodes including: a dc (direct current) voltage within a range of 0.5 to 5 volts; and a dc (direct current) voltage between -Bias in the range of 0.5 to -5 volts. In one embodiment of the present invention, the inductance between the top and bottom electrodes has a range of greater than 0.01 microhenry (// H) and less than 1 // H. In one embodiment of the present invention, in response to an applied bias voltage selected from the group consisting of + ldc volts and-ldc, the inductance between the top and bottom electrodes is a maximum 値. With the above structure, a solid-state inductor can be provided, which has a relatively high inductance, requires a small chip area, and is suitable for integration into a conventional integrated circuit (which may be a complementary metal oxide semiconductor or a silicon-on-silicon, Or a bipolar circuit made on a compound semiconductor substrate, and a method for manufacturing the same. Furthermore, since the inductance 改变 can be changed in a 1C circuit, it can be easier to tune. -10- (6) 1231509 Doctor! This' The invention described herein makes it possible to (1) provide a solid-state inductor with a large inductance to reduce its size and a manufacturing method thereof, and (2) provide a solid-state inductor, which can be easily Change the inductance of the 1C circuit for tuning and a manufacturing method. Those skilled in the art who read and understand the following detailed description with reference to the drawings will understand these and many other advantages of the present invention. [Implementation Mode] Now, a solid-state inductor (hereinafter referred to as an inductor) and a manufacturing method thereof according to the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram showing Inclusive structure of the inductor according to the present invention. In FIG. 1, the inductor 100 includes a bottom electrode i 02, an electric field-treated giant magnetoresistive (CMR) film 104 covering the bottom electrode 102, and a top electrode 106 covering the CMR. Thin film 104. The CMR thin film 104 is made of a material such as Pr () 3Ca0.77Mn03 (PCMO), La0.77Ca0.3MMn3 (LCMO), Y ^ axMnOa (YCMO), and high temperature superconductor (HTSC) ) Made of materials. However, depending on the requirements, other equivalent materials may also be practical. The CMR film 104 has a thickness of about 2000 angstroms. As explained in more detail now, the C MR film 104 is exposed to 0.4 to 1 million Electric field in the range of volts / cm (MV / cm) and pulse width in the range of 1000 nanoseconds (ns) to 1 millisecond (ms). This is only one -11-(7) (7) 1231509 kinds Exemplary processing. Depending on the CMR material, the insertion material, and the desired inductance, other processing methods are realistic. The bottom electrode 102 of the inductor 100 is selected from the group consisting of aj, Au, Ti, Ta, Pt, Cu, W, Ir, AlSi or other precious metals. However, it can also be used in 1C Other conductive materials are well known. Similarly, the top electrode 106 is generally formed from a material selected from the group consisting of Al, Au, Ti, Ta, Pt, Cu, W, Ir, AlSi, or other precious metals. Provided A voltage applying device 112 is used to apply a bias voltage between the top electrode 106 and the bottom electrode 102 of the inductor 100. Generally, the inductor 100 includes a part of a larger and more complicated circuit. And the bias voltage and the relative zero potential are connected through other components, such as a transistor (not shown). Between the CMR film 104 between the top and bottom electrodes 106/102, in response to the bias voltage applied by the voltage application device 112, one of the inductors has an inductance or inductance 値 L (1 1 4). In some aspects, the voltage application device 112 may change the bias voltage to apply a row to the inductor 1000. The inductance 値 L (1 14) between the top and bottom electrodes 106/1 02 changes in response to a change in the applied bias voltage. I have developed several practical bias ranges as examples. In some aspects, the voltage application device 112 applies a voltage between the top and bottom electrodes 106/102 within a range of 0.5 to 5 dc, or -0.5 to -5 dc. However, for specific circuit applications, an ac (alternating current) voltage can also be used. Moreover, other dc voltage ranges can be used for different variations of CMR materials, CMR volume, and electric field processing. Using the above bias voltage, depending on the CMR material and the -12 · (8) (8) 1231509 geometry (volume, diameter 108, and thickness) of the CMR film 104, between the top and bottom electrodes 106/102 The inductance 114 may be in a range greater than 0.001 microhenry (// H) and less than 1 A Η. Generally, the inductance 値 L (1 14) between the top and bottom electrodes 10 6/1 2 is a maximum value in response to a voltage applied to + ldc volt or-ldc volt. However, the relationship between the maximum inductance and the bias voltage again depends on the CMR material and CMR geometry. Fig. 2 is a sectional view of a device structure in which two inductors according to the present invention are applied to an actual 1C integrated circuit. As shown in FIG. 2, the inductor 100 according to the present invention has a two-terminal cylindrical structure. The inductor can be made as a single channel hole, with a bottom electrode to a pn junction, or a metal wire connected to one part. After the front end of the process is completed, the inductor 100 can be integrated into 1C. In device A 200, the inductor 100 can be integrated into a drain junction 202. At device B 204, another inductor 100 is integrated into a gate electrode 206. The inductor (s) 100 may be applied to a semiconductor substrate using conventional deposition methods such as spin coating, sputtering, and CVD (chemical vapor deposition) methods. Moreover, the inductor 100 has a very high inductance and uses a bias control that can be changed by two orders of magnitude. Inductor 100 is part of any LC circuit whose tuning can be achieved by adjusting the bias voltage across inductor 100. For example, the inductor 100 according to the present invention may be formed using a giant magnetoresistive (CMR) film formed by a spin coating method. The CMR material may be PCMO (Pr 0.3 CaO 7MnO 3). The CMR film was applied three times for a total thickness of about 200 亳 micron (nm) to a platinum substrate. The c MR film was annealed at 650 ° C for 30 minutes after the first coating, and -13- (9) 1231509 was annealed at 5 50 ° C for 30 minutes after the second and third coatings. The top electrode 106 is also platinum, but several other metals such as Al, Cu, W, Ir, A1SI, or other precious metals may be used. Immediately after manufacture or as produced, the CMR film 104 is measured to have a resistance R due to the resistive element and a capacitance C due to the capacitive element. Figure 3 illustrates the reactance of an exemplary CMR film before electric field processing. All measurements shown in Figure 3 are resistances in series with the inductor 値. The measurement frequency is 1 MHz. The measured inductance shown is negative and therefore capacitive. Figure 3 also shows that the capacitance and resistance of this CMR film are actually independent of the bias voltage at a given measurement location. Figure 4 illustrates the reactance of this exemplary CMR film after electric field treatment.

如圖4中所示，0.4MV/cm至lMV/cm之電場經由頂 電極106及底電極102加至CMR薄膜104後，阻抗之特 性急劇改變。CMR薄膜104之電阻自約275歐姆減少至 低於20歐姆。CMR薄膜104響應-5V至-0.5V，或0.5V 至5 V之偏壓而變成電感性。在此等偏壓範圍以外，CMR 薄膜104之電抗爲電容性。最大電感超過1//H。 改變加至該裝置之偏壓，PCMO固態電感器100之電 感値藉以可變化超過二個量級。自材料之性質，預期巨大 磁阻（CMR)及高溫超導體（HTSC )材料，對電可調諧 固態電感器製造爲切合實用。裝置面積確定電感之量級。 電可調諧電感器1 〇 〇適合作爲一種供任何積體電路之濾波 -14· (10) (10)1231509 器及天線之內建元件。 圖5爲流程圖，例示一根據本發明之電感器100，其 製造方法之一種實施例。 如圖5中所示，雖然爲說明淸楚，電感器100之製造 方法示爲一序列編號步驟，但除非明確說明，不應自編號 推斷順序。請予暸解，若干此等步驟可跳過，並行進行， 或進行若干此等步驟，而無需維持序列之嚴格順序。 如圖5中所示，固態電感器100之製造在步驟500開 始。 步驟502形成一底電極102。 步驟504形成一巨大磁阻（CMR)薄膜104覆蓋底電 極 1 02 〇 步驟506形成一頂電極106覆蓋CMR薄膜104。 步驟5 08施加一種電場處理至CMR薄膜104。要不 然，步驟508施加一電場，同時使 CMR薄膜104退火。 步驟510響應該電場處理，將CMR薄膜104轉變爲 一 CMR薄膜電感器100。 現在，將更詳細說明電感器1 〇〇之以上製造方法。有 些方面包括另外之步驟。在步驟510後面之步驟512在頂 與底電極之間施加一偏壓。 步驟514響應所施加之偏壓在頂電極106與底電極 102之間造成一電感。 在其他方面，步驟5 1 6改變所施加之偏壓。 步驟5 1 8響應在所施加之偏壓之變化而改變電感。 -15- (11) 1231509 然後，回至步驟504，形成一 cMR薄膜104覆蓋底 電極1〇2包括使用一種材料諸如pr()3Ca〇.7Mn03(PCMO )J La〇.7Ca〇.3Mn〇3 ( LCMO ) ，Yi_xCaxMn03 ( YCMO ) ，或高溫超導體（HT SC)材料。在有些方面，依上述之 變化而定，將CMR薄膜104形成至厚度約2000埃。 在有些方面，在步驟5 04形成一CMR薄膜覆蓋底電 極102包括子步驟504a至504f。 首先，步驟504a旋塗一第一層有一厚度約670埃。 其次，步驟504b使第一層在溫度約650度攝氏退火 約3 0分鐘之期間。 然後，步驟504c旋塗一第二層有一厚度約670埃， 覆蓋第一層。 然後，步驟504d使第二層在溫度約550度攝氏退火 約3 0分鐘之期間。 然後，步驟504e旋塗一第三層有一厚度約670埃， 覆蓋第二層。 最後’步驟504f使第三層在溫度約550度攝氏退火 約3 0分鐘之期間。 在該方法之有些方面，在步驟502形成一底電極102 包括自一種材料諸如Al，Au，Ti，Ta，Pt，Cu，W，Ir， A1 Si或其他貴金屬形成—底電極i〇2 ^同樣，在步驟506 形成一頂電極106包括自一種材料諸如A卜Au，Ti，Ta ，Pt，Cu，W，Ir，AlSi或其他貴金屬形成一頂電極106 -16- (12) (12)1231509 再者，在有些方面，在步驟508施加一電場處理至 CMR薄膜104包括在0.4至1百萬伏/公分（MV/cm )之 範圍，而脈衝寬度在100毫微秒（ns)至1毫秒（ms)之 範圍施加電場。 再者，在有些方面，在步驟512，在頂電極106與底 電極102之間施加偏壓包括在頂電極106與底電極102之 間施加一 dc (直流）電壓在0.5至5伏之範圍以內；及一 dc (直流）電壓在- 0.5至-5伏之範圍以內之偏壓。在步驟 514，在頂電極106與底電極102之間造成一電感，包括 造成一在大於0.01微亨利（//H)至少於1//H之範圍之 電感。 在有些方面，在步驟518響應在所施加偏壓之變化而 改變底與底電極間之電感包括在約+ldc伏或約-ldc之偏 壓造成最大電感。 如以上所說明，本發明之一種實施例包括：一形成一 底電極102之步驟；一形成一巨大磁阻（CMR)薄膜104 覆蓋底電極102之步驟：一形成一頂電極1〇6覆蓋CMR 薄膜104之步驟；一在〇·4至1百萬伏/公分（MV/cm)之 範圍，而脈衝寬度在100毫微秒（ns)至1毫秒（ms)之 範圍施加一種電場處理之步驟；一響應該電場處理，將 CMR薄膜104轉變爲一 CMR薄膜電感器之步驟；一在頂 電極106與底電極102之間施加一偏壓之步驟；及一響應 所施加之偏壓在頂電極106與底電極1〇2之間造成一電感 之步驟。在所施加之偏壓變化時，電感響應變化而變化。 -17- (13) (13)1231509 因此，可減低電感器之大小，而具有大電感値。再者，在 1C電路改變電感値，允許更容易進行調諧。 根據本發明之電感器1〇〇具有較之僅只此等實例更爲 寬廣之應用。同樣，在本案曾列舉一種例證性製造過程， 但固態電感器可使用同等過程及材料製成。精於該技藝者 將會想出本發明之其他種種變化及實施例。 如以上所說明，根據本發明，可減低電感器之大小， 而具有大電感値。再者，在1C電路改變電感値，允許更 容易進行調諧。 精於該技藝者將會明白及容易作成各種其他修改，而 不偏離本發明之範圍及精神。因之，附於本案之申請專利 範圍之範圍不意爲限於如在本案所闡示之說明，而是申請 專利範圍予以廣義解釋。 【圖式簡單說明】 圖1爲示意圖，示一根據本發明之電感器之槪括結構 〇 圖2爲一裝置結構之剖面圖，其中二根據本發明之電 感器施加至一實際1C積體電路。 圖3例示在電場處理前，一例證性CMR薄膜之電抗 〇 圖4例示在電場處理後，該例證性CMR薄膜之電抗 〇 圖5爲流程圖，例示一根據本發明之電感器，其製造 -18 - (14) (14)1231509 方法之一種實施例。 【主要元件對照表】 1 0 0 電 感 器 102 底 電 極 104 巨 大 磁阻 薄膜 106 頂 電 極 108 直 徑 1 12 電 壓 施加 裝置 L ( 114) 電感値 200 裝 置 A 202 汲 極 接合 處 204 裝 置 B 206 閘 電 極As shown in Fig. 4, after an electric field of 0.4 MV / cm to 1 MV / cm is applied to the CMR film 104 via the top electrode 106 and the bottom electrode 102, the characteristics of the impedance change dramatically. The resistance of the CMR film 104 decreases from about 275 ohms to less than 20 ohms. The CMR film 104 becomes inductive in response to a bias voltage of -5V to -0.5V, or 0.5V to 5V. Outside of these bias ranges, the reactance of the CMR film 104 is capacitive. The maximum inductance exceeds 1 // H. By changing the bias voltage applied to the device, the inductance of the PCMO solid-state inductor 100 can be changed by more than two orders of magnitude. From the nature of the materials, it is expected that huge magnetoresistive (CMR) and high temperature superconductor (HTSC) materials are suitable for the manufacture of electrically tunable solid-state inductors. The device area determines the magnitude of the inductance. The electrically tunable inductor 1 is suitable as a filter for any integrated circuit. -14 · (10) (10) 1231509 Built-in components for antennas and antennas. FIG. 5 is a flowchart illustrating an embodiment of a method of manufacturing the inductor 100 according to the present invention. As shown in FIG. 5, although the manufacturing method of the inductor 100 is shown as a serial numbering step for the sake of illustration, the order should not be inferred from the numbering unless explicitly stated. Please be aware that a number of these steps can be skipped, performed in parallel, or a number of these steps can be performed without maintaining the exact order of the sequence. As shown in FIG. 5, manufacturing of the solid-state inductor 100 begins at step 500. Step 502 forms a bottom electrode 102. Step 504 forms a giant magnetoresistive (CMR) film 104 to cover the bottom electrode 102. Step 506 forms a top electrode 106 to cover the CMR film 104. Step 508 applies an electric field treatment to the CMR film 104. Otherwise, an electric field is applied in step 508 while annealing the CMR film 104. In step 510, the CMR film 104 is transformed into a CMR film inductor 100 in response to the electric field processing. Now, the manufacturing method of the inductor 1000 or more will be described in more detail. Some aspects include additional steps. Step 512 after step 510 applies a bias voltage between the top and bottom electrodes. Step 514 creates an inductance between the top electrode 106 and the bottom electrode 102 in response to the applied bias voltage. In other aspects, step 5 16 changes the applied bias voltage. Step 5 18 changes the inductance in response to a change in the applied bias voltage. -15- (11) 1231509 Then, returning to step 504, forming a cMR film 104 covering the bottom electrode 102 includes using a material such as pr () 3Ca〇7Mn03 (PCMO) J La〇7Ca〇3Mn〇3 (LCMO), Yi_xCaxMn03 (YCMO), or high temperature superconductor (HT SC) materials. In some aspects, the CMR film 104 is formed to a thickness of about 2000 angstroms depending on the above-mentioned changes. In some aspects, forming a CMR film covering the bottom electrode 102 at step 504 includes sub-steps 504a to 504f. First, in step 504a, a first layer is spin-coated with a thickness of about 670 angstroms. Next, step 504b allows the first layer to be annealed at a temperature of about 650 degrees Celsius for a period of about 30 minutes. Then, in step 504c, a second layer is spin-coated with a thickness of about 670 angstroms to cover the first layer. Then, in step 504d, the second layer is annealed at a temperature of about 550 degrees Celsius for a period of about 30 minutes. Then, in step 504e, a third layer is spin-coated with a thickness of about 670 angstroms to cover the second layer. Finally, step 504f anneals the third layer at a temperature of about 550 degrees Celsius for about 30 minutes. In some aspects of the method, forming a bottom electrode 102 in step 502 includes forming from a material such as Al, Au, Ti, Ta, Pt, Cu, W, Ir, Al Si or other precious metals—the bottom electrode i02 In step 506, forming a top electrode 106 includes forming a top electrode 106 from a material such as Au, Ti, Ta, Pt, Cu, W, Ir, AlSi or other precious metals. 106 -16- (12) (12) 1231509 and Or, in some aspects, applying an electric field treatment to the CMR film 104 in step 508 includes a range of 0.4 to 1 million volts / cm (MV / cm), and a pulse width of 100 nanoseconds (ns) to 1 millisecond ( ms). Furthermore, in some aspects, in step 512, applying a bias voltage between the top electrode 106 and the bottom electrode 102 includes applying a dc (direct current) voltage within the range of 0.5 to 5 volts between the top electrode 106 and the bottom electrode 102. ; And a dc (direct current) voltage within a range of -0.5 to -5 volts. At step 514, an inductance is created between the top electrode 106 and the bottom electrode 102, including an inductance in a range greater than 0.01 microhenry (// H) and less than 1 // H. In some aspects, changing the inductance between the bottom and bottom electrodes in response to a change in the applied bias at step 518 includes the maximum inductance resulting from a bias voltage of about + ldc volts or about -ldc. As explained above, an embodiment of the present invention includes: a step of forming a bottom electrode 102; a step of forming a giant magnetoresistive (CMR) film 104 to cover the bottom electrode 102: a step of forming a top electrode 106 to cover the CMR Step of thin film 104; a step of applying an electric field treatment in the range of 0.4 to 1 million volts per centimeter (MV / cm) and a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms) A step of converting the CMR film 104 into a CMR film inductor in response to the electric field processing; a step of applying a bias voltage between the top electrode 106 and the bottom electrode 102; and a step of responding to the applied bias voltage on the top electrode A step of creating an inductance between 106 and the bottom electrode 102. As the applied bias voltage changes, the inductance changes in response to the change. -17- (13) (13) 1231509 Therefore, the size of the inductor can be reduced and a large inductance can be achieved. Furthermore, changing the inductance 在 in the 1C circuit allows easier tuning. The inductor 100 according to the present invention has a wider application than these examples alone. Also, an exemplary manufacturing process was cited in this case, but solid state inductors can be made using equivalent processes and materials. Those skilled in the art will come up with other variations and embodiments of the present invention. As described above, according to the present invention, it is possible to reduce the size of the inductor and to have a large inductance. Furthermore, changing the inductance 在 in the 1C circuit allows easier tuning. Those skilled in the art will understand and easily make various other modifications without departing from the scope and spirit of the invention. Therefore, the scope of the patent application attached to this case is not intended to be limited to the description as illustrated in this case, but the scope of patent application is to be interpreted broadly. [Brief description of the figure] FIG. 1 is a schematic diagram showing an integrated structure of an inductor according to the present invention. FIG. 2 is a cross-sectional view of a device structure in which two inductors according to the present invention are applied to an actual 1C integrated circuit. . Fig. 3 illustrates the reactance of an exemplary CMR film before electric field treatment. Fig. 4 illustrates the reactance of this exemplary CMR film after electric field treatment. Fig. 5 is a flowchart illustrating an inductor according to the present invention. 18-(14) (14) 1231509 An embodiment of the method. [Comparison table of main components] 1 0 0 electric sensor 102 bottom electrode 104 huge magnetoresistive film 106 top electrode 108 diameter 1 12 voltage application device L (114) inductance 値 200 device A 202 sink junction 204 device B 206 gate electrode

Claims (1)

(1) 1231509 拾、申請專利範圍 第921 0301 1號專利申請案 中文申請專利範圍修正本----一--·——--------- ： X { 民國93丨年3肖姓k?彳條:Ϊ 1________ 俯b: 1. 一種製造固態電感器之方法，包含： 形成一*底電極； 形成一巨大磁阻（CMR)薄膜覆蓋底電極； 形成一頂電極覆蓋CMR薄膜；以及 對CMR薄膜施加一電場處理，並且反應該電場處理 ，將CMR薄膜轉變爲一 CMR薄膜電感器。 2 ·根據申請專利範圍第1項的製造固態電感器之方法 ，進一步包含： 在頂與底電極之間施加一偏壓，並反應所施加之偏壓 ，在頂與底電極之間建立一電感。 3 ·根據申請專利範圍第2項的製造固態電感器之方法 ，另包含： 改變所施加之偏壓；以及 反應在所施加之偏壓之變化而改變電感。 4 ·根據申請專利範圍第1項的製g固態電感器之方法 ，其中形成一巨大磁阻（CMR)薄膜覆蓋底電極包括使用 一選自包括 Pr〇.3Ca〇.7Mn〇3 ( P C Μ Ο ) 、La〇.7Ca〇.3Mn〇3 (LCMO ) > Y!.xCaxMn03 ( YCMO )、及高溫超導體（ HTSC )材料之類組之材料，作爲巨大磁阻（CMR )薄膜 (2) 1231509 材料。 5 ·根據申請專利範圍第1或2項的製造固態電感器之 方法，其中形成一巨大磁阻（CMR)薄膜覆蓋底電極包括 形成一巨大磁阻（CMR)薄膜具有厚度接近2000埃。 6.根據申請專利範圍第1或4項的製造固態電感器之 方法，其中形成一巨大磁阻（CMR)薄膜覆蓋底電極包括 旋塗一有厚度接近670埃之第一層； 使第一層在溫度接近攝氏65 0度退火接近30分鐘之 期間； 旋塗一有厚度接近670埃之第二層，覆蓋第一層； 使第二層在溫度接近攝氏550度退火接近30分鐘之 期間； 旋塗一有厚度接近670埃之第三層，覆蓋第二層；以 及 使第三層在溫度接近攝氏550度退火接近30分鐘之 期間。 7 ·根據申請專利範圍第2項的製造固態電感器之方法 ’其中形成一底電極包括自一種選自包括Al、Au、Ti、 Ta、Pt、Cu、W、Ir、AlSi及其他貴金屬之類組之材料形 成該底電極。 8 ·根據申請專利範圍第1或2項的製造固態電感器之 方法’其中形成一頂電極包括自一種選自包括Al、Au、 Τί、Ta、Pt、Cu、W、lr、AlSi及其他貴金屬之類組之材 (3) 1231509 料形成該頂電極。 9 ·根據申請專利範圍第1或2項的製造固態電感器之 方法，其中施加一電場處理至C M R薄膜包括施加電場， 其具有在0.4至1百禺伏/公分（MV/cm)範圍之電場，脈 衝寬度在1 〇 0毫微秒（n s )至1毫秒（ms)之範圍的電場 〇 1 〇 ·根據申請專利範圍第3項的製造固態電感器之方 法’其中在頂與底電極之間施加偏壓包括施加一選自包括 一 dc (直流）電壓在0.5至5伏之範圍以內；及 一 dc (直流）電壓在-0.5至-5伏之範圍以內之類組 之偏壓。 1 1 ·根據申請專利範圍第2項的製造固態電感器之方 法，其中在頂與底電極之間建立一電感的步驟包括建立一 大於〇. 〇 1微亨利（// Η )小於1 // Η範圍之電感。 1 2 .根據申請專利範圍第1 0項的製造固態電感器之方 法，其中反應在所施加之偏壓之變化而改變在頂與底電極 之間的電感之步驟，包括在選自包括+ ldc伏及- Idc之類 組之一偏壓建立一最大電感。 1 3 .根據申請專利範圍第1項的製造固態電感器之方 法，其中對CMR薄膜施加一電場處理包括施加電場，而 同時使CMR薄膜退火。 1 4 · 一種製造固態電感器之方法，包含： 形成一底電極； -3- (4) 1231509 形成一巨大磁阻（CMR)薄膜覆蓋底電極； 形成一頂電極覆蓋CMR薄膜； 在0.4至1百萬伏/公分（MV/cm)之範圍，而脈衝寬 度在100毫微秒（ns)至1毫秒（ms)之範圍，對CMR 薄膜施加一電場處理，並且反應該電場處理，將CMR薄 膜轉變爲一 CMR薄膜電感器； 在頂與底電極之間施加一偏壓； 反應所施加之偏壓，在頂與底電極之間建立一電感； 以及 反應於改變偏壓，改變所施加之偏壓及改變電感。 1 5 · —種固態電感器，該電感器包含： 一底電極； 一巨大磁阻（CMR)薄膜覆蓋底電極；以及 一頂電極覆蓋CMR薄膜。 16. 根據申請專利範圍第15項之固態電感器，另包含 一裝置，用於在頂與底電極之間施加一偏壓，並且 其中反應所施加之偏壓，在頂與底電極之間建立一電 感。 17. 根據申請專利範圍第16項之固態電感器，其中 電壓施加裝置改變所施加之偏壓；以及 在頂與底電極間之電感反應於所施加偏壓之變化而改 變 〇 1 8 ·根據申請專利範圍第1 5至1 7項中任何一項之固 -4- (5) 1231509 態電感器，其中巨大磁阻（CMR)薄膜包括 P r 〇 3 C a 〇 7 Μ η Ο 3 ( P C Μ Ο ) 、La〇 7Ca〇 3Μη03 ( LCMO )、 YbxCaxMnCh ( YCMO)、及高溫超導體（HTSC)材料。 1 9 ·根據申請專利範圍第1 7項之固態電感器，其中g 大磁阻（CMR)薄膜具厚度接近2000埃。 2 〇 ·根據申請專利範圍第1 5或1 6項之固態電感器， 其中底電極包括一種選自包括Al、Au、Ti、Ta、Pt、Cvi 、W、Ir、AlSi及其他貴金屬之類組之材料。 2 1 ·根據申請專利範圍第1 5或1 6項之固態電感器， 其中頂電極係以一種選自包括Al、Au、Ti、Ta、Pt、Cu 、W、Ir、AlSi及其他貴金屬之類組之材料所形成。 2 2 .根據申請專利範圍第1 5或1 6項之固態電感器， 其中電場處理之CMR薄膜已曝露至一電場在〇.4至1百 萬伏/公分（MV/cm)之範圍，而脈衝寬度在1〇〇毫微秒 (n s )至1毫秒（m s )之範圍中。 23.根據申請專利範圍第17項之固態電感器，其中偏 壓施加裝置在頂與底電極之間施加一選自包括： 一 dc (直流）電壓在0.5至5伏之範圍以內；及 一 dc (直流）電壓在-0.5至-5伏之範圍以內之類組 之偏壓。 24·根據申請專利範圍第17項之固態電感器，其中在 頂與底電極間之電感，有一値在大於0.01微亨利（#H) 小於1 // Η之範圍。 2 5.根據申請專利範圍第23項之固態電感器，其中反 -5- (6) 1231509 應於選自包括+ldc伏及-ldc之類組一施加偏壓，在頂與 底電極間之電感爲一最大値。(1) 1231509, Patent Application Scope No. 921 0301 Patent Application No. 1 Chinese Application for Patent Scope Amendment -------------------: X {Republic of China 93 丨 year 3 Xiao surname k? 彳: Ϊ 1________ Top b: 1. A method for manufacturing a solid-state inductor, comprising: forming a bottom electrode; forming a giant magnetoresistive (CMR) film to cover the bottom electrode; forming a top electrode to cover the CMR film And applying an electric field process to the CMR film, and in response to the electric field process, transforming the CMR film into a CMR film inductor. 2 · The method for manufacturing a solid-state inductor according to item 1 of the scope of patent application, further comprising: applying a bias voltage between the top and bottom electrodes and reflecting the applied bias voltage to establish an inductance between the top and bottom electrodes . 3. The method of manufacturing a solid-state inductor according to item 2 of the scope of patent application, further comprising: changing the applied bias voltage; and changing the inductance in response to a change in the applied bias voltage. 4. The method for manufacturing a solid-state inductor according to item 1 of the scope of patent application, wherein forming a giant magnetoresistive (CMR) film to cover the bottom electrode includes using a member selected from the group consisting of Pr0.3CaCa.7Mn〇3 (PC Μ Ο ), La〇.7Ca〇.3Mn〇3 (LCMO) > Y! .XCaxMn03 (YCMO), and high temperature superconductor (HTSC) materials and other materials, as a giant magnetoresistive (CMR) film (2) 1231509 material . 5. The method of manufacturing a solid-state inductor according to item 1 or 2 of the patent application, wherein forming a giant magnetoresistive (CMR) film covering the bottom electrode includes forming a giant magnetoresistive (CMR) film having a thickness of approximately 2000 Angstroms. 6. The method for manufacturing a solid-state inductor according to item 1 or 4 of the scope of patent application, wherein forming a giant magnetoresistive (CMR) film to cover the bottom electrode includes spin coating a first layer having a thickness close to 670 angstroms; making the first layer When the temperature is close to 65 ° C and annealing for 30 minutes; spin-coat a second layer with a thickness of close to 670 Angstroms to cover the first layer; make the second layer at a temperature close to 550 ° C and anneal for 30 minutes; spin Apply a third layer with a thickness of approximately 670 angstroms to cover the second layer; and allow the third layer to anneal for approximately 30 minutes at a temperature near 550 ° C. 7. The method for manufacturing a solid-state inductor according to item 2 of the scope of the patent application, wherein the formation of a bottom electrode includes a material selected from the group consisting of Al, Au, Ti, Ta, Pt, Cu, W, Ir, AlSi, and other precious metals. The group of materials forms the bottom electrode. 8. The method for manufacturing a solid inductor according to item 1 or 2 of the scope of the patent application, wherein the formation of a top electrode includes a material selected from the group consisting of Al, Au, Τί, Ta, Pt, Cu, W, lr, AlSi and other precious metals. The group of materials (3) 1231509 is expected to form the top electrode. 9 · A method for manufacturing a solid-state inductor according to item 1 or 2 of the patent application scope, wherein applying an electric field treatment to the CMR film includes applying an electric field having an electric field in a range of 0.4 to 1 hundred volts / cm (MV / cm) Electric field with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms). 0. Method of manufacturing a solid-state inductor according to item 3 of the patent application scope, wherein between the top and bottom electrodes Applying a bias voltage includes applying a bias voltage selected from the group consisting of a dc (direct current) voltage within a range of 0.5 to 5 volts; and a dc (direct current) voltage within a range of -0.5 to -5 volts. 1 1 · The method of manufacturing a solid-state inductor according to item 2 of the scope of the patent application, wherein the step of establishing an inductance between the top and bottom electrodes includes establishing a greater than 0.001 microhenry (// Η) less than 1 // ΗRange of inductance. 1 2. The method for manufacturing a solid-state inductor according to item 10 of the scope of the patent application, wherein the step of changing the inductance between the top and bottom electrodes in response to a change in the applied bias voltage includes selecting from a group including + ldc One of the groups such as Volts and -Idc is biased to establish a maximum inductance. 1 3. The method for manufacturing a solid-state inductor according to item 1 of the scope of patent application, wherein applying an electric field treatment to the CMR film includes applying an electric field while annealing the CMR film. 1 4 · A method for manufacturing a solid-state inductor, comprising: forming a bottom electrode; -3- (4) 1231509 forming a giant magnetoresistive (CMR) film covering the bottom electrode; forming a top electrode covering the CMR film; between 0.4 and 1 In the range of millions of volts / cm (MV / cm) and the pulse width is in the range of 100 nanoseconds (ns) to 1 millisecond (ms), an electric field treatment is applied to the CMR film, and the CMR film is reflected in response to the electric field treatment Into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; responding to the applied bias voltage to establish an inductance between the top and bottom electrodes; and responding to changing the bias voltage and changing the applied bias Voltage and change inductance. 1 5 · A solid state inductor comprising: a bottom electrode; a giant magnetoresistive (CMR) film covering the bottom electrode; and a top electrode covering the CMR film. 16. The solid-state inductor according to item 15 of the scope of patent application, further comprising a device for applying a bias voltage between the top and bottom electrodes, and wherein the applied bias voltage is established between the top and bottom electrodes. Yield. 17. The solid-state inductor according to item 16 of the scope of patent application, wherein the voltage applying device changes the applied bias voltage; and the inductance between the top and bottom electrodes changes in response to a change in the applied bias voltage. A solid 4- (5) 1231509 state inductor according to any one of the patent scope Nos. 15 to 17 in which the giant magnetoresistive (CMR) film includes Pr 〇3 C a 〇7 Μ η Ο 3 (PC Μ 〇), La07Ca03M03 (LCMO), YbxCaxMnCh (YCMO), and high temperature superconductor (HTSC) materials. 19 · The solid-state inductor according to item 17 of the scope of patent application, wherein the g-large magnetoresistance (CMR) film has a thickness of approximately 2000 Angstroms. 2 〇 The solid-state inductor according to item 15 or 16 of the scope of the patent application, wherein the bottom electrode includes a member selected from the group consisting of Al, Au, Ti, Ta, Pt, Cvi, W, Ir, AlSi, and other precious metals. Of materials. 2 1 · The solid-state inductor according to item 15 or 16 of the scope of the patent application, wherein the top electrode is selected from a group including Al, Au, Ti, Ta, Pt, Cu, W, Ir, AlSi and other precious metals. Group of materials. 2 2. The solid-state inductor according to item 15 or 16 of the scope of patent application, wherein the CMR film processed by electric field has been exposed to an electric field in the range of 0.4 to 1 million volts / cm (MV / cm), and The pulse width is in the range of 100 nanoseconds (ns) to 1 millisecond (ms). 23. The solid-state inductor according to item 17 of the patent application, wherein the bias applying means applies between a top and a bottom electrode a member selected from the group consisting of: a dc (direct current) voltage within a range of 0.5 to 5 volts; and a dc (DC) Bias voltage in the range of -0.5 to -5 volts. 24. The solid-state inductor according to item 17 of the scope of patent application, wherein the inductance between the top and bottom electrodes has a range of greater than 0.01 microhenry (#H) and less than 1 // Η. 2 5. The solid-state inductor according to item 23 of the scope of patent application, wherein the anti-5- (6) 1231509 should be biased between the top and bottom electrodes selected from the group consisting of + ldc volts and -ldc. The inductance is a maximum value. -6 --6-
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