JP4158902B2 - Solid-state inductor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid state inductor and a manufacturing method thereof, and more specifically to an inductor such as a solid state inductor for an analog integrated circuit (IC) and a manufacturing method thereof.
[0002]
[Prior art]
Conventional solid state inductors (IC integrated solid inductors are referred to as IC integrated inductors) are formed from metal wires, designed in a spiral shape, and overlaid on a thick layer of insulator on a silicon substrate. Since the inductance value of the inductor formed in this way is very low, the silicon area necessary for forming an actual inductor is large. The large size inductor not only uses a very large amount of expensive IC area, but also parasitic reactance and unintended interaction with the elements adjacent to, overlaid on or underneath the inductor. Inductance is generated.
[0003]
An IC integrated inductor is a passive element. In other words, once an inductor is formed in an IC, its inductance value cannot be changed. Therefore, the inductor cannot be used for frequency tuning. Inductors for frequency tuning are desired in manufacturing various circuits such as filters, antennas, and oscillators.
[0004]
[Problems to be solved by the invention]
In the conventional IC integrated inductor, it is difficult to have a larger inductance value and to reduce the size. Further, the inductor cannot be used for frequency tuning by changing the inductance value of the IC integrated inductor.
[0005]
The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a solid-state inductor that can be reduced in size in a state having a larger inductance value, and a method for manufacturing the same.
[0006]
It is another object of the present invention to provide a solid state inductor that can be easily tuned by varying an inductance value in an IC circuit and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
The method of manufacturing a solid state inductor according to the present invention includes a step of forming a bottom electrode, a step of forming a supergiant magnetoresistive (CMR) thin film on the bottom electrode, and a supergiant magnetoresistive (CMR) thin film. Forming an upper electrode overlying the substrate, and applying electric field treatment to the supergiant magnetoresistive (CMR) thin film What Converting the giant magnetoresistive (CMR) thin film into a giant giant magnetoresistive (CMR) thin film inductor in response to the electric field treatment. Thus, the step of performing electric field treatment on the supergiant magnetoresistive (CMR) thin film has a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms), and 0.4 to 1 per centimeter. Including the step of applying an electric field in the megavolt (MV / cm) range. Therefore, the above object can be achieved.
[0008]
Preferably, in the method of manufacturing a solid state inductor according to the present invention, a bias voltage is applied between the upper electrode and the bottom electrode, and an inductance is created between the upper electrode and the bottom electrode according to the applied bias voltage. The method further includes the step of:
[0009]
Further preferably, the method of manufacturing a solid state inductor according to the present invention further includes a step of changing the applied bias voltage, and a step of changing the inductance in accordance with the change of the applied bias voltage.
[0010]
Further preferably, in the method of manufacturing a solid state inductor according to the present invention, the step of forming a supergiant magnetoresistive (CMR) thin film overlying the bottom electrode is performed using Pr as a supergiant magnetoresistive (CMR) thin film material. _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ Using a material selected from the group comprising (YCMO) and high temperature superconductor (HTSC) materials.
[0011]
Furthermore, preferably, in the method of manufacturing a solid state inductor according to the present invention, the step of forming a supergiant magnetoresistive (CMR) thin film on the bottom electrode comprises supergiant magnetoresistive (CMR) having a thickness of about 2000 mm. ) Including a step of forming a thin film.
[0012]
Further preferably, in the method of manufacturing a solid state inductor according to the present invention, the step of forming a supergiant magnetoresistive (CMR) thin film on the bottom electrode spins a first layer having a thickness of about 670 mm. Coating, annealing the first layer at about 650 degrees Celsius for about 30 minutes, and spin-coating a second layer about 670 mm thick overlying the first layer. Annealing the second layer at about 550 degrees Celsius for about 30 minutes; spin-coating a third layer about 670 mm thick on the second layer; and Annealing the third layer at about 550 degrees Celsius for about 30 minutes.
[0013]
Further preferably, in the method of manufacturing a solid state inductor according to the present invention, the step of forming the bottom electrode includes Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. Forming the bottom electrode from a material selected from the group.
[0014]
Further preferably, in the method of manufacturing a solid state inductor according to the present invention, the step of forming the upper electrode includes Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. Forming the upper electrode from a material selected from the group.
[0016]
Further preferably, in the method of manufacturing a solid state inductor according to the present invention, in the step of applying a bias voltage between the upper electrode and the bottom electrode, the bias voltage is a voltage within a range of DC 0.5 to 5 volts, And a voltage in the range of DC-0.5 to -5 volts.
[0017]
Further preferably, the step of creating an inductance between the top electrode and the bottom electrode in the method of manufacturing a solid state inductor according to the present invention includes an inductance within a range of a value greater than 0.01 microhenry (μH) to a value less than 1 μH. The process of creating is included.
[0018]
Further preferably, in the method of manufacturing a solid-state inductor according to the present invention, the step of changing the inductance between the upper electrode and the bottom electrode in accordance with the change of the applied bias voltage includes DC + 1 volts and DC-1 volts. Creating a maximum inductance with a bias voltage selected from the group including.
[0019]
Further preferably, in the method of manufacturing a solid state inductor according to the present invention, in the step of performing electric field treatment on the giant magnetoresistance (CMR) thin film, the electric field is simultaneously applied while annealing the giant magnetoresistance (CMR) thin film. Applying.
[0020]
Further preferably, the method of manufacturing a solid state inductor according to the present invention includes a step of forming a bottom electrode, a step of forming a supergiant magnetoresistive (CMR) thin film on the bottom electrode, and the supergiant magnetism. Forming a top electrode overlaid on a resistive (CMR) thin film, and a pulse width within the range of 100 nanoseconds (ns) to 1 millisecond (ms) for the supergiant magnetoresistive (CMR) thin film Then, electric field treatment in the range of 0.4 to 1 megavolt (MV / cm) per centimeter is performed, and the giant magnetoresistance (CMR) thin film inductor is changed to the giant giant magnetoresistance (CMR) thin film inductor according to the electric field treatment. A step of applying a bias voltage between the upper electrode and the bottom electrode, and a step of creating an inductance between the upper electrode and the bottom electrode according to the applied bias voltage, Indicia varying the pressure bias voltage, which comprises the step of varying the inductance in accordance with a variation in the bias voltage, the object can be achieved.
[0021]
The solid-state inductor of the present invention comprises a bottom electrode, a field-processed giant magnetoresistive (CMR) thin film overlying the bottom electrode, and an upper part overlying the field-processed giant magnetoresistive (CMR) thin film. With electrodes The electric field-treated supergiant magnetoresistive (CMR) thin film was exposed to an electric field in the range of 0.4-1 MV / cm with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms). Therefore, the above object can be achieved.
[0022]
Preferably, the solid-state inductor further includes a voltage applying means for applying a bias voltage between the upper electrode and the bottom electrode in the solid-state inductor according to the present invention, and the upper electrode and the bottom portion according to the applied bias voltage. An inductance is created between the electrodes.
[0023]
Further preferably, the voltage application means in the solid state inductor of the present invention varies the applied bias voltage, and varies the inductance between the upper electrode and the bottom electrode in accordance with the variation of the applied bias voltage.
[0024]
Furthermore, preferably, the giant magnetoresistive (CMR) thin film in the solid state inductor of the present invention is Pr. _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ At least one of (YCMO) and high temperature superconductor (HTSC) materials.
[0025]
Furthermore, preferably, the thickness of the giant magnetoresistive (CMR) thin film in the solid state inductor of the present invention is about 2000 mm.
[0026]
Further preferably, the bottom electrode in the solid state inductor of the present invention comprises a material selected from the group comprising Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals.
[0027]
Further preferably, the top electrode in the solid state inductor of the present invention is formed of a material selected from the group comprising Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. ing.
[0029]
Further preferably, the voltage applying means in the solid state inductor of the present invention applies a bias voltage between the upper electrode and the bottom electrode, and the bias voltage is a voltage within a range of DC 0.5 to 5 volts, And a voltage in the range of -0.5 to -5 volts.
[0030]
Further, preferably, the inductance value between the top electrode and the bottom electrode in the solid state inductor of the present invention is a value within a range from a value greater than 0.01 microhenry (μH) to a value less than 1 μH.
[0031]
Further preferably, the inductance between the top electrode and the bottom electrode in the solid state inductor of the present invention is a maximum value according to the applied bias voltage selected from the group including DC + 1 volts and DC-1 volts.
[0032]
With the above configuration, a relatively large inductance value and a very small chip area are required, and a conventional integrated circuit (a CMOS circuit manufactured on silicon or a compound semiconductor substrate may be used) It is possible to obtain a solid state inductor suitable for integration into a semiconductor device and a manufacturing method thereof. In addition, since the inductance value can be varied in the IC circuit, tuning can be easily performed.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a solid state inductor (hereinafter simply referred to as an inductor) and a method for manufacturing the same according to the present invention will be described with reference to the drawings.
[0034]
FIG. 1 is a diagram schematically showing a schematic configuration of an inductor according to the present invention.
[0035]
In FIG. 1, an inductor 100 includes a bottom electrode 102, an electric field processing giant magnetoresistive (CMR) thin film 104 overlaid on the bottom electrode 102, and a top electrode 106 overlaid on the CMR thin film 104. is doing.
[0036]
The CMR thin film 104 is made of Pr. _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO) or manufactured from materials such as high temperature superconductor (HTSC) materials. Other equivalent materials may be used according to requirements. The thickness t1 of the CMR thin film 104 is about 2000 mm.
[0037]
Here, in more detail, the CMR thin film 104 has a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms) and 0.4 to 1 megavolt (MV / cm) per centimeter. Exposed to a range of electric fields. This is only an exemplary process. Other processing means are also used, depending on the CMR material, the intervening material and the desired inductance value.
[0038]
The bottom electrode 102 of the inductor 100 is made of a material selected from a material group such as Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metals. Note that other conductive materials well known in the IC manufacturing field may be used. Similarly, the top electrode 106 is typically made of a material selected from the group of materials including Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metals. Is done.
[0039]
In addition, voltage applying means 112 for applying a bias voltage is provided between the upper electrode 106 and the bottom electrode 102 of the inductor 100. Typically, the inductor 100 has a part of a larger and more complicated circuit, and the bias voltage from the voltage applying means 112 and the ground zero potential relative to the bias voltage are not shown. Not connected to another member, such as a transistor circuit. The inductance or inductance value L (114) of the inductor 100 is created on the CMR thin film 104 between the upper electrode 106 and the bottom electrode 102 in accordance with the applied bias voltage from the voltage applying means 112.
[0040]
In some aspects, the voltage applying unit 112 can vary the bias voltage applied to the inductor 100. In response to fluctuations in the applied bias voltage, the inductance value L (114) between the top electrode 106 and the bottom electrode 102 varies. Several practical bias voltage ranges have been developed as an example. In some aspects, the voltage applying means 112 applies a voltage in the range of either DC 0.5-5 volts or DC-0.5--5 volts between the top electrode 106 and the bottom electrode 102. Note that in certain circuit applications, an AC voltage may be used. In addition, other DC voltage ranges may be used for different CMR materials, CMR capacitances, and electric field processing.
[0041]
By using the above bias voltage values, the inductance 114 between the top electrode 106 and the bottom electrode 102 depends on the bias voltage, the CMR material, and the geometry (capacitance, diameter 108, and thickness t1) of the CMR thin film 104. Thus, it can be in the range of a value greater than 0.01 microhenry (μH) to a value less than 1 μH. Typically, the inductance value L (114) between the top electrode 106 and the bottom electrode 102 is a maximum value depending on the applied voltage, either +1 dc volts or -1 dc volts. However, the relationship between maximum inductance value and bias voltage also depends on the CMR material and the CMR geometry.
[0042]
FIG. 2 is a cross-sectional view of the device structure when the two inductors 100 of the present invention are applied to an actual IC integrated circuit.
[0043]
As shown in FIG. 2, the inductor 100 of the present invention is a columnar structure having two terminals. Inductor 100 is fabricated in a single via hole with bottom electrode 102 on a pn junction or local interconnect metal line. Also, the inductor 100 can be integrated into the IC after the beginning of the process is complete. In the device A 200, the inductor 100 is integrated with the drain junction 202. In the device B 204, another inductor 100 is integrated with the gate electrode 206. These inductor (s) 100 may be deposited on the semiconductor substrate using conventional deposition methods, such as spin coating, sputtering, and CVD processes. Inductor 100 also has a very high inductance that can vary by more than two orders (two digits) by using bias voltage control. Tuning of any LC circuit of which inductor 100 forms a part can be accomplished by adjusting the bias voltage applied to inductor 100.
[0044]
For example, the inductor 100 of the present invention can be manufactured using a very giant magnetoresistive (CMR) thin film resistor manufactured using a spin coating process. The CMR material is, for example, PCMO (Pr _0.3 Ca _0.7 MnO ₃ ). The CMR thin film is coated three times on the platinum substrate until the total thickness is about 200 nm. The CMR thin film is annealed at 650 ° C. for 30 minutes after the first coating, and annealed at 550 ° C. for 30 minutes after the second and third coatings. The upper electrode 106 is platinum, but other metals such as Al, Cu, W, Ir, AlSi, or other noble metals may be used. The impedance of the CMR thin film 104 immediately after manufacture or as manufactured is determined to have a resistance R due to the resistance element and a capacitance C due to the capacitance element.
[0045]
FIG. 3 is a diagram illustrating reactance of an exemplary CMR thin film before electric field processing.
[0046]
All measured values in FIG. 3 are measured values for resistance values in series with inductance values. The measurement frequency is 1 MHz. The measured inductance value is negative, so it is capacitive.
[0047]
FIG. 3 also shows that the capacitance value and resistance value of the CMR thin film are actually independent of the bias voltage value in a certain measurement value range.
[0048]
FIG. 4 is a diagram illustrating reactance after electric field processing of an exemplary CMR thin film.
[0049]
As shown in FIG. 4, the impedance characteristics change significantly after an electric field of 0.4 MV / cm to 1 MV / cm is applied to the CMR thin film 104 via the top electrode 106 and the bottom electrode 102. The resistance of the CMR film 104 is reduced from about 275 ohms to less than 20 ohms. The CMR thin film 104 is inductive according to a bias voltage of −5V to −0.5V or 0.5V to 5V. At bias voltages outside these ranges, the reactance of the CMR thin film 104 is capacitance. The maximum inductance is higher than 1 μH.
[0050]
The inductance value of the PCMO solid state inductor 100 can vary more than two orders (two digits) by changing the bias voltage applied to the element. Due to the nature of the materials, giant magnetoresistance (CMR) and high temperature superconducting (HTSC) materials are expected to be practical in the manufacture of solid state inductors 100 that can be electrically tuned. The electrically tunable inductor 100 is suitable as a built-in element for any integrated circuit filter and antenna.
[0051]
FIG. 5 is a flowchart showing an embodiment of a method for manufacturing the solid state inductor 100 of the present invention.
[0052]
As shown in FIG. 5, in the manufacturing method of the inductor 100, the numbered steps are continuously shown for the sake of clarity, but the order is inferred from these numbers unless otherwise specified. Should not. Some of these steps may be skipped, performed in parallel, or need not be performed strictly in a sequential order.
[0053]
As shown in FIG. 5, in the process 500, the manufacture of the solid state inductor 100 is started.
[0054]
In step 502, the bottom electrode 102 is formed.
[0055]
Step 504 forms a supergiant magnetoresistive (CMR) thin film 104 overlying the bottom electrode 102.
[0056]
In step 506, an upper electrode is formed overlying the CMR thin film 104.
[0057]
In step 508, electric field processing is performed on the CMR thin film 104. Alternatively, in step 508, an electric field is applied simultaneously with annealing of the CMR thin film 104.
[0058]
In step 510, the CMR thin film 104 is converted to a CMR thin film inductor 100 in response to the electric field treatment.
[0059]
Here, the manufacturing method of the above inductor 100 will be described in more detail. Some aspects include additional steps. In step 512 following step 510, a bias voltage is applied between the top electrode 106 and the bottom electrode 102.
[0060]
In step 514, an inductance is created between the top electrode 106 and the bottom electrode 102 in response to the applied bias voltage.
[0061]
In other aspects, step 516 varies the applied bias voltage.
[0062]
In step 518, the inductance varies in response to variations in the applied bias voltage.
[0063]
Next, returning to step 504, the step of forming the CMR thin film 104 overlying the bottom electrode 102 comprises the steps of Pr _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO) or using a material such as a high temperature superconductor (HTSC) material. In some aspects, the CMR film 104 is formed to a thickness of about 2000 mm, depending on the variation.
[0064]
In some aspects, in step 504, forming a CMR thin film overlying the bottom electrode 102 includes substeps of steps 504a to 504f.
[0065]
First, in step 504a, a first layer about 670 mm thick is spin coated.
[0066]
Next, in step 504b, the first layer is annealed at a temperature of about 650 degrees Celsius for about 30 minutes.
[0067]
Further, in step 504c, a second layer about 670 mm thick overlying the first layer is spin coated.
[0068]
Further, in step 504d, the second layer is annealed at a temperature of about 550 degrees Celsius for about 30 minutes.
[0069]
Further, in step 504e, a third layer about 670 mm thick overlying the second layer is spin coated.
[0070]
Finally, in step 504f, the third layer is annealed at a temperature of about 550 degrees Celsius for about 30 minutes.
[0071]
In some aspects of the invention, the step of forming the bottom electrode 502 of step 502 includes forming the bottom electrode from a material such as Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metals. Forming a step. Similarly, the step of forming the upper electrode 106 in step 506 forms the upper electrode 106 from a material such as Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi or other noble metals. Process.
[0072]
In some aspects, the electric field treatment on the CMR thin film 104 in step 508 includes an electric field in a range of 0.4 to 1 megavolt (MV / cm) per centimeter with a pulse width of 100 ns to 1 ms. Applying.
[0073]
Also, in some aspects, the step of applying a bias voltage between the top electrode 106 and the bottom electrode 102 in step 512 can include a DC voltage in the range of 0.5-5 volts between the top electrode 106 and the bottom electrode 102. Or applying a bias voltage of any DC voltage within the range of -0.5 to -5 volts. Also, the step of creating an inductance between the top electrode 106 and the bottom electrode 102 in step 514 includes the step of creating an inductance in the range of a value greater than 0.01 microhenry (μH) to a value less than 1 μH.
[0074]
Also, in some aspects, the step of varying the inductance between the top electrode 106 and the bottom electrode 102 in response to variations in the applied bias voltage in step 518 can be either about DC +1 volts or about DC -1 volts. Creating a maximum inductance at a bias voltage.
[0075]
As described above, according to the embodiment of the present invention, the step of forming the bottom electrode 102, the step of forming the supergiant magnetoresistive (CMR) thin film 104 overlying the bottom electrode 102, and the layer of superposition on the CMR thin film 104 are performed. The upper electrode 106 and 0.4 to 1 megavolt (MV) per centimeter for the CMR thin film 104 with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms). / Cm) electric field treatment, a step of converting the CMR thin film 104 into a CMR thin film inductor according to the electric field treatment, a step of applying a bias voltage between the top electrode 106 and the bottom electrode 102, A step of creating an inductance between the upper electrode 106 and the bottom electrode 102 in accordance with the bias voltage. When the applied bias voltage varies, the inductance value varies accordingly. Therefore, the size can be further reduced in a state having a larger inductance value, and tuning can be easily performed by changing the inductance value in the IC circuit.
[0076]
It should be noted that the inductor 100 according to the present invention has a wider range of applications as well as these examples. Similarly, although an exemplary manufacturing process is shown, solid state inductors can be manufactured using equivalent processes and materials. Those skilled in the art will envision other variations and embodiments of the invention.
[0077]
【The invention's effect】
As described above, according to the present invention, the size can be further reduced in a state having a larger inductance value, and tuning can be easily performed by changing the inductance value in the IC circuit.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a schematic configuration of an inductor according to the present invention.
FIG. 2 is a cross-sectional view of a device structure when two inductors of the present invention are applied to an actual IC integrated circuit.
FIG. 3 is a diagram illustrating reactance of an exemplary CMR film before electric field treatment.
FIG. 4 is a diagram illustrating reactance after electric field treatment of an exemplary CMR thin film.
FIG. 5 is a flowchart showing an embodiment of the inductor manufacturing method of the present invention.
[Explanation of symbols]
100 inductor
102 Bottom electrode
104 Electric field processing super giant magnetoresistive (CMR) thin film
106 Upper electrode
112 Voltage application means

Claims (23)

Forming a bottom electrode;
Forming a supergiant magnetoresistive (CMR) thin film overlying the bottom electrode;
Forming an upper electrode overlying the supergiant magnetoresistive (CMR) thin film;
Ultra What colossal magnetoresistance (CMR) line field processing for thin film, depending on the electric field treatment, including the step of converting ultrafine giant magnetoresistive the (CMR) films in colossal magnetoresistance (CMR) thin film inductor See
The step of performing electric field treatment on the supergiant magnetoresistive (CMR) thin film has a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms), and 0.4 to 1 megavolt per centimeter ( MV / cm) range manufacturing method including solid state inductor the step of applying an electric field of the.   The solid state inductor manufacturing method according to claim 1, further comprising: applying a bias voltage between the upper electrode and the bottom electrode, and generating an inductance between the upper electrode and the bottom electrode according to the applied bias voltage. Method. Varying the applied bias voltage;
The method of manufacturing a solid state inductor according to claim 2, further comprising a step of changing the inductance according to a change in the applied bias voltage. A process of forming a supergiant magnetoresistive (CMR) thin film on the bottom electrode includes Pr _0.3 Ca _0.7 MnO ₃ (PCMO), La _{0. The} method of claim 1, comprising using a material selected from the group comprising ₇ Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO) and high temperature superconductor (HTSC) material. A manufacturing method of the described solid state inductor.   The super giant magnetoresistive (CMR) thin film overlaid on the bottom electrode includes forming a super giant magnetoresistive (CMR) thin film having a thickness of about 2000 mm. Solid state inductor manufacturing method. Forming a giant magnetoresistive (CMR) thin film overlying the bottom electrode;
Spin coating a first layer having a thickness of about 670 mm;
Annealing the first layer at about 650 degrees Celsius for about 30 minutes;
Spin coating a second layer having a thickness of about 670 mm overlying the first layer;
Annealing the second layer at about 550 degrees Celsius for about 30 minutes;
Spin coating a third layer about 670 mm thick overlying the second layer;
5. The method of manufacturing a solid state inductor according to claim 1, further comprising: annealing the third layer at about 550 degrees Celsius for about 30 minutes.   The step of forming the bottom electrode includes the step of forming the bottom electrode from a material selected from the group comprising Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. The manufacturing method of the solid state inductor of Claim 2.   The step of forming the upper electrode includes the step of forming the upper electrode from a material selected from the group including Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. The manufacturing method of the solid state inductor of Claim 1 or 2. In the step of applying a bias voltage between the top electrode and the bottom electrode, the bias voltage is:
A voltage in the range of 0.5 to 5 volts DC;
The method of manufacturing a solid state inductor according to claim 3, wherein the solid state inductor is selected from a group including a voltage within a range of DC −0.5 to −5 volts.   3. The solid state of claim 2, wherein creating an inductance between the top and bottom electrodes includes creating an inductance within a range of values greater than 0.01 microhenry (μH) to less than 1 μH. Inductor manufacturing method. The step of varying the inductance between the top electrode and the bottom electrode in response to variation of the applied bias voltage creates a maximum inductance with a bias voltage selected from the group including DC + 1 volts and DC-1 volts. The manufacturing method of the solid state inductor of Claim 9 including a process.   2. The solid state inductor according to claim 1, wherein the step of applying an electric field to the giant magnetoresistive (CMR) thin film includes the step of simultaneously applying an electric field while annealing the giant giant magnetoresistive (CMR) thin film. Production method. Forming a bottom electrode;
Forming a supergiant magnetoresistive (CMR) thin film overlying the bottom electrode;
Forming an upper electrode overlying the supergiant magnetoresistive (CMR) thin film;
With respect to the giant magnetoresistive (CMR) thin film, the pulse width is within the range of 100 nanoseconds (ns) to 1 millisecond (ms), and 0.4 to 1 megavolt (MV / cm) per centimeter. Performing a range of electric field treatments and converting the giant magnetoresistance (CMR) thin film into a giant magnetoresistance (CMR) thin film inductor in response to the field treatment;
Applying a bias voltage between the top and bottom electrodes;
Creating an inductance between the top and bottom electrodes in response to the applied bias voltage;
Varying the applied bias voltage and varying the inductance in accordance with the variation in the bias voltage. A bottom electrode;
An electric field processing giant magnetoresistive (CMR) thin film overlying the bottom electrode;
An upper electrode superimposed on the electric field treated supergiant magnetoresistive (CMR) thin film ,
The electric field treated supergiant magnetoresistive (CMR) thin film has a solid state exposed to an electric field in the range of 0.4 to 1 MV / cm with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms). Inductor. A solid state inductor further comprising a voltage applying means for applying a bias voltage between the upper electrode and the bottom electrode,
The solid state inductor according to claim 14 , wherein an inductance is created between the upper electrode and the bottom electrode in accordance with the applied bias voltage. The solid state inductor according to claim 15 , wherein the voltage application unit varies the applied bias voltage, and varies an inductance between the upper electrode and the bottom electrode in accordance with the variation of the applied bias voltage. The super giant magnetoresistive (CMR) thin film is composed of Pr _0.3 Ca _0.7 MnO ₃ (PCMO), La _0.7 Ca _0.3 MnO ₃ (LCMO), Y _1-x Ca _x MnO ₃ (YCMO). 17. A solid state inductor according to any one of claims 14 to 16 comprising at least one of a high temperature superconductor (HTSC) material. The solid state inductor of claim 16 , wherein the super giant magnetoresistive (CMR) thin film has a thickness of about 2000 mm. 16. The solid state inductor according to claim 14 or 15 , wherein the bottom electrode comprises a material selected from the group comprising Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. 16. The solid according to claim 14 or 15 , wherein the upper electrode is formed from a material selected from the group comprising Al, Au, Ti, Ta, Pt, Al, Cu, W, Ir, AlSi and other noble metals. State inductor. The voltage applying means applies a bias voltage between the upper electrode and the bottom electrode, and the bias voltage is
A voltage in the range of 0.5 to 5 volts DC;
The solid state inductor of claim 16 , wherein the solid state inductor is selected from the group comprising a voltage in the range of DC-0.5 to −5 volts. The solid state inductor according to claim 16, wherein an inductance value between the upper electrode and the bottom electrode is a value within a range of a value greater than 0.01 microhenry (μH) to a value less than 1 μH. The solid state inductor according to claim 21, wherein the inductance between the top electrode and the bottom electrode is a maximum value according to an applied bias voltage selected from the group including DC + 1 volts and DC-1 volts.

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