TWI231013B - Multilayer laminating structure of IC packing substrate and method for fabricating the same - Google Patents

Abstract

A multilayer laminating structure of IC packing substrate and method for fabricating the substrate are provided. An inner-layer substrate is formed with inner circuits on an upper surface and a lower surface thereof, and a plurality of conductive posts having predetermined thickness are formed on the inner circuits. A set of unit circuit boards with dielectric layers and first circuit layers mounted thereon, such as resin coated copper (RCC), are laminated with the inner-layer substrate by adhesive layers. Openings through the circuit layer and the dielectric layer are formed in the unit circuit board, corresponding to the conductive post of the inner-layer substrate. Then, the post formed on the inner-layer substrate can penetrate the adhesive layer to pierce into the opening of the unit circuit board, so as to electrically contact with second circuit layers applied over the other side of the dielectric layer. Therefore, inner-layer substrates and unit circuit boards are produced separately and laminated a multilayer board, so as to simplify processes and reduce working time.

Description

1231013 V. Description of the invention (1) [Technical field to which the invention belongs] ... The present invention relates to a multi-layered structure of an IC package substrate and its fabrication 'especially a semiconductor wafer carrier suitable for providing high integration (Integration) and Multi-layer structure of packaged IC package substrate and manufacturing method thereof. [Prior art]:

^ With the vigorous development of the electronics industry, electronic products have gradually entered the direction of multi-function and high-performance research and development. In order to meet the packaging requirements for integration and miniaturization of semiconductor packages, the printed circuit board (Printed Circuit Board) that provides most active and passive components and circuit loading has gradually evolved from a double-layer board. Multi-layer board (Multi-layer Board), confined to a limited space ^, through the use of interlayer connection technology (Interlayer Connection) to expand the available circuit area on the circuit board to meet the needs of integrated circuits with high electronic density (Integrated Circuit). Traditional multi-layer circuit board manufacturing methods generally use two methods: laminating press and build-up.

As shown in Figures 4A to 4C, prepare a plurality of circuit boards 4 1, 4, 2, 4 3, such as a copper box and an insulating substrate. The circuit board 4 1 is formed with upper and lower circuit layers 4 1 a, 4 1 b and conductive vias 4 1 c, and circuit boards 4 2, 4 3 are also formed with circuit layers 42a, 43a on one side, and conductive metals are formed on the other side of the circuit layers 42a, 43a Layers 42d, 43d. A prepreg 44 (Prepreg) made of fiber or thermosetting resin (such as epoxy resin, phenol polyester, etc.) is sandwiched between the circuit boards 41, 42, 43 as an adhesive layer.

17047. ptd Page 6 1231013 V. Description of the invention (2)

Layer), after the steps of laminating and heat pressing (Heat Press) the cross-over stacked circuit boards 41, 4 2, 43 are laminated into a multilayer bonding board; then drilling technology (D ri 1 1 i ng) drill a plurality of through-holes 4 5 'a conductive metal layer is overlaid on the surface of the through-hole 45 5 wall, and the circuit patterning is performed on the outermost conductive metal layers 4 2d, 4 3d (Patterning ) The circuit layers 42b and 43b are made, and the circuit boards 41, 42, 43 can be electrically connected through the through holes 45 to obtain a multilayer circuit board 40 having six circuit layers. However, manufacturing multilayer circuit boards by pressing has obvious limitations on the number of layers and holes, so it is difficult to apply to package products with high-density electrical connection ends (I / 0 Connect i ons), and it cannot be used as a multi-chip. Sources of substrates for semiconductor packages such as Multiple Chip Module (MCM) or Chip Scale Package (CSP). In view of this, the industry proposes a method for manufacturing multilayer boards by a build-up method (Bui Id ~ Up). The multi-layer board manufacturing by the build-up method generally includes two stages, namely the inner substrate process and the circuit build-up process. As shown in FIG. 5A, an inner substrate 51 (Inner Substrate) is prepared. The inner substrate 51 is composed of a resin core layer 5 1 1 having a predetermined thickness and copper formed on both sides of the core layer 5 1 丨A foil pattern 5 1 2 is formed. The resin core layer 5 1 1 is formed with a plurality of plating through holes 513 (Plating Through Holes, PTH), thereby electrically connecting copper on both sides of the resin core layer 5 1 1. Box pattern 5 丨 2; Then, as shown in Figures 5B and 5C, the inner substrate 51 is subjected to a build-up process, and a dielectric resin layer 55 is arranged on the front and back sides of the inner substrate 51. The dielectric resin layer 5 5 is provided with a plurality of blind holes connected to the copper foil pattern 5 1 2.

17047. ptd Page 7 1231013 V. Description of the invention (3)

5 5 2. After the electroplating operation is completed, a metal conductive layer 553 is plated on the exposed surface of the dielectric resin layer 5 5 (including the blind hole hole wall). Therefore, the patterned metal conductive layer can be electrically connected to the copper foil pattern 5 1 2 through the metal conductive layer on the wall of the blind hole 55 2 to form a first build-up circuit layer 5 6; similarly, the first build-up layer On the outermost surface of the circuit layer 56, a second build-up circuit layer 57 can be repeatedly formed using the same method. As shown in FIG. 5D, a multi-layer circuit board 50 with six-layer circuit layers can be gradually added. However, in the above process, the formation of the build-up circuit must be completed layer by layer from the inside to the outside, and the same process is repeated. If one of the layers in the build-up process is a waste product, the loss is serious, so it is in mass production. (Mass Production) is extremely time-consuming and costly, which is not conducive to mass production. Therefore, how to obtain a multi-layer IC packaging substrate manufacturing method that effectively solves the problems of the above-mentioned lamination and build-up technology has become a problem to be solved at present. [Summary of the invention]: The main object of the present invention is to provide an IC package substrate that can separately produce an inner substrate and a unit circuit board, and then press together to form an IC package substrate multi-layer structure, thereby shortening the process time and simplifying the process steps. Multi-layer structure and manufacturing method thereof.

In order to achieve the disclosure and other purposes, the manufacturing method of the multi-layered structure of the IC package substrate of the present invention includes two parts, an inner substrate process and a unit circuit board lamination process, and is implemented according to the following steps: First, the inner substrate Process:

17047. ptd Page 8 1231013 V. Description of the invention (4) A core layer is provided with an upper surface and a conductive metal layer (the conductive metal has a plurality of first core substrates, the lower surface, And the upper and lower surfaces are copper); forming, covering the first and second openings which should be at the conductive opening; the conductive pillar layer and the opening of the internal electric gold are formed in advance to form a through-layer base line opening and then clear the metal layer It is planned to implement more than the two optical layers on the board; otherwise, X3X3, an early chip, a single dielectric, and a dielectric substrate are relatively opposed to each other, and an opening resistance layer is laid on the bottom. Secondly, an inner bonding layer is used to bond a unit through the first substrate structure, and an IC package bonding layer is prepared, and two circuit layer boards are formed on the hole, and the unit is pushed into a second electrical circuit repeating substrate. The first layer of the circuit layer and the first layer of the circuit layer are formed; the single electrical connection board of the layered circuit board is obtained by the aforementioned multilayer first integrated photoresistor with multiple pillars (the photoresistor has completed the single core process) A photoresist layer is formed on the substrate, and the first conductive line is on the opening; on the connection layer, a pair of apertures of the second photoresist layer are smaller than the first open Metal Posts layer, and the non-constant height is removed The welding column is formed into an inner layer substrate to form a deposition weld, a second plurality of roads, and a laminated circuit board. The unit circuit board is a first circuit layer having a dielectric surface, and most of the first circuit layer of the unit has holes. Each of the first conductive lines is welded. The circuit board uses the corresponding board as the core, and the upper and lower surfaces are respectively adhered; after the welding holes formed on the inner layer circuit puncture the openings of the circuit board, the circuit layer is formed in the dielectric layer, and thus, the outer layer The circuit can be connected to the first circuit layer and the inner layer circuit; after the inner parts are separately produced, a laminated base welding post and a unit circuit board lamination step are laminated to form a laminated structure.

17047. ptd Page 9 1231013 V. Description of the invention (5) An embodiment of the manufacturing method of the present invention is a method in which a dielectric material (such as polypropylene (p0lypr〇pyiene, pp)) is arranged between the inner substrate and the unit circuit board. , Polyimide (P0yimide), prepreg (prepreg), etc.), and the heat press method (Heat press) instead of the layer-by-layer augmentation technology, each unit circuit board pressed into a multilayer circuit Board, so that the inner layer board and the single circuit board must be electrically connected by soldering posts, thereby simplifying the manufacturing process and shortening the manufacturing time. Field-: = From the perspective of structure, there are many IC package substrates produced according to the above manufacturing method. L :: There is at least one inner substrate, and the inner substrate has-core: two inner layers formed on the upper and lower surfaces of the core substrate. The inner layer line is formed with a plurality of conductive m and a plurality of unit circuit dielectric layers and a first electrical layer formed on the surface of the dielectric layer] 2: a bonding layer for bonding the inner substrate and the unit number! Thunder; there is electrical connection between the first and second circuit layers on the dagger board, and the first conductive hole and the corresponding solder post on the inner substrate are connected to the first circuit through the second circuit layer and the conductive hole. Electrically connected to the inner-layer circuit, R is 4 inner-layer circuit. Because the conductive hole system and structure of the saponin circuit board can be large :: f 电 性 联 #, the multilayer packaging substrate formed by it is superimposed -e, and the through holes (Plat_though, Yaxi) are arranged electrically. Layer substrate, you can get a package substrate in the form of a kiln. It is called “transistor with the same circuit density.” [Embodiment]:-The second Fuwei plate: See the first figure to explain the Ic of the present invention. Multilayer laminated structure of package substrate

17047.ptd Page 10 1231013 V. Schematic sectional view of the description of the invention (6). Taking a six-layer package substrate as an example, the c-package substrate 1 of the present invention includes at least one inner substrate 10 (Inner Substrate), a plurality of unit circuit boards 1 laminated on the front and back surfaces of the inner substrate 10, and for bonding. The inner layer substrate 10 and the adhesion layer 12 of the unit circuit board 丨 丨, wherein the inner layer substrate 10 is electrically conductive by a plurality of conductive posts 103 (Conductive Posts) formed on the inner layer circuit 102. 1 1 〇 Connected to each unit circuit board. Please refer to Figures 2A to 2K below to explain the overall manufacturing process of the multi-layered structure of this IC package substrate. However, the manufacturing method of the IC package substrate of the present invention includes the inner substrate process and the unit. The circuit board stacking process has two stages. Therefore, in this embodiment, the inner substrate process and the unit circuit board stacking process are sequentially described with reference to FIGS. 2A to 2F and 2G to 2K, respectively. First, the inner substrate manufacturing process is performed: as shown in FIG. 2A, prepare as glass cloth (Glass Cloth), maleimide triazine resin (B isma 1 eimide Triazine Resin, BT Resin) or FR -4 resin, FR-5 resin (both trade names) core substrate 100 (Core Substrate), the core substrate 100 has an upper surface 100a and a relatively lower surface l 〇〇b, drill most through holes 1 0 0 c using conventional drilling technology (Dr i 1 1 ng) on the substrate 100, and then, as shown in FIG. 2B, The top and bottom surfaces of the substrate 100 are 100a, 10 Ob and the hole wall of the through hole 100c are pre-plated with a conductive metal layer 100 (such as copper), and then shown in FIG. 2C, on the conductive metal layer 101 Covering a first photoresist layer 13, the first photoresist layer 13 has a plurality of first openings 13.

17047. ptd Page 11 1231013 V. Description of the invention (7) 俾 An inner layer 102 is formed at the first opening 130 by depositing a conductive line. Next, as shown in FIG. 2D, the first photoresist A second photoresist layer 14 is further coated on the layer 13, and the second photoresist layer 14 corresponds to a predetermined position of the inner layer circuit 102 and a plurality of apertures smaller than the first opening 1 3 0 are formed. After the two openings are at 140 °, as shown in Figure 2E, traditional electroplating / electroless plating (Electro Plating / Electroless Plating), evaporation, physical vapor deposition (Physical Vapor) Deposition), Chemical Vapor

Deposition) and other methods to deposit metal solder or other conductive materials, so that after the photoresist layer is removed, a plurality of conductive posts 103 (Conductive Posts) (especially copper, copper alloys, etc.) can be formed on the predetermined inner layer circuit 102. Metal Posts are preferred). The conductive pillar 10 may be made of copper, copper alloy, aluminum, aluminum alloy, or other conductive materials. Next, as shown in FIG. 2F, the first and second photoresist layers are removed and shifted to the conductive metal layer 1 (Π of the non-conductive circuit, so that the conductive circuit 102 on the surface of the core substrate 100 is predetermined. Form a process step with a plurality of pillars 103 and board 10. Then, enter the process of stacking the unit circuit board and the lower unit circuit between the unit circuit board stack circuit board and the inner substrate, and the others are above. The lower single-layer IC package substrate, if the upper layer is used; but to clearly show the unit relationship, this embodiment simply uses an upper layer as an example to briefly describe the unit circuit board and the inner circuit board and unit circuit board made outside the circuit board. Of

1231013 V. Description of the invention (8) The electrical connection mode has not deviated from the implementable scope of the present invention. Now, the steps of lamination of the upper unit circuit board and the lower unit circuit board in this embodiment will be described in detail in FIGS. 2G to 2K. However, because the components and manufacturing methods of the upper unit circuit board and the lower unit circuit board are completely It is the same because the components of the lower-layer unit circuit board having the same function as the upper-layer unit circuit board are covered according to the component symbols of the upper-layer unit circuit board.

As shown in FIG. 2G, a plurality of unit circuit boards 11 having a dielectric layer 110 and a first circuit layer 111 formed on the surface of the dielectric layer 110 are prepared. The unit circuit board 11 is provided with a through hole. The dielectric layer 110 and the plurality of openings 112 in the first circuit layer 111, and each of the openings 112 corresponds to a solder post (not shown) formed on the inner substrate. Generally, the unit circuit board 11 can be selected by depositing a copper layer on a glass fiber, a phenol resin, or an epoxy resin layer, or using a resin bonded copper junction (Resin Coated Copper). Etc. However, the production of this unit circuit board is not known, so it will not be described here. The meat is ΐf. As shown in FIG. 2H, an inner substrate 10 is taken as the core, and an adhesive layer 12 made of the inner substrate is used to adhere one

The circuit board 1U is called the upper layer unit circuit. The front layer of 1 layer is 1GGa, and the unit circuit board of 10 days is opposite to 100b. The unit circuit board is glued to the inner layer. The first circuit layer m facing the inner layer line is called ^ layer early element circuit board.) , Ίο pressure bonding, order to form on the inner road 102 and pierce the bonding layer 12 with the inner layer base, and push into the top;] the conductive pillar 10 on the line ι2 and the lower unit Circuit board 11511

17047. ptd 1231013 V. Description of the invention (9) ~-The opening ^ 12 ’is shown in Figure 21. And after 2 ′, as shown in FIG. 2J, a conductive metal layer is formed on the surface of the dielectric layer 1 1 0,: 7 1 1 2 of the unit circuit board 1, and the entire layer of conductive layer 1 1 3 is deposited above the photoresist §§ Do n% methods such as blouses, etching, etc. to make a second circuit layer 1 1 4, the conductive holes 115 of the two v electrical materials, as shown in Figure 2K. This I »can also be used to form an inner layer circuit 102 as shown in Fig. 2C of Fig. 2. The circuit layer 11 4 can be formed. Therefore, an external circuit (not shown) is applied to Ruyi. The package substrate shown in the figure can be electrically connected to the first circuit layer 111 and the inner layer circuit 102 through the second circuit layer π 4 and the conductive hole II 5, so that the inner substrate and the upper and lower unit circuit layers are electrically Lead. Therefore, after the inner layer base f 10 and the unit circuit board 11 are separately manufactured, a multi-layer substrate structure is pressed to reduce the mass production time and achieve the purpose of simplifying the manufacturing steps. As shown in FIG. 1, viewed from a structural point of view, the IC package substrate multi-layered structure 1 obtained by the above manufacturing method includes at least one inner layer substrate 10, which has a core layer substrate 100 and The inner layer circuit 100 is formed on the upper and lower surfaces of the core substrate 100 and the inner layer circuit 100, and the inner layer circuit 100 is formed with a plurality of conductive solder pillars 10 at a predetermined position; a plurality of cells A circuit board 11 having a dielectric layer 110 and a first circuit layer 111 and a second circuit layer 114 formed on the surface of the dielectric layer 110 corresponding to each other; most of the adhesive layers 12 are used for bonding the inner substrate 1 0 and the unit circuit board 11; the unit circuit board 11 is provided with a plurality of conductive holes 1 1 5 electrically connecting the first and second circuit layers 1 1 1, 1 1 4 and at least one conductive hole 1 1 5 and the inner layer Corresponding solder pillars 103 on the substrate 10 are electrically connected. The external circuit can be electrically connected to the conductive hole 11 5 through the second circuit layer 1 1 4

17047. ptd Page 14 1231013 V. Description of the invention (10) One ~ -One '----_

To the first circuit layer 1 1 1 and the inner layer back] 〇9 m lL 亓 two π, good road 1 0 2 ° Therefore, the 'inner layer substrate and Shanfan Bao road board can be produced separately, and then it ’s early in the morning结构。 Structure. On the other hand, the left-φj ^ mouth-sealed substrate is multi-layered and combined with 103 ray. Λ & Gan electrical hole 115 is electrically connected to the welding column of the inner layer circuit 102. The multilayer packaging substrate stack structure formed by it Large amount =: The technology uses the arrangement of plated through holes (PTT) 2 substrates, and a high-density seal can be obtained. 2 _ 3A and 3C show the present invention No. 1 (: multi-layered packaging substrate structure, another: embodiment, the multi-layered packaging substrate 20 can be processed as shown in Figure 2; a conductive metal layer is formed, and the processes shown in Figures 2B to 2F are repeated. In step, a conductive pillar is formed on the circuit layer 214 on the surface of the substrate, and 203 = Figure M = shown. Then, as shown in Figures 3B and 3C, the unit circuit board 2 is laminated according to the foregoing embodiment. The manufacturing steps of the adhesive layer 22 and the multi-layer packaging substrate 20 are performed, and a conductive layer is deposited, and other processes are performed to produce a circuit layer 2 1 6 on the substrate and a plurality of conductive holes 2 5 filled with a conductive material. Figure ^ shows a multi-layer structure of a package substrate 2 with ten circuit layers. This embodiment uses a hot-pressing method. (Heat Press) Instead of layer-by-layer build-up technology, each unit circuit board 21 is laminated to a multi-layer laminated substrate structure, so that the inner layer substrate and each unit circuit board 21 can be welded by the post as described in the previous embodiment. 2 〇 Electrical connection, thereby shortening mass production time and simplifying the manufacturing process. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention, the essential technology of the present invention Content ^ Broadly defined in the scope of patent application below,

17047. ptd

Page 15 1231013

17047.ptd Page 16 1231013 Simple illustration of the drawings ^ [Simplified illustration of the drawings] ································································································································································ Schematic diagram of the manufacturing process of the sealing structure method of the embodiment; Figures 3A to 3C of the substrate and the multilayer substrate are laminated. Figures 4A to 4C are schematic diagrams of the manufacturing process of the sealing structure method of the second embodiment of the present invention. Conventional hot pressing method for manufacturing multiple intentions; and schematic diagrams of layer packaging substrates 5A to 5D are diagrams for manufacturing multilayer packaging substrates by conventional layer-increasing methods 10, 41, 51 100, 511 100a 100b 100c, 41c, 513 101 102 , 41a, 41b, 512, 512 103,203 11, 21, 41, 42, 43 110,55 111,42a, 43a, 553 Blocked substrate Multi-layered inner substrate Core layer Substrate core layer Upper surface & Lower surface core layer Hole conductive metal layer inner layer conductive conductive pillar unit circuit board dielectric layer ~ circuit layer

Composite structure

17047.ptd Page 17 1231013 Brief description of the drawings 112,552 1 13, 42b, 43b 115,215 12,22,44 13 130 14 140 40, 50 45 Opening hole Second circuit layer conductive hole adhesive layer first photoresistive layer first opening Second photoresist layer, second opening, multilayer circuit board, through-hole

17047.ptd Page 18

Claims (1)

1231013 VI. Application Patent Scope 1. A method for manufacturing an IC package substrate multi-layered structure, comprising: providing at least one inner substrate and a plurality of unit circuit boards, the inner substrate having a core substrate and formed on the core substrate The inner layer circuit on the upper and lower surfaces forms a plurality of conductive welding posts with a predetermined height on the predetermined inner layer circuit, and the unit circuit board is composed of a dielectric layer and a first circuit layer formed on the surface of the dielectric layer. Among them, a plurality of openings penetrating through the dielectric layer and the first circuit layer are provided on the unit circuit board to correspond to each solder post; the inner layer substrate and the unit circuit board are bonded by a majority of adhesive layers, and the order A solder post on the inner substrate penetrates the adhesive layer and pushes into the opening of the unit circuit board; and a conductive metal layer is deposited on the outer surface of the unit circuit board and the opening of the dielectric layer to form a second circuit layer On the surface of the laminated substrate 0 2. The manufacturing method according to item 1 of the scope of patent application, wherein the welding rod is made of a metal material. 3. The manufacturing method of item 2 in the scope of patent application, wherein the metal material is copper. 4. The manufacturing method according to item 2 of the patent application scope, wherein the metal material is a copper alloy. 5. The manufacturing method according to item 1 of the scope of patent application, wherein the bonding between the inner substrate and the unit circuit board is heat-pressed. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the adhesive layer is 17047. ptd page 19 1231013 6. The scope of patent application is selected from the group consisting of polyimide (Po 1 yimi de), epoxy resin (Epoxy), polypropylene (Po 1 y pr opy 1 ene, PP) and other adhesive materials Made by one of the groups. 7. The manufacturing method according to item 1 of the patent application scope, wherein the adhesive layer is a prepreg made of an insulating resin film (Prepreg). 8. —A method for manufacturing an inner substrate for forming a multi-layer laminated structure of a package substrate, comprising: preparing a core substrate, and a conductive metal layer is formed on each of the upper and lower surfaces of the core substrate; and covering a first photoresist Layer to the conductive metal layer, the first photoresist layer has a plurality of first openings for forming conductive lines therein; a second photoresist layer is coated to the first photoresist layer, and the second photoresist layer corresponds to A plurality of second openings are formed at predetermined positions of the conductive line; a conductive material is deposited in the second openings; and the first and second photoresist layers are removed, and the conductive metal layer of the non-conductive line is removed, so that A plurality of conductive welding posts with a predetermined height are formed on the inner conductive line. 9. The manufacturing method according to item 8 of the patent application, wherein the core substrate is selected from the group consisting of glass cloth, bismaleimide triazine resin (BT Resin), FR-4 resin And FR-5 resin. 10. The manufacturing method according to item 8 of the scope of patent application, wherein the conductive metal layer is copper. 11. The manufacturing method according to item 8 of the patent application scope, wherein the conductive material is deposited 17047.ptd Page 20 1231013 6. Scope of patent application The second opening is made of a metal material. 12. The manufacturing method according to item 11 of the scope of patent application, wherein the metal material is copper. 13. The manufacturing method according to item 11 of the scope of patent application, wherein the metal material is a copper alloy. 1 4. An IC packaging substrate multi-layer structure includes: at least one inner substrate, the inner substrate including a core substrate and inner layer circuits formed on a surface of the core substrate, wherein a plurality of inner layer circuits are formed on the inner layer circuit; A conductive post with a predetermined height; a plurality of unit circuit boards having a dielectric layer and a first circuit layer and a second circuit layer formed on the surface of the dielectric layer; most of the adhesive layers for bonding the inner substrate And a unit circuit board; and the unit circuit board is provided with a plurality of conductive holes electrically connected to the first and second circuit layers, and at least one conductive hole is electrically connected to a corresponding soldering post on the inner substrate. 15. The multi-layered laminated structure of a substrate according to item 14 of the scope of patent application, wherein the bonding of the inner substrate and the unit circuit board is heat-pressed. 16. The multi-layered structure of a substrate according to item 14 of the scope of patent application, wherein the unit circuit board is formed on the inner substrate in a laminated manner. 17047.ptd Page 21