TW200418150A - Multilayer laminating structure of IC packing substrate and method for fabricating the same - Google Patents

Abstract

A multilayer laminating structure of IC packing substrate and method for fabricating the substrate are provided. An inner-layer substrate is formed with inner circuits on an upper surface and a lower surface thereof, and a plurality of conductive posts having predetermined thickness are formed on the inner circuits. A set of unit circuit boards with dielectric layers and first circuit layers mounted thereon, such as Resin Coated Copper (RCC), are laminated with the inner-layer substrate by adhesive layers. Openings through the circuit layer and the dielectric layer are formed in the unit circuit board, corresponding to the conductive post of the inner-layer substrate. Then, the post formed on the inner-layer substrate can penetrate the adhesive layer to pierce into the opening of the unit circuit board, so as to electrically contact with second circuit layers applied over the other side of the dielectric layer. Therefore, inner-layer substrates and unit circuit boards are produced separately and laminated a multilayer board, so as to simplify processes and reduce working time.

Description

200418150 • V. Description of the invention (l) [Technical field to which the invention belongs]: The present invention relates to a multi-layered structure of an IC package substrate and a manufacturing method thereof, particularly a semiconductor wafer carrier suitable for providing South Integration (Integration) And a multi-layer structure of a packaged IC package substrate and a manufacturing method thereof. -[Previous Technology]: With the vigorous development of the electronics industry, electronic products have gradually moved into a multi-functional, high-performance research and development direction. In order to meet the packaging of semiconductor packages with high integration (Miniature Integration) and miniaturization (Mini aturiza.t ion) of the package 'provided most active and passive components and printed circuit boards (Printed C ircuit B 0ard) carried by the line si also gradually Evolved from a double-layer board to a multi-layer board, confined in a limited space, and expanded the available circuit area on the circuit board by interlayer connection technology (I nter 1 ayer C ο η necti ο η) to cooperate Demand for integrated circuits with high electron density. Traditional multi-layer circuit board manufacturing methods are generally two methods: compression method (Lam i na t ng P ree s s) and layer build-up method (Bu i 1 d-up). As shown in Figs. 4A to 4C, a plurality of circuit boards 41, 4 2, 4 3, such as a copper plate and an insulating substrate, are prepared. The circuit board 41 is formed with upper and lower circuit layers 4 ·, 4 1 b. And conductive vias 4 1 c, and the circuit boards 4 2 and 4 3 are also formed with circuit layers 42a and 43a on one side, and the other side of the circuit layers 42a and 43 is formed with a conductive metal layer 42d, 43d, on the circuit board 4 丨, 42,43 'between ^ ^ — a prepreg 44 (Prepreg) made of fiber or thermosetting resin (such as epoxy resin, hope polymer, etc.) as an adhesive layer (

17047. ptd $ 6 pages 200418150

200418150 V. Description of the invention (3) 53 2. After the electroplating operation is completed, a metal conductive layer 5 5 3 is plated on the exposed surface of the dielectric resin layer 5 5 (including the wall of the blind hole). Therefore, the patterned metal conductive layer can be electrically connected to the copper foil pattern 5 1 2 through the metal conductive layer on the wall of the blind hole 55 2 to form a first build-up circuit layer 5 6; similarly, the first The circuit layer 56 can also be formed on the outermost surface repeatedly using the same method-the second layer circuit layer 57 can be gradually increased to form a multi-layer circuit board 50 with six circuit layers as shown in FIG. 5D. However, in the above process, the formation of the build-up circuit must be completed layer by layer from the inside to the outside, and the same process is repeated. If one of the layers in the build-up process is a waste product, the loss will be serious, so ♦ / product (Mass Production) is extremely time-consuming and costly, which is not conducive to mass production. Therefore, how to obtain a multi-layer IC packaging substrate manufacturing method that effectively solves the problems of the above-mentioned lamination and build-up technology has become a problem to be solved at present. [Summary of the invention]: The main object of the present invention is to provide an IC package substrate that can separately produce an inner substrate and a unit circuit board, and then press together to form an IC package substrate multi-layer structure, thereby shortening the process time and simplifying the process steps. Multi-layer structure and manufacturing method thereof. _ In order to achieve the disclosure and other purposes, the manufacturing method of the IC package substrate multi-layered laminate structure of the present invention includes two parts: an inner substrate process and a unit circuit board stacking process, and is implemented according to the following steps: First, the inner layer Substrate process:

17047. ptd page 8 200418150 V. Description of the invention (4) There is a conductive post with a guide formed in the second opening of the guide opening to form the immediate layer and the inner layer is formed, and the laminated layer passes through the inner layer. Bonding and opening the second substrate is prepared with a core substrate (and an opposite layer (such as copper); a metal layer is covered with a plurality of first openings, and the plutonium layer is deposited on the first light. The upper surface of the electric metal is conductively covered with a first electric circuit and two openings; then the metal layer is scheduled to be implemented and prepared more than the last time through the substrate, and two photoresist layers are scheduled; and then the first and second inner-shaped units are removed. Each soldering post of the dielectric layer and the dielectric layer of the film unit, Shen Yiyi, the circuit surface of the complex circuit board and the first

Core Substrate), the lower surface of the core substrate, and a plurality of second light beams are formed on each of the upper and lower surfaces, and the laminated board is made of the first and the first circuit photoresist layer and the conductive wire resistance layer. A plurality of holes (Metal barrier layer, and a predetermined height to complete the inner layer process: the unit circuit circuit layer, the majority of the layer, the first path is smaller than the second diameter of the Posts) Opening: The photoresist layer is connected to the first conductive line, so that each soldering 0 _ board system has a dielectric opening for the unit, and the circuit board is formed to correspond to the inner layer to form a unit circuit laminated layer to form a circuit. Layer and unit board structure, so that an IC package is pushed into the second electrically connected circuit board to repeat the front substrate and multiple substrates as the core, and the upper and lower surfaces are respectively bonded to each other; so that the solder pillars formed on the inner layer circuit After puncturing the hole of the circuit board of the unit, the circuit layer of the dielectric layer is formed. In this way, the outer circuit can be connected to the first circuit layer and the inner circuit; after the inner is separately produced, it is pressed into a stack. Floor Based on the steps of laminating the solder post and the unit circuit board, the laminated structure can be obtained.

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Which SI 17047. ptd page 9 200418150 V. Description of the invention (5) '' An embodiment of the manufacturing method of the present invention, a dielectric material (such as polypropylene (P ο 1 ypr 〇) is arranged between the inner substrate and the unit circuit board. py 1 ene (PP), polyimide (P ο 1 yimide), prepreg (P repreg), etc., and the hot press method (Heat Press) instead of layer-by-layer build-up ~ technology will Each unit circuit board is laminated into a multi-layer circuit board at a time, so that each inner-layer base board and the unit circuit board are electrically connected by soldering posts, thereby simplifying the manufacturing process and shortening the process time. If viewed from a structural perspective, the multi-layered structure of the IC package substrate produced according to the above-mentioned manufacturing method includes at least one inner substrate, the inner substrate having a core board and inner layer circuits formed on the upper and lower surfaces of the core substrate. A plurality of conductive soldering posts are formed at predetermined positions; a plurality of unit circuit boards have a dielectric layer and a first circuit layer and a second circuit layer formed on the surface of the dielectric layer; most of the adhesive layers are used for bonding The inner layer substrate and the unit circuit board. The unit circuit board is provided with a plurality of conductive holes electrically connected to the first and second circuit layers, and at least one conductive hole is electrically connected to a corresponding solder post on the inner layer substrate. The external circuit can be electrically connected to the first circuit layer and the inner circuit through the second circuit layer and the conductive hole. Because the conductive holes of the unit circuit board are electrically connected to the solder pillars of the inner layer circuit, the multilayer packaging substrate stack structure formed by it can greatly reduce the conventional technology for plating through holes (P 1 a 1: ingth 〇ughh · ^, PTH ) Through the arrangement of the multilayer substrate, a package substrate with high circuit density can be obtained. [Embodiment]: A first embodiment: Please refer to FIG. 1 to explain the multi-layer structure of the IC package substrate of the present invention.

17047. ptd Page 10 200418150 V. Description of the invention (6) ^ ~ -------- The surface is shown ~ The figure takes / and the layer package substrate as an example. The I c sealing board 1 of the present invention contains at least An inner substrate 10 (Inner Substrate), a plurality of unit circuit boards 正 on the front and back surfaces of the inner substrate 10, and: two adhesive layers i 2 which adhere the inner substrate 'inverse 10' and the unit circuit board ii, wherein, The inner substrate 1 G is formed by a plurality of conductors formed on its inner circuit 丨 Q 2: Welding posts 103 (Conductlve posts) are electrically connected to each unit circuit 11 ° Below the field, please read 2A to 2 Figure K details the overall manufacturing process of the multi-layer abundance structure of this IC packaging substrate. However, the manufacturing method of the packaging substrate of the present invention is a two-stage process including an inner substrate process and a unit electrical panel stacking process. For example, the second person to 2F and the second (^ to 2} [figure] are used to explain the inner substrate process and the unit circuit board stacking process in order. First, the inner substrate process is performed: as shown in Fig. 2A, prepare one Such as glass cloth (Giass Cloth), maleic acid diamine nitrite resin (Bismaleim ide Triazine

(Resin, BT Resin) or FR-4 resin, FR-5 resin (both trade names) core substrate 10 Q (Cresubstrate), the core substrate 100 has an upper surface 100 a and a Relative to the lower surface 100b, a large number of through holes 1 0 0 c are drilled on the core substrate 100 by conventional drilling technology (Dr i 1 1 i ng), and then 'as shown in FIG. 2B A conductive metal layer (such as copper) is pre-plated on the top and bottom surfaces 100a, 100b and the through hole 100 of the core substrate 100, and then as shown in FIG. 2C, The metal layer 101 is covered with a first photoresist layer 13, and the first photoresist layer 13 has a plurality of first openings i 3.

17047. ptd

200418150 V. Description of the invention (7) An inner layer circuit 102 ° is formed at the first opening 130 by depositing a conductive line. Then, as shown in FIG. 2D, another line is placed on the first photoresist layer 3 Covering one = two photoresist layers 14, the second photoresist layer 14 corresponds to the second opening '14 0 having a plurality of apertures smaller than the first opening 1 3 0 at the pre-position of the inner layer circuit 102. . After that, as shown in FIG. 2E, traditional electrolytic / electroless plating (Electroplating / Electroplating), evaporation, and physical vapor deposition (f Physical _dor Deposition) are performed at the second opening 140. Or chemical vapor deposition (chemical Vapor / Position) and other methods to deposit metal solder or other conductive materials, so that, after the removal of the resistive layer, a plurality of conductors 103 (of which Copper or copper alloy welding rods (Metal P0sts) are preferred. The conductive welding rod 103 can be made of copper, copper alloy, Shao, slaves, a μ # aluminum. Gold or other conductive materials. Next, as shown in Fig. 2F, Qingha removes the chives + △, storage + the person's first month and the second photoresist layer, and moves the conductive 峙 玖 1 η 9 box-cold report λ, 1〇 1 Make the ^% edge on the surface of the core substrate 100. The process steps to form the slave plate α 10 at the preliminaries are formed at the preliminaries. / 、 Welding pillars 10 3, and complete the inner layer base, and then enter the unit Circuit board Niebi circuit board and the internal connection between the base board from the paragraph, but to clearly indicate the unit circuit board and Unit # Di relation 'This embodiment only uses a stacking process of the upper layer, other than the upper and lower layers_ as an example to briefly describe the unit circuit board multi-layer IC package substrate. If two or more circuit boards are used to implement the inner substrate and the Unit circuit board

V. Explanation of the invention (8) When the electrical connection method is not found, the implementation range of the second graph to the first ^ Tianming is implemented. Element circuit board and lower-level unit are described in detail. In this embodiment, the circuit board and the lower-level unit circuit are the same as the upper-level circuit. = :: The efficiency of the circuit board is similar to that shown in Figure 2G. The first piece of the dielectric layer 11 has a dielectric layer 110 and a unit circuit board 11 is formed with an early element circuit board 丄 through eight layers +1 11, and most of the openings 112 of the ⑴ 'And each layer 110 corresponds to the gas-circuit layer = soldering post (not shown). Each and the inner layer substrate are formed on glass fiber (GUSS Flb and early choice of circuit board 11). Oxygen resin layer Γ, polyphenol resin (Ph e no iic) (Resm C0ated c)> two copper layers, or using resin pressing is well known ', so I will not repeat them here 6: But this unit circuit board Then, as shown in FIG. 2H, '= the inner substrate 10 on the front and back sides of the two inner substrates 10 are the cores, and one of them is respectively coated on the poly wide and epoxy resin 7 and 102. For example, the adhesive layer 12 made of Juya makes an adhesive (epoxy) or other adhesive material circuit board 1 1 (called the upper layer unit to respect the inner layer substrate 1 0 front 1 0 〇a unit 1 0 reverse 1 0 0 b Unit circuit board (^ board) and two bonded to the inner substrate with the first circuit layer 11 11 facing inward is called the lower unit circuit board) 10 respectively The order is formed in the way of spring road 102 and the inner substrate penetrates the bonding layer 12, and the conductive pillars 103 on the ^ S layer circuit 102, the upper and lower unit circuit boards ^^ 200418150 V. Description of the invention (9) ----- Opening the hole 1 1 2 as shown in FIG. 2I .: Later, as shown in FIG. 2J, a dielectric layer 1107 I is applied to the unit circuit board. 1 2 A conductive metal layer is formed on the surface, and the entire conductive layer 11 is deposited. The method of “production—the second circuit layer 1” after the development of “3,” and “insect engraving”: a plurality of conductive holes 115 filled with a conductive material, such as the first _ Shown. In addition, the first circuit layer 114 can also be formed by the method of forming the inner layer circuit 102 as shown in the aforementioned FIG. 2C. Therefore, an external circuit (not shown) can be applied to a packaging substrate such as With the second circuit layer 11 carefully conducting the conductive holes of the upper and lower unit circuit layers, the inner layer i = f unit circuit board 11 can be manufactured separately, and then pressed into a multi-layer I-layer substrate structure, thereby reducing the amount. The purpose of the production time is not coincident. As a coincidence, as shown in Figure 1, from a structural point of view, Bu, +. Drama, t 1C package substrate The multilayer structure m contains at least -inner = two pairs; the inner substrate 10 has a core substrate i 00 and a shape ^ 2 with an inner layer line g 1Q2, # 成 'on the surface 100a, 100b. The layer substrate 1 〇〇Upper and lower guards Zangu, -Banga, .. ° Inner layer line 102 is at the predetermined position = ^ welding please; a plurality of unit circuit boards 11, #circuit layer 1 1 1 and first-thunder road 厗] 厗 4 · / U 0 surface is connected to the inner substrate 10 and | —4 most adhesive layers 12 for adhesive electrical connection; :::; circuit board 11; the unit circuit board 11 is provided with few-conductive holes 115 and inner and beauty: upper 114: two conductive holes 115 'and reach. The external circuit can be electrically connected to the conductive hole 1 丨 5 by the branch 103-I circuit layer 1 1 4

17047. ptd page 14 2P0418150 V. Description of the invention (10) to the first circuit layer 111 and the inner layer circuit 102. Therefore, the inner substrate and the single circuit board can be manufactured separately, and then pressed into a multi-layer structure of a package substrate. In addition, because the conductive holes 1 1 5 of the unit circuit board are electrically connected to the solder pillars 1 0 3 of the inner layer circuit 102, the multilayer packaging substrate stack structure 1 formed by the circuit board can be greatly reduced > The arrangement of holes (Piating though hole, PTH) through the multilayer substrate can obtain a packaging substrate with high circuit density. Poor ~ Three Ijj cases:, Figures 3 A and 3 C show another example of the I c package substrate / multi-layer laminated structure of the present invention—an embodiment, a multilayer package substrate 20 can be formed on the surface as shown in Figure 2 J —Conductive metal layer, repeating the process steps shown in FIG. 2B to FIG. 2F, the conductive layer 2 0 3 can be formed on the circuit layer 2 1 4 on the substrate surface as shown in FIG. 3A. Next, as shown in FIG. 3B and FIG. 3C, according to the foregoing embodiment, a single step is performed, the process steps of the meta circuit board 2 and the adhesive layer 22 and the multi-layer packaging substrate 20 are performed, and a process of depositing a conductive layer and etching is performed. A circuit layer 2 1 6 and a plurality of conductive holes 2 1 5 filled with a conductive material are fabricated on the substrate. As shown in Figure 3C, it is a multi-layer laminated structure of the packaging substrate 2 with ten circuit layers. In this embodiment, the heat press method (Heat Press) is used to replace the layer-by-layer build-up technology to place each unit pen board 2 1 ~ times. The laminated multi-layered substrate structure is pressed, so that the inner layer substrate and each unit circuit board 21 can be electrically connected through the soldering posts 20 as in the foregoing embodiment, thereby reducing mass production time and simplifying the manufacturing process. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is-in the true meaning of the scope of the patent application described below. Completion

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17047. ptd page 16 200418150 I Schematic description ί [Schematic description]: Figure 1 is a cross-sectional view of the multi-layered structure of the IC package substrate of the present invention 丨 Intent; ’

I

I; Figures 2A to 2K are not intended for the manufacturing process of the multi-layered packaging substrate of the first embodiment of the present invention and I structure manufacturing method, and Figures 3A to 3C are the multi-layered packaging substrates of the second embodiment of the present invention. Schematic diagram of the manufacturing process of the composite structure method; Figures 4A to 4C are schematic diagrams of manufacturing a multilayer package substrate by a conventional hot pressing method; and / Figures 5A to 5D are schematic diagrams of manufacturing a multilayer package substrate by a conventional layer increasing method. 1,2 | 10,41,51 1 00, 51 1 100a 100b 100c, 41c, 513 101 Package substrate multi-layer laminated structure inner layer substrate core layer substrate core layer upper surface core layer lower surface through hole conductive metal layer 1 0 2, 4 1 a, 4 1 b, 5 1 2, 5 1 2 Inner layer circuit 1 0 3, 2 0 3 Conductive welding posts 11, 21, 41, 42, 43 Unit circuit board 110, 55 Dielectric layer first circuit Layer 1 1 1, 42a, 43a, 553

17047. ptd p. 17 200418150 Schematic description of ΐ2, 552 113, 42b, 43b 115,215 12, 22, 44 13 130 14 140 40,50 Opening second circuit layer conductive hole adhesive layer photoresist layer opening second Photoresist layer second opening multilayer circuit board through-hole '

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Claims (1)

200418150 The scope of patent application is more than one IC package substrate 1. The predetermined height of the inner layer line provided to the inner substrate surface and the openings formed in the circuit layer of the unit are made by the majority to make the openings of the inner substrate circuit board to the single conductive There is a core in one of the metal layers, and the conductive solder dielectric layer is opened to adhere to the laminated layer; and the manufacturing method of the element circuit and the laminated structure includes: a layer substrate and a plurality of unit circuits Board, the layer substrate and a plurality of pillars formed on the core layer substrate on a predetermined inner layer line, and the unit circuit board is composed of a first circuit layer on the surface of a dielectric layer, wherein: A plurality of soldering columns penetrating through the dielectric layer and the first electrical layer correspond to each other; bonding the inner substrate and the unit circuit board, 俾, / the soldering columns pierce the bonding layer and push into the outer surface of the unit electric plate and the aforementioned dielectric A layer of holes is deposited to form a second circuit layer on the surface of the laminated substrate. 2. The manufacturing method of item 1 in the scope of the patent application, wherein the welding post is made of a metal material. 3. The manufacturing method of item 2 in the scope of patent application, wherein the metal material is copper. 4. The manufacturing method according to item 2 of the patent application scope, wherein the metal material is a copper alloy. 5. The manufacturing method according to item 1 of the scope of patent application, wherein the bonding between the inner substrate and the unit circuit board is heat-pressed. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the adhesive layer is 17047. ptd page 19 200418150 6. The scope of patent application is selected from the group consisting of polyimide (P ο 1 yimide), epoxy resin (E ρ ◦ X y), polypropylene (P o 1 ypropy 1 ene, PP) and Made of one of the other groups of adhesive materials. 7. The manufacturing method according to item 1 of the patent application scope, wherein the adhesive layer is a prepreg made of an insulating resin film (Prepreg). -8. A method for manufacturing an inner layer substrate for forming a multi-layer laminated structure of a package substrate, comprising: preparing a core substrate, each of which has a conductive metal layer formed on the upper and lower surfaces thereof; A photoresist layer to the conductive metal layer, the first photoresist layer has a plurality of first openings for forming conductive lines therein; a second photoresist layer is coated to the first photoresist layer, and the second light A plurality of second openings are formed in the resistive layer corresponding to the predetermined position of the conductive line; a conductive material is deposited on the second opening; and the first and second photoresistive layers are removed, and the conductive metal layer of the non-conductive line is removed, In order to form a plurality of conductive welding posts with a predetermined height on a predetermined inner-layer conductive line. 9. The manufacturing method according to item 8 of the scope of the patent application, wherein the core layer substrate is selected from the group consisting of glass cloth, maleimide triazine resin (BT Resin), FR-4 Made of resin and FR-5 with f grease. 10. The manufacturing method according to item 8 of the scope of patent application, wherein the conductive metal layer is copper. 1 1. The manufacturing method of item 8 in the scope of patent application, wherein the conductive material is deposited 17047. ptd page 20 200418150 6. Scope of patent application The quality of the second opening is 1 2. If the scope of patent application is copper. 1 3. If the scope of patent application is the quality of copper alloy. 14. An IC package substrate having at least one inner layer base and a first plurality of adhesive layers formed on the surface of the core layer with a plurality of unit dielectric layers formed thereon; and a plurality of conductive holes of the unit circuit board, And it is electrically connected to the welding column. 1 5. According to the scope of the patent application, the inner substrate and the unit are pressed together. 1 6. According to the scope of patent application, the unit circuit board is made of a metal material. The manufacturing method of item 11, wherein the manufacturing method of item 11 of the metal material, wherein the laminated structure of the metal material includes: a board, the inner substrate includes an inner layer circuit having a core substrate surface, and the inner layer Conductive welding pillars with a predetermined height; a circuit board having a dielectric layer and formed on the circuit layer and the second circuit layer; an electrical connection for bonding the inner substrate and the unit circuit board is provided; The circuit layer has one less conductive hole and the corresponding 14-layer multi-layer laminated structure on the inner substrate. Among them, the circuit board is bonded by hot pressing (Heat 14 4-layer multi-layer laminated structure, of which, A lamination method is formed on the inner substrate. 17047.ptd Page 21