WO2023272650A1

WO2023272650A1 - Packaging substrate and manufacturing method therefor, chip packaging structure, and electronic apparatus

Info

Publication number: WO2023272650A1
Application number: PCT/CN2021/103824
Authority: WO
Inventors: 张童龙; 任亦纬
Original assignee: 华为技术有限公司
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2023-01-05
Also published as: CN117063276A

Abstract

The embodiments of present application relate to the technical field of electronic packaging. Provided are a packaging substrate and a manufacturing method therefor, a chip packaging structure, and an electronic apparatus. The package substrate of the present application comprises a plurality of stacked substrates, a first dielectric layer, and a first dielectric interconnection structure. Each substrate comprises a core plate, two first circuit structure layers, and a core plate interconnection structure penetrating the core plate. The coefficient of thermal expansion of the core plate is lower than that of the first dielectric layer. The two first circuit structure layers are respectively positioned on the upper surface and the lower surface of the core plate, and the core plate interconnection structure is electrically connected to the two first circuit structure layers. The first dielectric layer is arranged between two adjacent substrates. The first dielectric interconnection structure penetrates the first dielectric layer, and is electrically connected to the first circuit structure layers on the substrate. In the present application, the plurality of substrates having the core plates, and the first dielectric layers are arranged in a staggered manner, such that the number of core plates in the packaging substrate is increased, the average coefficient of thermal expansion of the packaging substrate is decreased, and the problem of warping deformation of the packaging substrate is reduced.

Description

A packaging substrate and its manufacturing method, chip packaging structure, electronic equipment

technical field

The present application relates to the technical field of electronic packaging, in particular to a packaging substrate and a manufacturing method thereof, a chip packaging structure, and electronic equipment.

Background technique

Packaging substrates are key materials for electronic packaging. As communication equipment, artificial intelligence (AI) and other applications have higher and higher requirements for integration, the package size of electronic packages is getting larger and larger. Since the thermal expansion coefficient (coefficient of thermal expansion, CTE) of the packaging substrate is different from that of the chip, the packaging substrate is prone to warping and deformation, which limits the size of the packaging substrate and limits the integration of more chips in the packaging shell. .

The existing packaging substrate includes a core board and organic medium layers respectively arranged on the upper surface and the lower surface of the core board. Among them, the core board, also known as the core layer, is a hard board with a specific thickness and copper clad on both sides. The coefficient of thermal expansion of the organic medium layer is relatively large, so that the coefficient of thermal expansion of the entire packaging substrate is relatively large. As a result, the package substrate will be warped and deformed when the chip generates a lot of heat.

Contents of the invention

Embodiments of the present application provide a packaging substrate and a manufacturing method thereof, a chip packaging structure, and an electronic device, which are used to solve the problem that the packaging substrate has a large thermal expansion coefficient and is prone to warping and deformation.

In order to achieve the above object, the application adopts the following technical solutions:

In a first aspect, the embodiment of the present application provides a packaging substrate. The packaging substrate includes a plurality of stacked substrates, a first dielectric layer and a first dielectric interconnection structure. Wherein, each substrate may include a core board, two first circuit structure layers, and a core board interconnection structure penetrating through the core board. The two first circuit structure layers are respectively located on the upper surface of the core board and the lower surface of the core board, and the core board interconnection structure is electrically connected to the two first circuit structure layers respectively. The first dielectric layer can be disposed between two adjacent substrates, and can bond the two adjacent substrates. The thermal expansion coefficient of the core board is smaller than the thermal expansion coefficient of the first dielectric layer. The first dielectric interconnection structure penetrates the first dielectric layer and is electrically connected to the first circuit structure layer on the substrate on both sides of the first dielectric layer. The number of the above-mentioned substrates may be two or more than two. Correspondingly, the number of the first dielectric layer can be one layer or multiple layers. The number of second dielectric interconnection structures is equal to the number of first dielectric layers.

It can be seen from the above that the packaging substrate in the embodiment of the present application includes a plurality of substrates having core boards and a first dielectric layer, and the plurality of substrates are stacked. The first dielectric layer is respectively disposed between two adjacent substrates, and is bonded to the two adjacent substrates, that is, multiple substrates and the first dielectric layer are alternately arranged. And because the upper surface of the core board of the present application and the lower surface of the core board are respectively made with a layer of first circuit structure layer, the core board is penetrated to form a core board interconnection structure electrically connected to the two layers of the first circuit structure layer, thus forming A metal interconnect layer. In addition, the first dielectric interconnection layer penetrates the first dielectric layer and is electrically connected to the first circuit structure layer on the substrate on both sides of the first dielectric layer, forming another metal interconnection layer. In this way, a multi-layer metal interconnection layer can be formed on the packaging substrate, and the multi-layer metal interconnection layer respectively constitutes a circuit structure electrically connected to the chip and the circuit board. Therefore, the packaging substrate in the embodiment of the present application can achieve the purpose of being electrically connected to the chip and the circuit board respectively. Based on the above, in the packaging substrate of the embodiment of the present application, the above-mentioned circuit structures are distributed in the first dielectric layer between adjacent core boards, which can increase the number of core boards in the packaging substrate. And because the thermal expansion coefficient of the core board is smaller than the thermal expansion coefficient of the first dielectric layer, the thermal expansion coefficient of the packaging substrate with multiple core boards is lower, and the thermal expansion coefficient of the packaging substrate is lower than that of the chips arranged on the packaging substrate. Close, the deformation of the package substrate after heating is consistent with that of the chip. Therefore, the probability of warping deformation of the packaging substrate is reduced. The packaging substrate can be manufactured with a larger area, which expands the package size boundary of the packaging substrate, so that more chips can be integrated in the plastic packaging compound.

In a possible implementation of the first aspect, the above-mentioned core board may be a glass substrate, the first dielectric layer may be a non-conductive film (non conductive film, NCF), and a glass material with a relatively low thermal expansion coefficient is used to make the core board , so that the thermal expansion coefficient of the packaging substrate can be further reduced.

In a possible implementation manner of the first aspect, the first dielectric layer includes a matrix polymer and a filler located in the matrix polymer. Wherein, the matrix polymer can be a film-forming agent in the non-conductive film, for example, the matrix polymer is a resin material. Fillers may include silica particles dispersed in a matrix polymer. Silica fillers can improve the reliability of chip packaging structures utilizing packaging substrates with non-conductive thin films.

In a possible implementation of the first aspect, the average particle size of the above-mentioned silica particles is less than 10um, which can make the non-conductive film have better smoothness and higher transparency, and can reduce the heat curing of the first dielectric film. Damage to the core board when interconnecting structures.

In a possible implementation manner of the first aspect, the two outermost substrates among the plurality of stacked substrates are respectively a top substrate and a bottom substrate. The package substrate also includes a top wiring layer and a bottom wiring layer. The top wiring layer and the bottom wiring layer are similar in structure. The top wiring layer may include a second dielectric layer, a second dielectric interconnection structure penetrating through the second dielectric layer, and a second circuit structure layer. The second dielectric layer is connected to the surface of the top substrate away from the bottom substrate. The second circuit structure layer is located on a surface of the second dielectric layer away from the top substrate, and is electrically connected to the first circuit structure layer in the top substrate through the second dielectric interconnection structure. The bottom wiring layer may include a third dielectric layer, a third dielectric interconnection structure penetrating through the third dielectric layer, and a third circuit structure layer. The third dielectric layer is connected to the surface of the bottom substrate away from the top substrate. The third circuit structure layer is located on the surface of the third dielectric layer away from the bottom substrate, and is electrically connected to the first circuit structure layer in the bottom substrate through the third dielectric interconnection structure. The top wiring layer and the bottom wiring layer can respectively form mechanical protection for the outer surface of the substrate.

In a possible implementation manner of the first aspect, both the fluidity of the second dielectric layer and the fluidity of the third dielectric layer are smaller than the fluidity of the first dielectric layer. Therefore, in the process of making the first dielectric interconnection structure, it is convenient to reflow the solder layer in the first dielectric interconnection structure and fuse the copper pillars into one structure, and to pressurize the second dielectric layer and the third dielectric layer Curing, convenient craft production.

In a second aspect, an embodiment of the present application provides a chip packaging structure, including a chip and the packaging substrate described in the foregoing embodiments. Wherein, the chip is arranged on the package substrate and is electrically connected with the package substrate. Since the packaging substrate in the chip packaging structure of the embodiment of the present application has the same structure as the packaging substrate described in the above-mentioned embodiments, they can solve the same technical problem and obtain the same technical effect, and will not be repeated here.

In a third aspect, the embodiments of the present application provide an electronic device including a motherboard and the chip packaging structure described in the above embodiments. The main board is located on the surface of the package base upper board away from the chip in the chip package structure, and is electrically connected to the chip package structure. Since the packaging substrate in the electronic device of the embodiment of the present application has the same structure as the packaging substrate described in the above-mentioned embodiments, both can solve the same technical problem and obtain the same technical effect, and will not be repeated here.

In a fourth aspect, the embodiment of the present application provides a method for manufacturing a packaging substrate, including the following steps: forming a first substrate. The step of forming the first substrate includes: providing a first core board, forming a first core board interconnection structure penetrating through the first core board, and forming a first circuit structure layer on the upper surface and the lower surface of the first core board respectively . The first core interconnect structure is electrically connected to the first circuit structure layer. Form the second substrate. The steps of forming the second substrate are similar to the steps of forming the first substrate. The step of forming the second substrate specifically includes: providing a second core board, forming a second core board interconnection structure penetrating through the second core board, and forming a layer of the first circuit structure on the upper surface and the lower surface of the second core board respectively layer; the second core board interconnection structure is electrically connected to the first circuit structure layer. A first dielectric interconnection structure is then formed on the first circuit structure layer of the first substrate. A first dielectric layer is formed on the upper surface of the first substrate with the first dielectric interconnection structure; the first dielectric interconnection structure penetrates the first dielectric layer. The second substrate is placed on the first dielectric layer on the side away from the first substrate, and the second substrate and the first substrate are bonded through the first dielectric layer; the dielectric interconnection structure and the first dielectric layer The first circuit structure layer of the first substrate and the first circuit structure layer of the second substrate on both sides of the first substrate are electrically connected. Since the packaging substrate produced by the method for manufacturing the packaging substrate in the embodiment of the present application has the same structure as the packaging substrate described in the above-mentioned embodiments, the two can solve the same technical problem and obtain the same technical effect, and will not repeat them here. .

In a possible implementation manner of the fourth aspect, forming the interconnection structure of the first core board through the first core board specifically includes: opening a blind hole on the first core board, and forming a first core board interconnection structure in the blind hole. board interconnect structure, after which the first core board is thinned to expose the bottom surface of the blind vias.

In a possible implementation manner of the fourth aspect, the step of arranging the second substrate on the side of the first dielectric layer away from the first substrate specifically includes: heating and pressing the second substrate on the first dielectric layer on the side away from the first substrate.

In a possible implementation manner of the fourth aspect, forming the first dielectric interconnection structure on the first substrate includes: forming a copper pillar on the first circuit structure layer on the first substrate. Afterwards, a solder layer is formed on the copper pillars. Moreover, when the second substrate is heated and pressed on the side away from the first substrate on the first dielectric layer, the copper pillar and the solder layer are fused into one structure and electrically connected to the first circuit structure layer on the lower surface of the second core board. The unitary structure is a first dielectric interconnection structure. When the first core board in the first substrate is bonded to the second core board in the second substrate through the first dielectric layer, the first circuit structure layer on the first substrate and the first circuit structure layer on the second substrate are simultaneously realized. A circuit structure layer is electrically connected, which saves the process flow, and the connection force between the first substrate and the second substrate is reliable.

Description of drawings

FIG. 1 is a perspective view of an electronic device according to an embodiment of the present application;

Fig. 2 is the explosion diagram of the electronic equipment of the embodiment of the present application;

FIG. 3 is a schematic structural diagram of a chip packaging structure and a motherboard in an electronic device according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a chip installed in a chip packaging structure in an electronic device according to an embodiment of the present application;

5 is a schematic structural diagram of two stacked chips installed in the chip packaging structure in the electronic device of the embodiment of the present application;

FIG. 6 is a structural schematic diagram of two chips mounted on the same layer on the packaging substrate in the chip packaging structure of the electronic device according to the embodiment of the present application;

7 is a schematic structural diagram of a packaging substrate in the related art;

FIG. 8 is a schematic structural diagram of a packaging substrate in an electronic device according to an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a packaging substrate including a top substrate and a bottom substrate in an electronic device according to an embodiment of the present application;

FIG. 10 is a schematic structural diagram of the packaging substrate in the electronic device according to the embodiment of the present application, in which the materials of the top substrate and the bottom substrate are different from those of the first substrate;

FIG. 11 is a schematic structural diagram of a packaging substrate including a first solder resist layer and a second solder resist layer in an electronic device according to an embodiment of the present application;

12 is a schematic flow diagram of a method for manufacturing a package substrate according to an embodiment of the present application;

FIG. 13 is a schematic flow diagram of forming a first substrate in a method for manufacturing a packaging substrate according to an embodiment of the present application;

(a), (b), (c), (d), (e), (f), and (g) in FIG. 14 are the various processes for forming the first substrate in the manufacturing method of the packaging substrate in the embodiment of the present application, respectively. Schematic diagram of the structure corresponding to the steps;

15 is a schematic flow diagram of forming a first core board interconnection structure penetrating through the first core board in the manufacturing method of the package substrate according to the embodiment of the present application;

16 is a schematic flow diagram of forming a second substrate in the manufacturing method of the packaging substrate according to the embodiment of the present application;

17 is a schematic flow diagram of laminating and electrically connecting the first substrate and the second substrate in the manufacturing method of the packaging substrate according to the embodiment of the present application;

(a), (b), (c), (d), and (e) in FIG. 18 are structural schematic diagrams corresponding to various process steps of forming copper pillars in the manufacturing method of the package substrate of the embodiment of the present application;

(a) and (b) in FIG. 19 are schematic structural diagrams of forming solder balls in the manufacturing method of the package substrate of the embodiment of the present application;

(a), (b), and (c) in FIG. 20 respectively represent the formation of the first dielectric layer and bonding of the first substrate, the first dielectric layer, and the second substrate in the manufacturing method of the packaging substrate of the embodiment of the present application. Structural schematic diagrams corresponding to various process steps;

(a), (b), and (c) in FIG. 21 are structural schematic diagrams corresponding to various process steps of bonding the third substrate to the second substrate in the manufacturing method of the packaging substrate of the embodiment of the present application;

(a), (b), (c), (d), and (e) in FIG. 22 are structural schematic diagrams corresponding to various process steps for forming the top wiring layer in the manufacturing method of the packaging substrate of the embodiment of the present application;

(a), (b), (c), (d), and (e) in FIG. 23 are structural schematic diagrams corresponding to various process steps for forming the bottom wiring layer in the manufacturing method of the packaging substrate according to the embodiment of the present application.

Figure number:

1000-electronic equipment, 100-screen, 200-middle frame, 300-back shell, 400-main board, 500-camera, 10-chip packaging structure, 1-packaging substrate, 112a-rewiring layer, 1121a-organic dielectric layer, 1122a-circuit structure, 1120-metal interconnection layer, 11-substrate, 11a-top substrate, 11b-bottom substrate, 111-core board, 112-first circuit structure layer, 113-core board interconnection structure, 12-first intermediary Electrical layer, 13-first dielectric interconnection structure, 14-top wiring layer, 141-second dielectric layer, 1411-second blind hole, 142-second dielectric interconnection structure, 143-second circuit structure layer, 15-bottom wiring layer, 151-third dielectric layer, 1511-third blind hole, 152-third dielectric interconnection structure, 153-third circuit structure layer, 16-first solder resist layer, 17 - second solder resist layer, 101 - first substrate, 1011 - first core board, 1012 - first blind via, 1013 - first core board interconnection structure, 1013a - first bonding layer, 1013b - first seed layer, 1014-first photoresist layer, 1014a-first window, 1015-copper pillar, 1015a-second bonding layer, 1015b-second seed layer, 1016-second photoresist layer, 1016a-second Window, 1017-solder layer, 1017a-solder ball cap, 1010-conductive pillar, 102-second substrate, 1021-second core board, 1022-second core board interconnection structure, 103-third substrate, 2-chip , 3-molding compound.

detailed description

The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

Hereinafter, the terms "first", "second", etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature.

In addition, in the present application, orientation terms such as "upper", "lower", "left", "right", "horizontal" and "vertical" are defined relative to the schematic placement orientations of components in the drawings, It should be understood that these directional terms are relative concepts, which are used for description and clarification relative to each other, and which may change accordingly according to changes in the orientation in which components are placed in the drawings.

In this application, unless otherwise specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary.

The present application provides an electronic device, which may include a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer , in-vehicle devices, wearable devices, augmented reality (augmented reality, AR) glasses, AR helmets, virtual reality (virtual reality, VR) glasses or VR helmets and other devices that need to store data. The embodiment of the present application does not specifically limit the specific form of the foregoing electronic device. For the convenience of description, the electronic device is taken as an example of a mobile phone as shown in FIG. 1 for illustration.

Please refer to FIG. 1 and FIG. 2 , FIG. 1 is a perspective view of an electronic device provided by some embodiments of the present application, and FIG. 2 is an exploded view of the electronic device shown in FIG. 1 . It can be seen from the above that, in this embodiment, the electronic device 1000 is a mobile phone. The electronic device 1000 may include a screen 100 , a middle frame 200 , a rear case 300 and a main board 400 fixed on the middle frame 200 as shown in FIG. 2 .

It can be understood that FIG. 1 and FIG. 2 only schematically show some components included in the electronic device 1000, and the actual shape, actual size, actual position and actual configuration of these components are not limited by FIG. 1 and FIG. 2 . In some other examples, the electronic device 1000 may not include the screen 100 . Alternatively, the electronic device 1000 may further include a camera 500 as shown in FIG. 2 .

In some embodiments of the present application, the electronic device 1000 may further include a chip packaging structure 10 as shown in FIG. 3 . The chip packaging structure 10 is disposed on the main board 400 and is electrically connected to the main board 400 . For example, the chip package structure 10 may be electrically connected to the main board 400 through a ball grid array (BGA) or a plurality of copper pillar bumps (CPB) arranged in an array, so that the chip package structure 10 can Signal transmission is realized with other chips or chip stack structures on the main board 400 .

It should be noted that, the above-mentioned main board 400 may be a printed circuit board (printed circuit board, PCB). The present application does not limit the number of chip packaging structures 10 on the motherboard 400 , there may be one, two or more than two.

To facilitate the description below, X, Y, and Z coordinate systems may be established in some drawings. The plane where the main board 400 shown in FIG. 3 can be an XY plane, take the main board 400 shown in FIG. The axis is a direction perpendicular to or approximately perpendicular to the main board 400 within manufacturing tolerances. It can be understood that the width dimension of the mainboard 400 is smaller than the length dimension of the mainboard 400 .

The structure of the above-mentioned chip package structure 10 is illustrated below. Referring to FIG. 4 , the chip package structure 10 may include a package substrate (substrate, SUB) 1 , a chip 2 disposed on the package substrate 1 , and a molding compound (molding) 3 for molding the chip 2 . The packaging substrate 1 is located between the motherboard 400 and the chip 2 . The chip 2 can be a bare chip (that is, a single die), and can also be a chip stack structure (that is, a plurality of bare dies are stacked). The present application does not limit the number of chips 2 packaged in the chip packaging structure 10, which can be one as shown in Figure 4, or two as shown in Figures 5 and 6, or more than two . Multiple bare chips can be stacked as shown in FIG. 5 , or can be arranged on the packaging substrate 1 in the same layer as shown in FIG. 6 .

It should be noted that the chip 2 above can be a processing chip with data processing functions, such as a central processing unit (central processing unit, CPU), a system on chip (system on chip, SOC) or an image processing unit (graphics processing unit, GPU). ) and other chips capable of processing data.

In some related technologies, the above package substrate 1 may include a core board 111 as shown in FIG. 7 and redistribution layers 112a respectively disposed on the upper surface and the lower surface. The two redistribution layers 112a are respectively used for electrical connection with the chip 2 and the main board 400 . The redistribution layer 112a may include an organic medium layer 1121a and a circuit structure 1122a located in the organic medium layer 1121a. The circuit structure 1122a is composed of multiple metal interconnection layers 1120 . Since the circuit structure 1122a having multiple metal interconnection layers 1120 is fabricated in the organic medium layer 1121a, the thickness of the organic medium layer 1121a needs to be relatively large. Since the thermal expansion coefficient of the organic medium layer 1121a is relatively large, two organic medium layers 1121a with a larger thickness will increase the thermal expansion coefficient of the entire packaging substrate 1, so that there is one core board 111 with a lower thermal expansion coefficient and two thicker ones. The packaging substrate 1 with a large organic medium layer 1121a is prone to warping and deformation.

In order to further reduce the probability of warpage of the packaging substrate 1 described above, an embodiment of the present application provides a packaging substrate 1 with a multi-layer core board 111 . Referring to FIG. 8 , the packaging substrate 1 includes a plurality of substrates 11 , and the plurality of substrates 11 are stacked. Wherein, each substrate 11 includes a core board 111 , two first circuit structure layers 112 and a core board interconnection structure 113 . The two first circuit structure layers 112 are respectively located on the upper surface of the core board 111 and the lower surface of the core board 111 . The core board interconnection structure 113 runs through the core board 1 and electrically connects the two layers of the first circuit structure layer 112 . The packaging substrate 1 further includes a first dielectric layer 12 and a first dielectric interconnection structure 13 . The first dielectric layer 12 is disposed between two adjacent substrates 11 . Moreover, the first dielectric layer 12 can be used to bond two adjacent substrates 11 . The thermal expansion coefficient of the core board 111 is smaller than the thermal expansion coefficient of the first dielectric layer 12 . The first dielectric interconnection structure 13 penetrates through the first dielectric layer 12 and is electrically connected to the first circuit structure layer 112 on the substrate 11 on both sides of the first dielectric layer 12 . Also, the numbers of the first dielectric layer 12 and the first dielectric interconnection structure 13 are equal.

It can be understood that when there are two substrates 11 in the packaging substrate 1 , the first dielectric layer 12 is one layer. When there are more than three substrates 11 in the packaging substrate 1 , both the first dielectric layer 12 and the first dielectric interconnection structure 13 are multi-layered. For example, there are four substrates 11 shown in FIG. 8 , and both the first dielectric layer 12 and the first dielectric interconnection structure 13 are three layers.

It can be seen from the above that the packaging substrate 1 of the embodiment of the present application includes a plurality of substrates 11 having core boards 111 and a first dielectric layer 12 , and the plurality of substrates 11 are stacked. The first dielectric layers 12 are respectively disposed between two adjacent substrates 11 and bond the two adjacent substrates 11 , that is, a plurality of substrates 11 and the first dielectric layers 12 are arranged alternately. And since the upper surface of the core board 111 and the lower surface of the core board 111 in the embodiment of the present application are respectively provided with a layer of first circuit structure layer 112, the core board 111 is penetrated to form a core electrically connected to both layers of the first circuit structure layer 112. plate interconnection structure 113, thereby forming a metal interconnection layer.

In addition, the first dielectric interconnection structure 13 penetrates the first dielectric layer 12 and is electrically connected to the first circuit structure layer 112 on the substrate 11 on both sides of the first dielectric layer 12, forming another layer of metal interconnect layer. In this way, a multi-layer metal interconnection layer can be formed on the package substrate 1 , and the multi-layer metal interconnection layer respectively constitutes the circuit structure in the redistribution layer electrically connected to the chip 2 and the main board 400 . Therefore, the packaging substrate 1 in the embodiment of the present application can achieve the purpose of being electrically connected to the chip 2 and the main board 400 respectively.

Based on the above, compared with the package substrate with one core board 111 and two redistribution layers 112a shown in FIG. In the first dielectric layer 12 between adjacent core boards 111 , the number of core boards 111 in the packaging substrate 1 can be increased, and the thickness of each first dielectric layer 12 can be reduced. When the thickness of the packaging substrate 1 of the embodiment of the present application is equal to or less than the thickness of the packaging substrate shown in FIG. The thickness of a layer of core board in the package substrate. And because the thermal expansion coefficient of the core board 111 is smaller than the thermal expansion coefficient of the first dielectric layer 12 , the thermal expansion coefficient of the packaging substrate 1 having multiple core boards 111 is relatively low. The thermal expansion coefficient of the package substrate 1 is relatively close to that of the chip 2 disposed on the package substrate 1 , and the deformation of the package substrate 1 and the chip 2 after being heated are consistent. Therefore, the probability of warping deformation of the packaging substrate 1 is reduced. The packaging substrate 1 can be manufactured with a larger area, which expands the package size boundary of the packaging substrate 1 , so that more chips 2 can be integrated in the plastic packaging compound 3 .

Since the thermal expansion coefficient of the core board 111 needs to be smaller than that of the first dielectric layer 12 , the core board 111 needs to be made of a material with a lower thermal expansion coefficient. The materials for making the core board 111 will be described with examples below.

For example, the core board 111 may be a glass substrate, such as quartz glass or high silica glass. The linear thermal expansion coefficient of quartz glass is 0.5×10 ^-6 /K, and the linear thermal expansion coefficient of high silica glass is 0.78×10 ^-6 /K. Thus, the thermal expansion coefficient of the packaging substrate 1 is further reduced.

As another example, the above-mentioned core board 111 can also be a ceramic substrate, such as mullite ^porcelain or alumina porcelain. 10 ^-6 /K, the thermal expansion coefficient of the core plate 111 is also low.

Since the first dielectric interconnection structure 13 needs to be fabricated in the first dielectric layer 12, when the first dielectric interconnection structure 13 is an integrated structure composed of copper pillars and solder balls after melting, the first dielectric layer 12 needs to use The semi-cured (pre-preg) sheet, and the fluidity of the first dielectric layer 12 needs to be relatively high. For example, the first dielectric layer 12 in the embodiment of the present application may be a non-conductive film, and the non-conductive film has high fluidity and reducibility. When the solder ball is a solder ball, the acidic material (such as an amine compound) in the non-conductive film can undergo a reduction reaction with the oxide layer on the outer surface of the solder ball, which facilitates the reflow of the solder ball and the melting of the copper pillar, which facilitates the process. .

The above-mentioned non-conductive film may include a matrix polymer, and fillers located in the matrix polymer, and the fillers are dispersed in the collective polymer. Wherein, the matrix polymer is a film-forming agent, which can make the non-conductive thin film have film-forming ability. And adjusting the content of the matrix polymer in the non-conductive film can adjust the fluidity, softness and transparency of the non-conductive film. The aforementioned fillers may include silica fillers, and the silica fillers can improve the reliability of a chip packaging structure utilizing a packaging substrate with a non-conductive thin film. The aforementioned matrix polymer may be a solid epoxy resin. The above-mentioned non-conductive film may also include a polymer resin, and when the non-conductive film is cured under a pressurized atmosphere, the polymer resin can help increase the toughness of the non-conductive film after curing.

Exemplarily, in some embodiments of the present application, the average particle diameter of the above-mentioned silica particles is less than 10 um. The first dielectric layer 12 adopts silicon dioxide particles in the above-mentioned particle size range, which can make the non-conductive film have better smoothness and higher transparency, and can reduce the impact on the core board when heating and curing the first dielectric interconnection structure 13. 111 injuries.

Among the packaging substrates 1 in which the plurality of substrates 11 and first dielectric layers 12 are arranged alternately, the two outermost ones are the top substrate 11a and the bottom substrate 11b as shown in FIG. 8 . Considering that the core board 111 in the substrate 11 is a glass substrate or a ceramic substrate, the toughness of the top substrate 11a and the bottom substrate 11b is poor, and they are easy to be worn or broken during transportation or assembly.

In order to solve the above problems, in some embodiments of the present application, the package substrate 1 may further include a top wiring layer 14 as shown in FIG. 9 . The top wiring layer 14 may include a second dielectric layer 141 , a second dielectric interconnection structure 142 and a second circuit structure layer 143 . The second dielectric layer 141 is connected to the surface of the top substrate 11 a away from the bottom substrate 11 b (ie, the upper surface of the top substrate 11 a in FIG. 9 ). The second dielectric interconnection structure 142 penetrates through the second dielectric layer 141 . The second circuit structure layer 143 is located on the side surface of the second dielectric layer 141 away from the top substrate 11a (ie, the upper surface of the second dielectric layer 141 in FIG. 9 ), and the second circuit structure layer 143 is interconnected through the second dielectric layer. The structure 142 is electrically connected to the first circuit structure layer 112 in the top substrate 11a (specifically, the first circuit structure layer 112 on the upper surface of the top substrate 11a). After the second circuit structure layer 143 in the top wiring layer 14 is electrically connected to the top substrate 11a through the second dielectric interconnection structure 142, a layer of metal interconnection layer in the circuit structure in which the packaging substrate 1 and the chip 2 are electrically connected can be formed. . Therefore, the top wiring layer 14 can not only form mechanical protection for the top substrate 11a, but also form a layer of metal interconnection layer in the top wiring layer 14, effectively utilize the second dielectric layer 14, and reduce the thickness of the packaging substrate 1 .

Continuing to refer to FIG. 9 , the package substrate 1 further includes a bottom wiring layer 15 , and the structure of the bottom wiring layer 15 is similar to that of the top wiring layer 14 . The bottom wiring layer 15 includes a third dielectric layer 151 , a third dielectric interconnection structure 152 and a third circuit structure layer 153 . Wherein, the third dielectric layer 151 is connected to the surface of the bottom substrate 11 b away from the top substrate 11 a (ie, the lower surface of the bottom substrate 11 b in FIG. 9 ). The third dielectric interconnection structure 152 penetrates through the third dielectric layer 151 . The third circuit structure layer 153 is located on the surface of the third dielectric layer 151 away from the bottom substrate 11 b (ie, the lower surface of the third dielectric layer 151 in FIG. 9 ). The third circuit structure layer 11b is electrically connected to the first circuit structure layer 112 in the bottom substrate 11b (specifically, to the first circuit structure layer 112 on the lower surface of the bottom substrate 11a ) through the third dielectric interconnection structure 152 .

Similarly, after the third circuit structure layer 153 in the bottom wiring layer 15 is electrically connected to the bottom substrate 11b through the third dielectric interconnection structure 152, it can form a layer of metal in the circuit structure in which the packaging substrate 1 and the motherboard 400 are electrically connected. interconnect layer. The bottom wiring layer 15 can not only form mechanical protection for the bottom substrate 11b, but also can reduce the thickness of the packaging substrate 1 as well.

Based on the above, the second dielectric layer 141 connected to the top substrate 11 a and the third dielectric layer 151 connected to the bottom substrate 11 b can be made of the same material or different materials. In the following, the second dielectric layer 141 and the third dielectric layer 151 are made of the same material for illustration.

In some embodiments of the present application, the first dielectric layer 12 , the second dielectric layer 141 and the third dielectric layer 151 are all made of non-conductive films, as shown in FIG. 9 .

Considering that the difference from the first dielectric layer 12 requires better fluidity in order to make the first dielectric interconnection structure 13, the second dielectric interconnection structure 142 in the second dielectric layer 141, and the third dielectric interconnection structure The third dielectric interconnection structure 152 in the layer 151 can be made by digging holes, sinking copper, electroplating and other processes. Therefore, in some other embodiments of the present application, the fluidity of the second dielectric layer 141 and the third dielectric layer 151 is lower than that of the first dielectric layer. For example, both the second dielectric layer 141 and the third dielectric layer 151 can adopt Ajinomoto build-up film (ajinomoto build-up film, ABF), which is convenient for the pressurization of the second dielectric layer 141 and the third dielectric layer 151. Curing, as shown in Figure 10. Of course, the second dielectric layer 141 and the third dielectric layer 151 can also use other thin film materials with properties similar to those of the Ajinomoto stacked film.

In order to protect the above-mentioned top wiring layer 14 and bottom wiring layer 15, the package substrate 1 of the embodiment of the present application further includes a first solder mask 16 and a second solder mask 17, as shown in FIG. 11 . The first solder resist layer 16 is provided on the upper surface of the top wiring layer 14 . The second solder resist layer 17 is provided on the lower surface of the bottom wiring layer 15 .

The manufacturing method of the above-mentioned package substrate is illustrated below with an example. In some embodiments of the present application, the manufacturing method of the packaging substrate 1 includes steps S100-S700 as shown in FIG. 12 , specifically as follows:

S100: forming a first substrate.

Wherein, the above step S100 may specifically include S101-S103 as shown in FIG. 13 , specifically as follows:

S101: Provide a first core board.

Exemplarily, a first core board 1011 as shown in (a) of FIG. 14 is provided. The first core plate 1011 adopts a solid plate structure made of glass.

S102: Form a first core board interconnection structure passing through the first core board.

In some embodiments of the present application, the above step S102 may specifically include S1021-S1023 as shown in FIG. 15 , specifically as follows:

S1021: Opening a first blind hole on the first core board.

Referring to (b) in FIG. 14, on the first core board 1011, chemical etching (such as chemical etching using hydrofluoric acid), laser (laser), laser induced wet etching (Laser induced wet etch) and other methods are used to open The first blind hole 1012 .

S1022: Form a first core board interconnection structure in the first blind hole.

First, a metal film such as titanium (Ti) or nickel (Ni) is formed in the first blind hole 1012 by a sputtering (physical vapor deposition, PVD) process, and the metal film is used as the first metal film as shown in (c) in FIG. Adhesive layer 1013a.

Then, a copper (Cu) layer is formed on the metal thin film by a sputtering process as a first seed layer 1013b as shown in (d) of FIG. 14 . The above sputtering process may be magnetron sputtering or ion beam sputtering.

Afterwards, the thickness of the first seed layer 1013b is increased by electroplating (electrochemical deposition, ECD), so that the first blind hole 1012 is filled with copper material, thereby forming the first core board interconnection structure as shown in (e) in FIG. 14 1013.

S1023: Thinning the first core board to expose the bottom surface of the first core board interconnection structure in the first blind hole.

In some embodiments, a back grinding (back grinding, BG) process may be used to thin the thickness of the first core board 1011 so that the bottom surface of the first core board interconnection structure 1013 in the first blind hole 1012 is exposed, as shown in FIG. 14 (f) shown. For example, the thickness of the first core board 1011 can be reduced by 20um˜100um from the bottom surface. If the first core board 1011 is a glass substrate, the above thinning process is to thin the first blind hole 1012 of the first core board 1011 into a through glass via (TGV).

S103: Forming a first circuit structure layer on the upper surface and the lower surface of the first core board respectively, and both layers of the first circuit structure layer are electrically connected to the interconnection structure of the first core board.

On the upper surface and the lower surface of the first core board 1011, a layer of first circuit structure layer 112 having conductive lines and pads can be formed respectively by using a photoresist process. Thus, the first substrate 101 as shown in (g) of FIG. 14 is formed. Wherein, the above-mentioned photoresist process refers to the process of forming patterns by using photoresist, mask plate, exposure machine, etc., including film formation, exposure, development and other process processes.

S200: forming a second substrate.

The steps of forming the second substrate are similar to the steps of forming the first substrate 101 . The above step S200 may specifically include S201-S203 as shown in FIG. 16 , specifically as follows:

S201: Provide a second core board.

S202: Form a second core board interconnection structure penetrating through the second core board.

S203: Form a first circuit structure layer on the upper surface and the lower surface of the second core board respectively, and both layers of the first circuit structure layer are electrically connected to the second core board interconnection structure.

S300: Laminate and electrically connect the first substrate and the second substrate.

The above step S300 may specifically include S301-S304 as shown in FIG. 17 , specifically as follows:

S301: Forming copper pillars on the first circuit structure layer of the first substrate.

First, a first photoresist layer 1014 as shown in (a) of FIG. 18 is coated on the first circuit structure layer 112 of the first substrate 101 . Expose the first photoresist layer 1014 to form a first window 1014a for setting copper pillars as shown in FIG. 18( b ).

Then, a second bonding layer (such as a titanium layer) 1015a as shown in (c) of FIG. 18 may be formed on the first window 1014a by using physical vapor deposition or sputtering.

Then, a copper (Cu) layer is formed on the second adhesive layer 1015a by using a physical vapor deposition process or a sputtering process as a second seed layer 1015b as shown in (d) of FIG. 18 .

Afterwards, the thickness of the second seed layer 1015b at the first window 1014a is increased by means of electrochemical deposition (ECD), so that copper pillars 1015 as shown in (e) of FIG. 18 are formed in the first window 1014a.

S302: Forming a solder layer on the copper pillar to form a conductive pillar including the copper pillar and the solder layer.

A solder layer (generally tin-silver material) 1017 is formed on the copper pillar 1015 by means of electroplating as shown in (a) of FIG. 19 . Finally, the first photoresist layer 1014 is removed by an etching process, as shown in (b) of FIG. 19 .

It should be noted that a barrier layer (for example, a nickel (Ni) layer is formed by electroplating as a barrier layer) may be formed between the copper pillar 1015 and the solder 1017 to reduce the interdiffusion of solder and copper. The height direction of the copper pillars 1015 and the thickness direction of the first photoresist layer 1014 are the same as the thickness direction of the packaging substrate 1 .

S303: Form a first dielectric layer on the upper surface of the first substrate having conductive pillars, and the conductive pillars penetrate through the first dielectric layer.

Referring to (a) of FIG. 20 , the first dielectric layer 12 can be directly bonded to the upper surface of the first substrate 101 with the conductive pillars 1010 .

S304: Disposing the second substrate on the side of the first dielectric layer away from the first substrate, and bonding the second substrate and the first substrate through the first dielectric layer.

Wherein, the conductive column 1010 is electrically connected with the first circuit structure layer 112 of the first substrate 101 and the first circuit structure layer 112 of the second substrate 102 located on both sides of the first dielectric layer 12, as shown in (b) of FIG. 20 and (c) shown.

The above step S304 specifically includes:

The second substrate 102 is heated and laminated (lamination) on the first dielectric layer 12 on the side away from the first substrate 101, and the solder layer 1017 is melted and reflowed to form an arched solder ball cap as shown in (c) in FIG. 20 At the same time, the solder ball cap 1017a in the conductive pillar 1010 and the copper pillar 1015 are fused into one structure and electrically connected to the first circuit structure layer 112 on the lower surface of the second core board 1021 . The above integrated structure is the first dielectric interconnection structure 13 .

When the first core plate 1011 in the first substrate 101 is bonded to the second core plate 1021 in the second substrate 102 through the first dielectric layer 12, the first circuit structure layer on the first substrate 101 is realized at the same time. The electrical connection between 112 and the first circuit structure layer 112 on the second substrate 102 saves the process flow, and the connection force between the first substrate 101 and the second substrate 102 is reliable.

Specifically, the solder balls 1017 in the conductive pillars 1010 and the copper pillars 1015 are fused into one structure and electrically connected to the pads on the first circuit structure layer 112 on the lower surface of the second core board 1021 .

The above manufacturing method is described by taking the packaging substrate 1 including the first substrate 101 and the second substrate 102 as an example. If the packaging substrate 1 also includes a third substrate, a fourth substrate, ..., the Nth substrate, the third substrate, the fourth substrate, ..., the manufacturing method of the Nth substrate can be compared with the first substrate 101 (or the second substrate 102 ) are made in the same way. The manufacturing method of the first dielectric layer 12 and the first dielectric interconnection structure 13 between two adjacent substrates can also be the same as the above-mentioned manufacturing method, and the connection method of the adjacent two substrates can also be the same as that of the first substrate 101 and the first substrate 101. The connection method of the second substrate 102 is the same, which will not be repeated here.

Take the packaging substrate 1 including a first substrate 101 , a second substrate 102 and a third substrate as an example. The manufacturing method of the above packaging substrate 1 also includes:

S400: forming a third substrate.

The method for manufacturing the third substrate is the same as the method for manufacturing the second substrate 102 or the first substrate 101 , and will not be repeated here.

S500: Laminate and electrically connect the third substrate and the second substrate.

(a) to (c) in FIG. 21 show some process steps of connecting the third substrate 103 to the second substrate 102 . This step is the same as the process steps between the second substrate 102 and the first substrate 101 , and will not be repeated here.

Taking the aforementioned packaging substrate 1 including the first substrate 101, the second substrate 102, and the third substrate 103 as an example, in some embodiments of the present application, the manufacturing method of the aforementioned packaging substrate 1 further includes the following steps:

S600: Form a top wiring layer on the upper surface of the third substrate.

Firstly, the second dielectric layer 141 as shown in FIG. 22( a ) is heated and pressed on the upper surface of the third substrate 103 .

Then, a second blind hole 1411 as shown in (b) of FIG. 22 is opened on the second dielectric layer 141 by means of mechanical drilling or laser drilling. And the copper material is filled in the second blind hole 1411 to form the second dielectric interconnection structure 142 as shown in (c) of FIG. 22 . The second dielectric interconnection structure 142 penetrates through the second dielectric layer 141 and is electrically connected to the first circuit structure layer 112 on the upper surface of the third substrate 103 .

Afterwards, a second circuit structure layer 143 as shown in (d) of FIG. 22 is formed on the upper surface of the second dielectric layer 141 , and the second circuit structure layer 143 is electrically connected to the second dielectric interconnection structure 142 . In some embodiments, a photoresist process may be used to form the second circuit structure layer 143 on the upper surface of the second dielectric layer 141 . Thus, the top wiring layer 14 is formed.

Based on the above, in some embodiments, after the second circuit structure layer 143 is formed, the upper surface of the top wiring layer 14 is printed with the first solder resist layer 16 as shown in (e) of FIG. 22 . The first solder resist layer 16 can form mechanical protection for the second circuit structure layer 143 .

S700: Form a bottom wiring layer on the lower surface of the first substrate.

The process of forming the bottom wiring layer 15 is similar to that of the top wiring layer 14 . Specifically, the following steps may be included:

Firstly, the third dielectric layer 151 shown in (a) of FIG. 23 is heated and pressed on the upper surface of the first substrate 101 .

Then, a third blind hole 1511 as shown in (b) of FIG. 23 is opened on the third dielectric layer 151 . And the copper material is filled in the third blind hole 1511 to form the third dielectric interconnection structure 152 as shown in (c) of FIG. 23 . The third dielectric interconnection structure 152 penetrates through the third dielectric layer 151 and is electrically connected to the first circuit structure layer 112 on the lower surface of the first substrate 101 .

After that, a third circuit structure layer 153 as shown in (d) of FIG. 23 is formed on the lower surface of the third dielectric layer 151 , and the third circuit structure layer 153 is electrically connected to the third dielectric interconnection structure 152 . Thus, the bottom wiring layer 15 is formed.

Based on the above, in some embodiments, after the third circuit structure layer 153 is formed, the upper surface of the bottom wiring layer 15 is printed with the second solder resist layer 17 as shown in (e) of FIG. 23 . Likewise, the second solder resist layer 17 can also form mechanical protection for the third circuit structure layer 153 .

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A packaging substrate, characterized in that, comprising:

A plurality of stacked substrates, each of which includes a core board, two layers of first circuit structure layers and a core board interconnection structure that runs through the core board, and the two layers of first circuit structure layers are respectively located on the core board The upper surface of the board and the lower surface of the core board, the interconnection structure of the core board is electrically connected to the two layers of the first circuit structure layer;

One or more first dielectric layers, the first dielectric layer is arranged between two adjacent substrates, the thermal expansion coefficient of the core board is smaller than the thermal expansion coefficient of the first dielectric layer;

One or more layers of the first dielectric interconnection structure penetrate the first dielectric layer and are electrically connected to the first circuit structure layer on the substrate on both sides of the first dielectric layer.
The packaging substrate according to claim 1, wherein the core board is a glass substrate, and the first dielectric layer is a non-conductive film NCF.
The packaging substrate according to claim 2, wherein the first dielectric layer comprises a matrix polymer and a filler located in the matrix polymer, the filler comprises silica particles, and the filler is dispersed in the matrix polymer.
The package substrate according to claim 3, characterized in that the average particle size of the silicon dioxide particles is less than 10 um.
The packaging substrate according to any one of claims 1-4, wherein the two outermost substrates among the plurality of stacked substrates are respectively a top substrate and a bottom substrate; the packaging substrate Also includes:

The top wiring layer includes a second dielectric layer, a second dielectric interconnection structure penetrating through the second dielectric layer, and a second circuit structure layer; the second dielectric layer and the top substrate are far away from the bottom One side surface of the substrate is connected, the second circuit structure layer is located on the second dielectric layer on the side surface away from the top substrate, and is connected to the top substrate through the second dielectric interconnection structure The first circuit structure layer in is electrically connected;

The bottom wiring layer includes a third dielectric layer, a third dielectric interconnection structure penetrating through the third dielectric layer, and a third circuit structure layer; the third dielectric layer and the bottom substrate are far away from the top One side surface of the substrate is connected, the third circuit structure layer is located on the side surface of the third dielectric layer away from the bottom substrate, and is connected to the bottom substrate through the third dielectric interconnection structure. The first circuit structure layer is electrically connected.
The package substrate according to claim 5, wherein the fluidity of the second dielectric layer and the fluidity of the third dielectric layer are both smaller than the fluidity of the first dielectric layer.
A chip packaging structure, characterized in that, comprising:

chip;

The package substrate according to any one of claims 1-6, wherein the chip is disposed on the package substrate and electrically connected to the package substrate.
An electronic device, characterized in that it includes a main board, and the chip packaging structure according to claim 7; The above chip package structure is electrically connected.
A method for manufacturing a packaging substrate, characterized in that it comprises:

forming a first substrate, including: providing a first core board, forming a first core board interconnection structure passing through the first core board, and forming a layer of first core board on the upper surface and the lower surface of the first core board respectively. A circuit structure layer; the first core board interconnection structure is electrically connected to the first circuit structure layer;

forming a second substrate, including: providing a second core board, forming a second core board interconnection structure penetrating through the second core board, and forming a layer of first A circuit structure layer; the second core board interconnection structure is electrically connected to the first circuit structure layer;

forming a first dielectric interconnection structure on the first circuit structure layer of the first substrate;

A first dielectric layer is formed on the upper surface of the first substrate having the first dielectric interconnection structure; the first dielectric interconnection structure penetrates the first dielectric layer;

disposing the second substrate on a side away from the first substrate on the first dielectric layer, and bonding the second substrate and the first substrate through the first dielectric layer; The dielectric interconnection structure is electrically connected to the first circuit structure layer of the first substrate and the first circuit structure layer of the second substrate on both sides of the first dielectric layer.
The method for manufacturing a package substrate according to claim 9, wherein the forming the first core board interconnection structure penetrating through the first core board specifically comprises:

opening a blind hole on the first core board;

forming a first core board interconnection structure in the blind hole;

The first core board is thinned to expose the bottom surface of the blind hole.
The method for manufacturing a packaging substrate according to claim 9 or 10, wherein the disposing the second substrate on the side of the first dielectric layer away from the first substrate comprises:

The second substrate is heated and pressed on the side of the first dielectric layer away from the first substrate.
The method for manufacturing a packaging substrate according to claim 11, wherein the forming a first dielectric interconnection structure on the first substrate comprises:

forming copper pillars on the first circuit structure layer on the first substrate, forming a solder layer on the copper pillars, and heating and pressing the second substrate on the first dielectric layer away from the On one side of the first substrate, the integrated structure of the copper pillar and the solder layer is electrically connected to the first circuit structure layer on the lower surface of the second chip; the integrated structure is the first dielectric interconnection structure .