TWI230461B - Method for manufacturing thin film transistor panel - Google Patents

Abstract

A method for manufacturing a thin film transistor panel is disclosed. First, a gate line with a gate electrode is formed on an insulating substrate. After a gate insulating layer is deposited over the gate line, a semiconductor layer of amorphous silicon is formed on the gate insulating layer. After the semiconductor layer is patterned, a photoresist pattern is formed such that areas on the substrate to be provided with source/drain electrodes are not covered by the photoresist pattern. Then, after depositing an ohmic contact layer and a second metal layer, the photoresist pattern is removed such that those portions of the ohmic contact layer and the conductive layer which are formed on the photoresist pattern are removed, leaving behind the desired ohmic contact pattern and the source/drain electrodes. Finally, a patterned passivation layer and pixel electrodes are provided to obtain the TFT panel of the present invention.

Description

1230461 V. Description of the invention (υ [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a thin film transistor (TFT) panel. [Previous technology] The space required for a display device Minimization, research on the development of various flat display devices (such as liquid crystal display devices, plasma display panels, and electroluminescent displays) has been ongoing. Especially in the field of liquid crystal display devices, liquid crystal technology is based on liquid crystal materials. The optical characteristics can be controlled by applying changes in the applied electric field. At present, the main method of manufacturing liquid crystal display devices and panels is based on amorphous silicon thin film transistor technology. Using these technologies, high-quality image display of basic size The device can be manufactured using a low temperature process. As known to those skilled in the art, a conventional liquid crystal display device generally includes a thin-film transistor panel, a color filter panel, and a liquid crystal layer sandwiched therebetween. Different from conventional formation in a semiconductor substrate Monolithic transistor, thin The transistor system is manufactured by stacking several thin films on a substrate. Therefore, the thin film transistor has a simpler and easier structure than a single transistor. Therefore, the thin film transistor has been widely used, for example, as a large-sized electronic device. (Such as liquid crystal displays). In addition, the simple device structure and manufacturing method of thin film transistors can produce a variety of applications at low cost, which helps their popularity in the market. In recent years, thin film transistors have been described above. Convenience features have been further improved

00687.ptd Page 6 1230461 V. Description of the Invention (2), and development. Referring to FIG. 1, a thin film transistor 10 includes a substrate 100, a semiconductor layer 102, a source 104, a drain 106, a gate insulating layer 108, and a gate electrode. 1 1 0. The source electrode 104 and the drain electrode 106 are disposed on the same side of the semiconductor layer 102 separately from each other, and are electrically connected to the semiconductor layer 102. The gate insulating layer 108 is disposed on the opposite side of the source layer 104 and the drain electrode 106 on the semiconductor layer 102. The gate electrode 1 10 is provided on the same side as the gate insulating layer 108 on the semiconductor layer 102, and is opposed to the semiconductor layer 102 via the gate insulating layer 108. When a proper gate voltage is applied, a conductive channel is formed in the gate-side surface area of the semiconductor layer 102. The semiconductor layer 1 02 is generally made of an undoped (i-t y p e) semiconductor material. In this example, it is necessary to sandwich an impurity impurity semiconductor layer 112 between the semiconductor layer 102 and the opposite source 104 / and the drain 106. The n + impurity-doped semiconductor layer 1 12 is used to form a semiconductor layer between the naturally doped semiconductor layer 102 and the source electrode 104 and the drain electrode 106 respectively.

Source and non-electrode contact area. The source is in good ohmic contact with the drain contact area B. -When the 11+ impurity impurity-doped semiconductor layer 丨 i 2 is provided as the source-drain contact area, the source 104 and the drain 106 will suffer depending on the observation. : Pure, doped semiconductor layers " 2 and short-circuit each other, resulting in channel leakage. The current loss of this channel). Due to the display and image applications ▲ The power needs: "" (off ㈣ off) current, so such devices have a large back etchlng process for selecting

1230461 V. Description of the invention (3) The n + impurity in the channel region 1 1 4 between the source 104 and the drain 106 is doped with a semiconductor layer. Generally, the n + impurity-doped semiconductor layer 1 12 is etched with a gas / sulfur hexafluoride (C12 / SF6) gas. However, due to environmental considerations in the world in recent years, this toxic and corrosive material (such as gas) will be eliminated in the next ten years. In addition, chlorine is difficult to control, highly toxic and expensive. In addition, the V impurity-doped semiconductor layer 11 2 is usually formed by a plasma chemical weather deposition method (C V D) at a temperature of 300 ° C. Therefore, although the impurity-doped amorphous silicon layer 1 1 2 is generally designed to have a thickness of 200 angstrom (angstrom), the impurity-doped impurity diffuses to a semiconductor layer located thereunder such that the impurity is doped. The total distribution thickness of the impurities may become 6 0-7 0 0 Angstroms. Therefore, in the back etching process, in addition to the n + impurity-doped semiconductor layer 1 1 2 in the channel region, a portion of the semiconductor layer 102 under the n + impurity-doped semiconductor layer 112 also needs to be removed to determine All n + impurity impurity semiconductors have been removed. This is actually very time consuming. In addition, the back-etching process may cause corrosion of the source 104 and the drain 106. The present invention therefore seeks to provide an improved method for manufacturing a thin film transistor panel to overcome or at least improve the aforementioned problems of the prior art. SUMMARY OF THE INVENTION The object of the present invention is to solve the above-mentioned problem of channel leakage of a thin film transistor panel by selectively forming an ohmic contact pattern between the undoped semiconductor layer and the source / drain. This reduces manufacturing costs and improves yield by eliminating time-consuming back etching processes.

00687.ptd Page 8 1230461 V. Description of the invention (4) The method for manufacturing a thin film transistor panel according to the present invention is to form a first conductive pattern including at least one gate line with a gate electrode on an insulating substrate (for example Transparent glass substrate). Next, a gate insulation layer is deposited on the gate line. An amorphous silicon semiconductor layer is formed on the gate insulating layer. After patterning the semiconductor layer, an n + impurity-doped semiconductor pattern and a source / drain are selectively formed by a photoresist peeling method (1 i f t-0 f f). In this process, a patterned photoresist layer is used so that the source / drain region on the substrate is not covered by the photoresist pattern. Then, after an ohmic contact layer and a second conductive layer are deposited, the photoresist pattern is removed in an ultrasonic bath with acetone. After doing so, the ohmic contact layer and the conductive layer on the photoresist pattern will be removed, leaving the desired ohmic contact pattern and the source / drain. Then, a protective layer (such as a Si N x layer) is formed on the entire surface of the structure to a predetermined thickness and the protective layer is patterned to expose a portion of the drain electrode. . After forming an indium-tin-oxide (ITO) layer as a transparent conductive layer on the entire surface of the structure having the patterned protective layer, the indium-tin-oxide layer is patterned. The pixel electrode is formed to obtain the thin film transistor panel of the present invention. By using the photoresist stripping process, the ohmic contact layer is selectively formed between the undoped semiconductor layer and the source / drain, so that no ohmic contact material is formed between the source / drain. In the channel area, the problem of channel leakage is thereby overcome. Therefore, the manufacturing method of the present invention can eliminate the conventional back etching process, thereby preventing the source / drain from being used by the conventional back etching process.

00687.ptd Page 9 1230461 V. Description of the invention (5) The etchant used is corroded. In addition, by eliminating a back etching process that generally requires the use of a toxic gas, the method for manufacturing a thin film transistor panel of the present invention greatly reduces the amount of the toxic gas that needs to be purchased, managed, and disposed of in a user's waste liquid. In order to make the above and other objects, features, and advantages of the present invention more apparent, the following description will be described in detail with reference to the accompanying drawings. [Embodiment] Although the present invention may be embodied in different forms of embodiments, those shown in the drawings and those described below are preferred embodiments of the present invention, and please understand that those disclosed herein are considered to be the present invention. Examples, and are not intended to limit the invention to the specific embodiments illustrated and / or described. Now, a method for manufacturing a thin film transistor panel according to an embodiment of the present invention will be described with reference to FIGS. 2 to 6 as follows. First, a first conductive layer is sputter-formed to a predetermined thickness on an insulating substrate 200 (such as a transparent glass substrate). As shown in FIG. 2, the first conductive layer is patterned by a first lithography process to form a first conductive pattern on the substrate 200. The first conductive pattern includes a gate electrode 2. The gate circuit of 02 is on the substrate 200. This patterning process is preferably completed with a photoresist and a wet or dry etchant selected according to the conductive layer used and the operator's preference. The first conductive layer may be a two-layer gate metallization layer formed on chromium and patterned by a reactive ion etching method. Next, as shown in FIG. 3, an oxide, silicon nitride, or silicon oxynitride layer is deposited on the entire surface of the substrate 2 0 0 having the gate line and the gate electrode 2 0 2

00687.ptd Page 10 1230461 V. Description of the invention (6) plane to form a gate insulation layer 204. Then, a semiconductor layer of pure amorphous silicon is disposed on the gate insulating layer 204. After that, the semiconductor layer is patterned by a second lithography process to form a patterned semiconductor layer 206 on the thin film transistor portion of the thin film transistor panel. Then, an n + impurity-doped semiconductor pattern and a source / drain are selectively formed by a photoresist peeling method (1 i f t-0 f f). In this process, a layer of photoresist is applied to the insulating substrate 200 having the patterned semiconductor layer 206 by, for example, spin coating, and a conventional lithography process is performed to obtain A photoresist pattern 2 1 0. After development, as shown in FIG. 4, the photoresist pattern 210 includes a first portion 2 1 0 a and a second portion 2 1 0 b facing a channel region. It should be noted that the area where the source / drain is disposed on the substrate is not covered by the photoresist pattern 210. In addition, pay attention to the negative slope (n e g a t i v e s 1 o p e) of the outline of the photoresist pattern after development. This negative slope facilitates subsequent deposition and photoresist exfoliation steps as it prevents material from being deposited on the photoresist's sidewalls (s i d e wa 1 1) and allows solvents to reach the photoresist pattern. Referring to FIG. 5, an ohmic contact layer 220 is formed on the entire surface of the insulating substrate 200 having the photoresist pattern 210, and a second conductive layer 230 is covered on the ohmic contact layer 220. Specifically, the ohmic contact layer may be an n + impurity-doped semiconductor layer, which covers the first part 2 1 Oa, the second part 2 1 Ob, and the photoresist pattern 2 1 of the photoresist pattern 2 1 0. 0 in the opening. The n + impurity-doped semiconductor layer may be formed by a sputtering process described below. First, the entire surface of the insulating substrate 2 0 0 having the photoresist pattern is cleaned, and then placed in a sputtering chamber, which is capable of producing

00687.ptd Page 11 1230461 V. Description of the invention (7) Produces a relatively high plasma density and contains a plate to support the target of the deposited material. Generally, a vacuum pumping system is connected to the sputtering chamber to evacuate the chamber and maintain a desired pressure in the chamber. The target is connected to a high negative voltage and placed in a low-pressure inert gas. Under the influence of the high potential difference, the gas ion system is accelerated toward the surface of the cathode, wherein the momentum of the ion is transferred to the atoms on the surface of the target, and the atoms on the surface of the cathode are ejected and brought into contact with and adhered to The entire surface of the insulating substrate 200. The inert gas commonly used in this sputtering method includes helium, neon, argon, krypton, xenon, nitrogen, and the like. An exemplary sputtering process for the n + impurity-doped semiconductor layer will be described in detail below. The n + impurity-doped semiconductor layer can be formed by sputtering an amorphous silicon target in a vacuum chamber, which uses a phosphine gas or hydrogen and filled hydrogen as a reaction gas. The sputtering process of the impurity-doped semiconductor layer involves sputtering a material from an n + impurity-doped semiconductor material onto the undoped semiconductor layer to form the impurity-doped semiconductor layer. In addition, the n + impurity-doped semiconductor layer may be It is formed by sputtering a material from an n + impurity-doped target onto the insulating substrate having a photoresist pattern. The n + impurity-doped semiconductor layer may also be formed by sputtering a material from an n + impurity-doped target, freeing the sputtered material, and attracting the sputtered material to the insulating substrate having a photoresist pattern. In this embodiment, a process gas such as inert argon or helium or a reaction gas such as argon and phosphine can also be supplied into the sputtering chamber. The n + impurity-doped target can be made of amorphous silicon and pentavalent impurities such as antimony (Sb), arsenic (As), or phosphorus.

00687.ptd Page 12 1230461 V. Description of Invention (8) (P). The second conductive layer 230 may include a relatively thin layer of chromium, tantalum, or other suitable metal that can make good ohmic contact with n + impurity-doped amorphous silicon, and a relatively thick layer of molybdenum, aluminum, or tungsten. . It should be noted that the second conductive layer and the n + impurity-doped semiconductor layer can be continuously sputtered in the sputtering chamber without breaking the vacuum. After that, when the insulating substrate is immersed in an appropriate solvent and placed in an ultrasonic bath, the ohmic contact layer and the second conductive layer are formed on the first part 2 1 0 a and the second part of the photoresist pattern. The part on 2 1 0 b is removed (lifted-off), leaving the desired ohmic contact pattern 220 a and the source / drain electrode 2 3 0 a separated by the channel region (see Figure 6) . In detail, after the ohmic contact layer or the second conductive layer is formed, it may be subjected to a thermal tempering process or a hydrogen plasma tempering process. Next, a protective layer (not shown in the figure, such as a silicon nitride layer) is formed on the entire surface of the structure to a predetermined thickness, and the protective layer is patterned by a lithography process and the drain is exposed. Part of the pole. After an indium tin oxide layer (I TO) (not shown) as a transparent conductive layer is formed on the entire surface of the structure with the protective layer pattern, the IT0 layer is patterned by another lithography process. Thus, the thin film transistor panel of the present invention is obtained. Generally speaking, the thin film transistor shown is just one of many thin film transistors formed on the same substrate at the same time. In the thin-film transistor panel manufacturing method described in FIGS. 2-6, the ohmic contact layer is selectively formed between the undoped semiconductor layer and the source / drain so that no ohmic contact material is formed on the source. /〉 And the communication between poles

00687.ptd Page 13 1230461 V. Description of the invention (9) In the track area, the problem of channel leakage is overcome. Therefore, the manufacturing method of the present invention can eliminate the conventional back etching process, thereby preventing the source / drain from being corroded by the etchant used in the conventional back etching process. In addition, by eliminating the toxic gas required for a general back-etching process, the thin-film transistor panel manufacturing method of the present invention greatly reduces the amount of the toxic gas that needs to be purchased, managed, and disposed of in the user's waste liquid. The user can therefore expect substantial savings in operating costs, as the toxic gas, which is no longer needed, has been removed. Next, a method of manufacturing a thin-film transistor panel according to another embodiment of the present invention will be described with reference to FIGS. 7-10. Referring to FIG. 7, after the gate circuit having the gate electrode 202 and the gate insulating layer 204 are formed on the substrate 200, an i-type semiconductor layer such as a pure amorphous is formed. A silicon semiconductor layer 3 1 0 is formed on the gate insulating layer 204 and an ohmic contact layer such as an impurity-doped semiconductor layer 3 2 0 is formed on the pure amorphous silicon semiconductor layer 3 1 0 by a sputtering process. It is worth noting that the impurity-doped semiconductor layer 3 2 0 is formed by sputtering an amorphous silicon target in a vacuum chamber, which uses phosphine gas or nitrogen and filled nitrogen. Is a reactive gas. In addition, the n + impurity-doped semiconductor layer 3 2 0 can also be formed by sputtering a material from an n + impurity-doped target onto the pure amorphous silicon semiconductor layer 3 1 0. In this embodiment, a process gas such as inert argon or helium or a reaction gas such as hydrogen and phosphine can also be supplied into the sputtering chamber. Referring to FIG. 8, the pure amorphous silicon semiconductor layer 3 1 0 and the n + impurity-doped semiconductor layer 3 2 0 are patterned through a second lithography process to form a pure amorphous silicon semiconductor pattern 3 1 0 a. And n + impurity-doped semiconductor patterns

00687.ptd Page 14 1230461 V. Description of the invention 3 2 0 a on the thin film transistor portion of the thin film transistor panel. After a metal layer having a predetermined thickness is formed on the entire surface of the insulating layer 204 and the semiconductor patterns 310a and 320a by, for example, sputtering, referring to FIG. 9, the aforementioned metal layer is formed by a third lithography process. Patterned to form a conductive pattern 3 1 4, the conductive pattern 3 1 4 includes a data line (not shown in the figure), a source 3 1 6 and a drain 3 1 8, wherein the source 3 1 6 and The drain electrodes 3 1 8 are separated by a channel region 3 2 1. The UI + impurity-doped semiconductor pattern 3 2 0 a has a portion located in the channel region 3 2 1 and is exposed from the conductive pattern 314. Next, referring to FIG. 10, the n + impurity is doped with the semiconductor pattern 3 2 0 a. The exposed portion 3 2 2 of the channel region 3 2 1 is treated with an insulating step to make the exposed portion 3 2 2 conductive. Significant reduction in sex. The insulating step of the present invention can be achieved by an oxidation process, a nitridation process, or a P + impurity doping process. The oxidation process can be achieved by ozone (03) treatment, ultraviolet radiation (UV radiation), atmospheric plasma (atmosphere plasma) or oxygen ashing (02 ashing). Specifically, the oxidation process can be achieved by exposing the impurity to the exposed portion 3 2 0 of the semiconductor pattern 3 2 0 a by exposure to ozone (03) or high-intensity ultraviolet light generated by an ultraviolet light bulb. In another embodiment of the present invention, the oxidation process can be achieved by exposing the n + impurity-doped semiconductor pattern 320a with the exposed portions 322 of the semiconductor pattern 320a in a reaction chamber (oxygen plasma). In yet another embodiment of the present invention, the oxidation process can be achieved by exposing the n + impurity-doped semiconductor pattern 320a with the exposed portion 3 2 2 in an ashing unit to an oxygen plasma. When the insulation of the present invention

00687.ptd Page 15 1230461 V. Description of the invention (11) When the above-mentioned oxidation process is completed, the photoresist left over from the third lithography process can be removed in the same oxidation process, which can additionally Eliminate the steps of removing photoresist in conventional techniques. The nitriding process can be achieved by exposing the n + impurity to the exposed portion 322 of the semiconductor pattern 3 2 0 a under a gas plasma using ammonia gas. The p + impurity impurity doping process can be achieved by implanting a trivalent impurity (such as boron, aluminum, or gallium) into the n + impurity impurity doped exposed portion 3 2 2 of the semiconductor pattern 3 2 0 a. Next, a protective layer (not shown in the figure, such as a nitride layer) is formed in a predetermined thickness on the entire surface of the structure. The protective layer is patterned by a fourth lithography process and a part of the drain electrode 3 1 8 is exposed. After that, an indium tin oxide layer (ITO) as a transparent conductive layer is formed on the entire surface of the structure with the protective layer, and the IT 0 layer is patterned by a fifth lithography process to obtain the invention. Thin film transistor panel. In the method for manufacturing a thin-film transistor panel according to the present invention, since the n + impurity-doped semiconductor layer is formed by a sputtering process, it does not diffuse to the amorphous silicon semiconductor layer below it, so the actual impurity is The total distribution thickness can be accurately controlled within a predetermined value (for example, 200 angstrom). Therefore, the thin-film transistor panel manufactured according to the present invention can be designed with an amorphous silicon semiconductor layer much thinner than a user. In addition, compared with the impurity-doped semiconductor layer obtained by the conventional CVD process, the impurity-doped semiconductor layer formed by the sputtering process of the present invention has a much lower actual total distribution thickness of the impurities, so the above-mentioned insulation step It is easier to reduce the conductivity of the exposed portion of the impurity-doped layer, and make the source and

00687.ptd Page 16 1230461 V. Description of the invention (12) The electrons of the impurity-doped layer between the drain electrodes are not easy to move, thereby overcoming or at least improving the leakage problem of the channel. Although the present invention has been disclosed by the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

00687 · ptd Page 17 1230461 Brief description of the drawings [Simplified description of the drawings] Figure 1: is a cross-sectional view of a conventional thin film transistor; Figures 2 to 6: according to an embodiment of the present invention The diagram illustrates the main steps of manufacturing a thin-film transistor panel; and FIG. 7 to FIG. 10 are cross-sectional diagrams illustrating the main steps of manufacturing a thin-film transistor panel according to another embodiment of the present invention. Drawing date; 3: 10 thin film transistor 100 substrate 102 104 source 106 108 gate insulating layer 110 112 n + impurity-doped semiconductor} 罾 114 channel region 200 insulating substrate 202 204 gate insulating layer 206 210 photoresist pattern 210a 210b The second part 220 ohmic contact layer 2 2 a a 230 second conductive layer 2 3 0 a 310 pure amorphous silicon semiconductor layer 310a pure amorphous silicon semiconductor pattern 314 conductive pattern 31 6 source only 318 drain ohmic contact pattern source / drain The electrode layer of the electrode body is partially turned off, and the transistor is half off.

00687.ptd Page 18 1230461 Schematic description Exposed part 3 2 0 n + impurity-doped semiconductor layer 3 2 0 a n + impurity-doped semiconductor pattern 32 1 channel region 322

00687.ptd Page 19

Claims (1)

1230461 6. Scope of patent application 1. A method for manufacturing a thin film transistor panel, comprising the following steps: forming a gate circuit on an insulating substrate, the gate circuit having a gate electrode connected thereto; forming a gate insulating layer on the gate On the circuit; forming a semiconductor layer on the gate insulating layer; patterning the semiconductor layer; forming a photoresist pattern on the insulating substrate having the patterned semiconductor layer, the photoresist pattern including a first part Opposite a channel region, where the source / inverter region on the substrate is not covered by the photoresist pattern; an ohmic contact layer is formed on the substrate with the photoresist pattern The entire surface of the insulating substrate; forming a conductive layer on the ohmic contact layer; and removing the photoresist pattern so that the ohmic contact layer and the conductive layer on the photoresist pattern are also removed, leaving the desired An ohmic contact pattern and the source / drain, wherein the drain and source are separated by the channel region. 2. The method for manufacturing a thin-film transistor panel according to item 1 of the patent application scope, wherein the ohmic contact layer is an impurity-doped semiconductor layer formed by a sputtering process. 3. The method for manufacturing a thin-film transistor panel according to item 2 of the patent application scope, wherein the sputtering process is a process in which a material is sputtered from an impurity-doped target to the insulating substrate with a photoresist pattern to form the impurity-doped Semiconductor layer. 00687.ptd Page 20 1230461 VI. Patent application scope 4. The method of manufacturing a thin film transistor panel according to item 3 of the patent application scope, wherein the impurity-doped target material is an impurity containing amorphous silicon and a pentavalent impurity Doped with dry material. 5. The method for manufacturing a thin film transistor panel according to item 3 of the patent application scope, wherein the sputtering process is performed in a vacuum chamber using a phosphine gas as a reaction gas. 6. The method for manufacturing a thin-film transistor panel according to item 3 of the patent application scope, wherein the sputtering process is performed in a vacuum chamber using hydrogen gas and phosphine gas as a reaction gas. 7. The method for manufacturing a thin film transistor panel according to item 2 of the scope of the patent application, wherein the impurity-doped semiconductor layer is formed by sputtering a target of amorphous silicon in a vacuum chamber using a phosphine gas as a reaction gas. Material. 8. The method for manufacturing a thin-film transistor panel according to item 7 of the scope of patent application, wherein the sputtering process is performed in a vacuum chamber using hydrogen gas and phosphine gas as a reaction gas. 9. The method for manufacturing a thin film transistor panel according to item 1 of the scope of the patent application, wherein the photoresist pattern removing step is performed in an ultrasonic bath (u 1 t r s ο n i c bath). 00687.ptd Page 21 1230461 VI. Patent application scope 10, The method of manufacturing a thin film transistor panel according to item 1 of the patent application scope, wherein the ohmic contact layer and the conductive layer are continuously sputtered without breaking the vacuum . 11. The method for manufacturing a thin-film transistor panel according to item 1 of the scope of patent application, wherein the semiconductor layer is an amorphous silicon layer. 1 2. The method for manufacturing a thin film transistor panel according to item 1 of the scope of patent application, further comprising a hydrogen plasma annealing process performed after the step of forming the ohmic contact layer. 1 3. The method for manufacturing a thin film transistor panel according to item 1 of the scope of patent application, further comprising a hydrogen plasma tempering process performed in the conductive layer forming step 1 4. The method for manufacturing a thin film transistor according to item 1 of the scope of patent application The crystal panel method further includes a thermal annealing process performed after the ohmic contact layer forming step. 15. The method for manufacturing a thin film transistor panel according to item 1 of the scope of patent application, further comprising a thermal tempering process performed after the conductive layer forming step. 16. A method for manufacturing a thin film transistor panel, comprising the following steps: 00687.ptd Page 22 1230461 6. The scope of the patent application forms a gate circuit on an insulating substrate, the gate circuit having a gate electrode connected to it; forming a gate insulating layer on the gate circuit; forming an undoped (i -type) a semiconductor layer on the insulating layer; forming an impurity-doped semiconductor layer on the undoped semiconductor layer by a sputtering process; patterning the undoped semiconductor layer and the impurity-doped semiconductor layer; forming a A conductive pattern layer is disposed on the patterned undoped semiconductor layer and the impurity-doped semiconductor layer. The conductive pattern layer has a source electrode, a drain electrode, and a channel region disposed between the source electrode and the drain electrode. The impurity-doped layer has a portion in the channel region and is exposed from the conductive pattern layer; and the exposed portion of the impurity-doped layer is insulated. 17. The method for manufacturing a thin film transistor panel according to item 16 of the scope of patent application, wherein the sputtering process for forming the impurity-doped semiconductor layer is to sputter the material from an impurity-doped target to the undoped semiconductor. Layer to form the impurity-doped semiconductor layer. 18. The method for manufacturing a thin-film transistor panel according to item 17 of the scope of patent application, wherein the impurity-doped target material is an n + impurity-doped material including amorphous silicon and a pentavalent impurity. 19. Method of manufacturing thin film transistor panel according to item 17 of the scope of patent application 00687.ptd Page 23 1230461 6. Patent application method, wherein the sputtering process is performed in a vacuum chamber using phosphine gas as a reaction gas. 20. The method for manufacturing a thin film transistor panel according to item 17 of the scope of patent application, wherein the sputtering process is performed in a vacuum chamber using hydrogen and a phosphine gas as a reaction gas. The Fang Youzhi borrowed the thin layer construction system of the surface coating system of electroplated electrosputter film. The half of the miscellaneous 16 mixed with the pure material is not suitable for this specialization. Please go to 1 according to its 2 and / The air in the room is really the body gas nitrogen. For the formation of phosphorus, the crystal opposite of the target is used for the gasification of the surface gas, and the crystal and electricity are produced by the thin gas to generate hydrogen. 2 ^ The system is encircled in the normal system, and the Zhongli plating room is empty. Please refer to the true application. The 22 method should be 3 to 4 to 5 夬 2 ,, / 2 ,, / 2 ,, / Fangzhi Plate surface. Japan's aa layer of electric broken film crystal thin non-manufactured system layer 16 body first half of the guide ring Λ · 巳 隹 利 mixed with non-Yuhailingkou ancient mouth in the plate surface body crystal ο electroforming The oxygen term of the thin-film manufacturing system is not limited to the first step of the system. It is absolutely necessary to ask the middle to the board surface V body U crystal electrical film to shoot the purple item outside the light system. The first one is implemented by the 2nd system of the system, and it is requested to apply for the application in accordance with 00687.ptd, page 24, 1230461 6. Application for patent treatment (radiation treatment). 2 6. The method of manufacturing a thin film transistor panel according to item 24 of the scope of patent application, wherein the oxidation process is achieved by an atmospheric plasma treatment ° 2 7. According to the scope of patent application of scope 2 4 In the method of manufacturing a thin film transistor panel, the oxidation process is achieved by an oxygen ashing treatment. 28. The method for manufacturing a thin-film transistor panel according to item 24 of the scope of the patent application, wherein the oxidation process is achieved by an ozone treatment (〇 3 t r e a t m e n t). 29. The method for manufacturing a thin film transistor panel according to item 16 of the scope of patent application, wherein the insulating step is achieved by a nitriding process. 30. The method for manufacturing a thin film transistor panel according to item 16 of the patent application scope, wherein the impurity-doped layer is an n + amorphous silicon layer and the insulating step is achieved by a p + impurity-doped process. 31. A liquid crystal display device comprising a thin film transistor panel made of the following steps: forming a gate circuit on an insulating substrate, the gate circuit having a connection to the gate circuit; 00687.ptd Page 25 1230461 6. The gate electrode in the scope of patent application, forming a gate insulation layer on the line; forming a semiconductor layer on the gate insulation layer; patterning the semiconductor layer; β #insulation forming a photoresist pattern having the already patterned On the substrate of the semiconductor layer, the photoresist pattern includes a first portion facing a channel ^. (C ha η ne 1 regi ο η), where a source /; and electrodes and regions are not covered by the photoresist pattern on the substrate; / forming an ohmic contact layer Forming a conductive layer on the ohmic contact layer on the entire surface of the insulating substrate of the photoresist pattern; and removing the photoresist pattern so that the ohmic contact layer and the special electrical layer on the photoresist pattern are also removed, and Leave the desired ohmic contact pattern and the source / drain, where the drain and source are separated by the channel area; ^ U: ΐ Liquid crystal display device of item 31 of the patent scope, where the ohmic contact layer is Impurity-doped semiconductor layer formed by a layer of riding shoes / straight, layer-by / base plating. 3 3. According to the process of item 32 of the scope of patent application, the material is doped with a target by impurities. In the display device, the sputtered insulating substrate is doped to form the impurity and is injected onto the layer with a photoresist pattern. 34. The doping target material according to item 33 of the patent application scope includes amorphous silicon. And I9 ", staff display device, which should not Η + Impurities of Pentavalent Impurities 1230461 6. Scope of patent application Doped dry material. 35. The liquid crystal display device according to item 33 of the scope of patent application, wherein the sputtering process is performed in a vacuum chamber using a phosphine gas as a reaction gas. 36. The liquid crystal display device according to item 33 of the scope of patent application, wherein the sputtering process is performed in a vacuum chamber using hydrogen and a phosphine gas as reaction gases. 37. The liquid crystal display device according to item 32 of the scope of patent application, wherein the impurity-doped semiconductor layer is formed by sputtering an amorphous silicon target in a vacuum chamber using phosphine gas as a reaction gas. form. 38. The liquid crystal display device according to item 37 of the scope of patent application, wherein the sputtering process is performed in a vacuum chamber using hydrogen and a phosphine gas as a reaction gas. 39. The liquid crystal display device according to item 31 of the scope of patent application, wherein the photoresist pattern removing step is performed in an ultrasonic bath. 40. The liquid crystal display device according to item 31 of the scope of patent application, wherein the ohmic contact layer and the conductive layer are continuously sputtered without breaking vacuum. 00687.ptd Page 27 1230461 VI. Patent application scope 41. The liquid crystal display device according to item 31 of the patent application scope, wherein the semiconductor layer is an amorphous silicon layer. 4 2. The liquid crystal display device according to item 31 of the patent application scope further includes a hydrogen plasma annealing process performed after the ohmic contact layer forming step. 4 3. The liquid crystal display device according to item 31 of the patent application scope further includes a hydrogen plasma tempering process performed after the conductive layer forming step. 4. The liquid crystal display device according to item 31 of the patent application scope further comprises a thermal annealing process performed after the ohmic contact layer forming step. 4 5. The liquid crystal display device according to item 31 of the patent application scope further includes a thermal tempering process performed after the conductive layer forming step. 46. A liquid crystal display device comprising a thin film transistor panel made of the following steps: forming a gate circuit on an insulating substrate, the gate circuit having a gate electrode connected thereto; and forming a gate insulating layer on the gate circuit Forming an i-type semiconductor layer on the gate insulating layer; forming an impurity-doped semiconductor layer on the undoped semiconductor by a sputtering process 00687.ptd Page 28 1230461 6. Apply for patents on the bulk layer; pattern the undoped semiconductor layer and the impurity-doped semiconductor layer; form a conductive pattern layer on the patterned undoped semiconductor layer and impurity-doped On the hetero-semiconductor layer, the conductive pattern layer has a source electrode, a drain electrode, and a channel region disposed between the source electrode and the drain electrode, wherein the impurity-doped layer has a portion located in the channel region and is conductive from the conductive region. The pattern layer is exposed; and the exposed portion of the impurity-doped layer is insulated. 47. The liquid crystal display device according to item 46 of the patent application scope, wherein the sputtering process for forming the impurity-doped semiconductor layer is to sputter the material from an impurity-doped target onto the undoped semiconductor layer to form The impurity is doped in the semiconductor layer. 48. The liquid crystal display device according to item 47 of the scope of patent application, wherein the impurity-doped target material is an n + impurity-doped target material including amorphous silicon and a pentavalent impurity. 49. The liquid crystal display device according to item 47 of the patent application scope, wherein the sputtering process is performed in a vacuum chamber using a phosphine gas as a reaction gas. 50. The liquid crystal display device according to item 47 of the scope of patent application, wherein the sputtering process is performed in a vacuum chamber using hydrogen and an argon phosphide gas as a reaction gas. 00687.ptd Page 29 1230461 VI. Patent application range 51, liquid crystal display device according to item 46 of the patent application range, wherein the plating process for forming the impurity-doped semiconductor layer is performed by using a hydrogen-filled gas. This is achieved by sputtering a target of amorphous silicon in a vacuum chamber of a reactive gas. 52. The liquid crystal display device according to item 51 of the patent application scope, wherein the sputtering process is performed in a vacuum chamber using hydrogen and an argon phosphide gas as a reaction gas. 53. The liquid crystal display device according to item 46 of the patent application scope, wherein the undoped semiconductor layer is an amorphous layer. 5. The liquid crystal display device according to item 46 of the scope of patent application, wherein the insulating step is achieved by an oxidation process. 55. The liquid crystal display device according to item 54 of the scope of patent application, wherein the oxidation process is achieved by a UV radiation treatment. 56. The liquid crystal display device according to item 54 of the patent application scope, wherein the oxidation process is achieved by an atmospheric plasma treatment. 5 7. The liquid crystal display device according to item 54 of the scope of patent application, wherein the oxidation 00687.ptd Page 30 1230461 6. Scope of patent application The manufacturing process is achieved by an oxygen ashing treatment (02 ashing treatment). 58. The liquid crystal display device according to item 54 of the scope of patent application, wherein the oxidation process is achieved by an ozone treatment (0 3 treatment). 59. The liquid crystal display device according to item 46 of the scope of patent application, wherein the insulating step is achieved by a nitriding process. 60. The liquid crystal display device according to item 46 of the patent application scope, wherein the impurity-doped layer is an n + amorphous silicon layer and the insulation step is achieved by an impurity-doped process. 00687.ptd Page 31