TWI229392B - Semiconductor molding structure and method thereof - Google Patents

Abstract

A semiconductor package and method thereof are proposed, wherein a chip carrier including a plurality of semiconductor chips arrayed thereon and an encapsulant formed thereon for covering the semiconductor chips is provided. A plurality of package units is respectively defined by the encapsulant covering the semiconductor chips, and at least a pair of adjacent package units is connected by at least a connected portion made by the encapsulant, thereby preventing the semiconductor molding structure from warpage and deformation.

Description

1229392 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor die pressing method and a die-finger finger which can reduce half of warping and deformation of a semiconductor device =: structure, method and die pressing structure. ¥ Phantom Pressing [Previous Technology] A ball grid array semiconductor packaging technology is an advanced technology. As shown in Figure 5, the substrate 5 丨 is used as a semiconductor and is mounted on the top surface of the semiconductor. A conductive trace is laid on both the lower surface and the wafer 5 2, which is located at 5 2, and the conductive trace on the upper surface is electrically connected with a bonding wire 5 3. Therefore, a solder ball 5 6 implanted on the lower surface is provided. The telecommunication signal is transmitted to 5 4 'to hunt for one formed on its upper surface and covering the chip 52 and the bonding wire,' and 55 to protect the package. 3 package colloid This ball grid array package 5 〇 In order to take into account the production requirements of the manufacturing method, generally in batch mode (Batch Type) and the amount of substrate strip (Substrate Strip) staggered $ 表 义 界线 Predefining a plurality of matrix arrayed packages called h P rn. Yi Zaowu, Q Die Bond), welding (Wire Bond) and colloidal seal stop you -Π Xu · Lie Yi Xun Steps •, and further, singuing (singu 1 ati ο η) to remove the connection between adjacent packaging units to make a single semiconductor package 50 shown in Figure 5. Conventionally, in order to improve process efficiency and reduce the time and cost of colloidal packaging, it is often the same as the thin ball grid array (+ Thin Fine BaU Grid Array, TFBGA) disclosed in US Patent No. 5,7 7 6, 7 9 8 As shown in FIG. 6, a method for nuclear pressure of a semiconductor package is formed by forming a plurality of array-type predetermined packaging areas on the substrate 100 (such as component symbols 1 0 1, 1 0 2, 1 0 3, 1 〇4 , 1229392 V. Description of the invention (2) 105, 106, etc.), each of the packaging areas is separated from each other by a gap around the circumference. Among them, the substrate 100 is packaged in the form of a substrate strip, and a dam structure is formed around the substrate 100 so that the predetermined packaging areas are located in the dam structure. Within 1 〇8. Then, an encapsulation gel body 109 such as resin (Epoxy) is used to cover the array-type encapsulation region 'in the dam structure 108. After molding, the encapsulation regions on the substrate 100 are encapsulated. Among them, the dam structure 108 surrounds the entire encapsulation area, so that the encapsulation gel 10 covering it can form a flat surface. Finally, after the hardening process (Post molding cUring, PMC) is performed to complete the resin bonding, the packaging gel 109 and the substrate 100 below it are cut at the gap i 〇7 of the sealing area of the obtained package to divide each of the two packages. By hitting the area, an individual semiconductor package as shown in FIG. 5 is obtained. However, the predetermined encapsulation area of this conventional method is arrayed. The encapsulation gel 10, which is encapsulated in the entire encapsulation area, has a very large area, generally 42.5 mm X 42.5 mm. ,

Different thermal expansion amounts due to the mismatch of the thermal expansion coefficient (CTE M ismatch) of the packaging colloid 1 09 and the substrate 100, and the thin ball tree array is added.] The thickness of the substrate 100 is thinner, and the packaging colloid 1 0 The contact area between 9 and the substrate i 00 is extremely large, which causes the package to produce a warpage phenomenon as shown in FIG. 7, forming two major problems in process yield and structural strength. Poor flatness makes it difficult to cut or damage the cutting tool. ,. Therefore, as disclosed in U.S. Patent No. 5, 89 7, 334, a plurality of packaging lines 6 3 are constructed on the substrate strip 6 1 shown in FIG. 8.

17437 Joint Test. Ptd

1229392 V. Description of the invention (3) ^ _ 一一 ^ — (Package Line) Substrate remote technology divided and adjacent to and connected to each adjacent substrate unit 62, square substrate unit 62, and a wafer connected to unit 62 65, and the base unit 62 is electrically connected with the bonding wire 66, so that a corresponding mold (not shown) can be used for the molding process. The mold has a plurality of mold cavities corresponding to the position of the substrate unit 62, so as to 9 As shown in the figure, each substrate unit 62 is molded into an individual packaging unit 67, and the packaging colloids 68 of adjacent packaging units 67 are separately separated, which can greatly reduce the contact area between the sealing f colloid 68 and the substrate strip 61. The thermal stress is released by the sealant colloid 6 8 space 6 9 between the adjacent packaging units ^, so that the warping phenomenon caused by the mismatch of the thermal expansion coefficients does not occur as shown in FIG. 7. However, this molding method and molding structure still have other structural problems. 'This is because after the foregoing molding process, the user often needs to hold one end of the substrate strip 61 to move its position for subsequent transportation or fixtures. The step of transfer 'saves the completion of subsequent ball-planting, reliability testing, cutting or transportation procedures, etc. At this time, since the packaging units 6 7 on the substrate strip 61 are separated from each other', it will be as shown in Figure 10 ( The user is held at the right end of the substrate strip 6), so that the substrate strip 61 is subject to the gravity of the left-end packaging unit 67 like a cant i lever to cause a bending (Bencji ng) deformation phenomenon, which causes the The long-term adverse effects of the substrate strip 61 will cause cracks or peeling of the packaging gel 68 and the chip 65 on each packaging unit 67, which will greatly affect the yield of the overall structure. Therefore, how to develop a semiconductor molding method and a molding structure to solve the two conventional problems at the same time, to avoid structural warping due to mismatched thermal expansion coefficients, and to avoid structural deformation due to gravity.

17437 联 测 .ptd Page 7 1229392 V. Description of the Invention (4) An urgent problem in this field. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor molding method and a molding structure which can prevent warping due to mismatch of thermal expansion coefficients. Another object of the present invention is to provide a semiconductor molding method and a molding structure which can avoid deformation due to gravity. Still another object of the present invention is to provide a semiconductor molding method and a molding structure capable of improving the structural strength and yield. In order to achieve the above and other objectives, the semiconductor molding method of the present invention includes the following steps: preparing a wafer carrier carrying a plurality of semiconductor wafers, and electrically connecting the semiconductor wafer and the wafer carrier, and performing a molding step, The chip carrier is filled with a packaging colloid, and a plurality of packaging units respectively covering the semiconductor wafer are formed, and at least one adjacent two packaging units are formed with at least one connection portion composed of the packaging colloid. And performing a demolding step to form a semiconductor mold structure. The semiconductor molded structure made by the present invention includes: a wafer carrier; a plurality of semiconductor wafers connected to the wafer carrier and electrically connected to the wafer carrier; and a packaging gel filled on the wafer carrier. To form a plurality of packaging units respectively covering the semiconductor wafer; and at least one connection portion is composed of the packaging gel and is formed between at least one set of two adjacent packaging units. The aforementioned connecting portion is formed by filling the encapsulating gel into a preset connecting channel in the mold of the molding step, and the shape of the connecting portion is a long strip.

17437 联 测 .ptd Page 8 1229392 V. Description of the invention (5), and its height is lower than the package list / > Between the two adjacent package units are formed; ::: 3; Tongri Temple, The connection part is not formed at the interval of each assembly unit, and the seals between the groups are as follows: All adjacent packaging units are: ±: The design can also be changed. Therefore, by the aforementioned connection; ::; Edge connection. < Machic redemption, that is, a suitable semiconductor die pressing method proposed by the wafer carrier and its ^ 1 'are maintained between the eight packaging units, which can make the effect of the present invention neither cause the material to swell. ^. The structure of X is stable and the overall structure is changed from the tongue a. The warping coefficients do not match, and the structure is not caused by the gravity effect. The structural strength and process yield are resolved. question. The Dilemma Encountered by I & Knowing Technology [Implementation] The following are specific implementations. Those skilled in the art can understand the other advantages of the invention and ... from the perspective of different perspectives and applications. The details in Fuji are also modified and changed. The first A and 1 B drawings are performed without departing from the spirit of the present invention. The first embodiment shows a preferred embodiment of the semi-structure of the present invention. # 弟 1A shown in the figure, provide—wafer bearing :: 20 αHAI said that the chip carrier 20 can be a predetermined cutting line such as a thin ball, etc. # 满 述 加 口 々, 心 顶 疋 Cut line, so that The loading area and the final cut of the qP array of semiconductor wafers 21, where the semiconductor wafers m are welded with bonding wires 22 and 1229392. 5. Description of the invention (6) 2: Electrical connection of the conductive traces of the bull " To carry out this article, hold 24 ΐ ΐ Ϊ ，;, as shown in the figure—special upper and lower molds 23, carrier 20, so that each wafer 21 and its solder joints = upper tool 23 corresponding In the mold cavity 25, at the same time, two adjacent mold cavities 25 are matched =: = t Two mold molds 25 in the same group are formed to have two heights higher than the mold cavity 25 ^, r 俾, so that the encapsulant 26 is self-injected π (not (Illustrated) After being injected into the yoke 25, the encapsulant 26 can also be connected to the two connecting channels 30. The brother Yu Xiangxiang two branches and eighty-five indirectly wrote "When all the mold cavities 25 and the connecting channel 30 are filled with the colloid 26, the removal of the cattle is completed. The 30-sentence sentence has filled the sealed semiconductor device two-group , And the two packaging units of the same group 4! Door Qiao, f Yi Zaofan 4 1 series is configured to be connected to the upper mold 3, the connecting portion 31 is corresponding to the aforementioned two adjacent ... "ΐ:?; = 体 26, In order to cover one of the connecting portions 31... Not shown in the figure, the shape can be more clearly seen, which is connected by the connecting channel of the cavity 25. It is formed into two long strips and The gel joints 徨, which are spaced apart from each other by a distance, are connected to the central positions of the packaging gels 26 of two adjacent packaging units 41, and the contact area between the chip carrier 20 and all the packaging gels 26 is not ^ 7. By using the connecting portion 3, the distance between the two adjacent packaging units 4 is increased, so that the packaging unit 41 at both ends of the wafer carrier 20 will not be bent and deformed by the wafer carrier 20 due to its weight. 'With the aforementioned connection channel 3 〇 disclosed in the upper mold 2 3

17437 联 测 .ptd Page 10 1229392 V. Description of the invention (7) It can make the adjacent two joints 31 that are finished by molding, on this day ^ Because the contact area of the strip is not large, so it will not be ordered The bondage is too large, and the connection force can be used to prevent warping due to the mismatch of the packaging colloid 26; At the same time, two adjacent packaging units 4 1 are connected at the same time, so 4 1 exerts moderate restraint to counteract The two big problems that make it not to be bent due to gravity 4 ′ and its structural design force is controlled at an ideal appropriate value, in order to achieve the effect 0 forming two long strips between the packaging unit 41 ^ 3 1 and the wafer carrier 2 〇The joint gel 2 6 releases its thermal expansion on both sides of the production section 31 when thermally expanded. The thermal expansion between the wafer carriers 20 should also be caused by the connection section 31. It is still used for the name of the packaging unit that can still be used on both ends. The gravity effect and shape phenomenon of the package unit 41 solves the problem of the conventional method and the constraint between the package units 41 is used to stabilize the overall molding structure.

The semiconductor device that has been molded as described above 40. Keshiyu A performs ball implantation, cutting, and testing after each step, and the process is like the process, and then listed in the semiconductor package. F A thin ball grid enzyme. The same, I will repeat the details; In addition, the aforementioned molding process is used to cover humming _

The encapsulating colloid 26 of the connecting portion 31 designed in the present invention is a thermosetting resin or polycarbonate such as Z (such as oxyepoxy resin).

Est.er), acrylic resin, and polymethyl chloride ycaybonat) thermoplastic resins, as well as (Pobeste limit 4ϊ :: ΓΓ phantom compression method and its molding structure are not only connected :: shown in Figure 3A , Change the upper mold 2 to form a car 2 fv mother—the adjacent mold cavity 2 corresponding to the wafer 21 has a connection channel 30, and the mold cavity 25 and the connection channel 30 are both

Page 111229392 V. Description of the invention (8) The molding compound is filled with the packaging colloid 26, and after the demolding step as shown in Figure 3B, all the packaging units 41 can be connected to each other and the packaging can be formed by the packaging. The connection portion 31 composed of the gel body 26 is, therefore, the packaging gel body 2 6 on the wafer carrier 20 will be integrally formed to cover each wafer 21, and since the connection portion 3 1 is as shown in FIG. 4 The top view shows two long strips of packaging gel 26 which are spaced apart from each other, so that the integrally formed packaging gel 26 will not contact the wafer carrier 20 with an excessively large area, but can be as in the previous embodiment. In order to maintain a proper binding force between each of the packaging units 41, warping and deformation of the molded structure due to mismatch of thermal expansion coefficient and gravity, and play a role in stabilizing the structure. In summary, the semiconductor molding method and the molding structure proposed by the present invention can indeed play a role in stabilizing the overall structure by the design of the connection portion, which will not cause warpage damage due to the mismatch of the thermal expansion coefficients of the materials, nor will it cause damage. The bending deformation of the structure due to the effect of gravity fully improves the strength of the structure and the yield of the process, and solves the problems encountered in the conventional technology. The above are only used to explain specific examples of the present invention, and are not intended to limit the implementable scope of the present invention. For example, those who are familiar with the technology can do all without departing from the spirit and technical ideas disclosed by the present invention. Equivalent modifications or changes shall still be covered by the scope of patent application mentioned later.

17437 联 测 .ptd Page 12 1229392 Brief description of the drawings [Simplified description of the drawings]: Figures 1 A and 1 B are schematic diagrams of the preferred embodiment of the semiconductor molding method and the molding structure proposed by the present invention; Figure 2 It is a top view of the molded structure shown in Figure 1B; Figures 3A and 3B are schematic diagrams of another embodiment of the semiconductor molding method and the molded structure proposed by the present invention; Figure 4 is shown in Figure 3B Top view of the molded structure; Figure 5 is a sectional view of a ball grid array semiconductor package; Figure 6 is a top view of a conventional substrate; Figure 7 is a sectional view of the substrate shown in Figure 6 after the molding process is warped FIG. 8 is a top view of another conventional substrate strip; FIG. 9 is a cross-sectional view of the substrate shown in FIG. 8 after the molding process; and FIG. 10 is a view of the substrate shown in FIG. 8 during the molding process. A cross-sectional view of bending deformation. 100 Base board 101 Pre-defined packaging area 102 Pre-defined packaging area 103 Pre-defined packaging area 104 Pre-defined packaging area 105 Pre-defined packaging area 106 Pre-defined packaging area 107 Gap 108 Dam structure 109 Packing colloid 20 Wafer carrier 23 Loading 21

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Brief description of the drawing 24 Lower mold 25 Mold cavity 26 Encapsulation gel 30 Connection channel 31 Connection portion 40 Semiconductor device 41 Encapsulation unit 50 Ball grid array seal 51 Substrate 52 Wafer 53 Welding wire 54 Conductive trace layer 55 Encapsulation gel 56 Fresh ball 61 Substrate Strip 62 Substrate unit 63 Encapsulation line 64 Substrate connection part 65 Wafer 66 Bonding wire 67 Encapsulation unit 68 Encapsulation gel 69 Gap 17437 Joint test. Ptd Page 14

Claims (1)

1229392 6. Scope of patent application 1. A semiconductor molding method includes the following steps: preparing a wafer carrier carrying a plurality of semiconductor wafers, and electrically connecting the semiconductor wafer with the wafer carrier; performing a molding step, The chip carrier is filled with a packaging colloid, and a plurality of packaging units respectively covering the semiconductor wafer are formed, and at least one adjacent two packaging units are formed with at least one connection portion composed of the packaging colloid. And performing a demolding step to form a semiconductor mold structure. 2. The semiconductor molding method according to item 1 of the patent application scope, wherein the connection portion is formed by filling the packaging gel in a preset connection channel in a mold of the molding step. 3. The semiconductor molding method according to item 1 of the scope of patent application, wherein two adjacent packaging units are formed with two connecting portions spaced apart from each other by a distance. 4. For the semiconductor molding method according to item 1 of the patent application scope, wherein the shape of the connecting portion is a long shape. 5. For the semiconductor molding method according to item 1 of the application, wherein the height of the connection portion is lower than the height of the packaging unit. 6. For example, the semiconductor molding method of the scope of the patent application, wherein the connection portion is formed between two adjacent packaging units of each group, and the connection portion is not formed at the packaging unit interval between the groups. 7. The semiconductor molding method according to item 1 of the patent application scope, wherein the connection portion is formed between all adjacent packaging units. 8. The semiconductor die-pressing method according to item 1 of the application, wherein the wafer carrier is a thin ball grid array substrate. 17437 联 测 .ptd Page 15 1229392 6. Application for Patent Scope 9. For example, the semiconductor die pressing method of the scope of application for patent No. 1, wherein a plurality of grid-like staggered predetermined cutting lines are formed on the wafer carrier, Each packaging unit is defined by the predetermined cutting lines. 10. The semiconductor molding method according to item 1 of the scope of patent application, wherein the semiconductor wafer is electrically connected to the wafer carrier with a fresh wire. 11. A semiconductor molding structure, comprising: a wafer carrier, a plurality of semiconductor wafers connected to the wafer carrier and electrically connected to the wafer carrier; and a packaging gel filled in the wafer carrier to form a plurality of wafers. The packaging units respectively covering the semiconductor wafer; and at least one connection portion are composed of the packaging gel and are formed between at least one adjacent two packaging units. 1 2. As in the semiconductor mold structure of item 11 in the scope of patent application, wherein adjacent packaging units are formed with two connecting portions spaced apart from each other by a distance ° 1 3. As in semiconductor mold structure in the area of patent application 11 The structure, wherein the shape of the connecting portion is a long shape. 14. The semiconductor molded structure according to item 11 of the scope of patent application, wherein the height of the connecting portion is lower than the height of the packaging unit. 1 5. According to the semiconductor molded structure of item 11 in the scope of patent application, wherein the connection portion is formed between two adjacent packaging units of each group, and the connection is not formed at the packaging unit interval between each group. unit. 16. The semiconductor mold structure according to item 11 of the patent application scope, wherein 17437 联 测 .ptd Page 16 1229392 6. Scope of patent application The connection part is formed between adjacent packaging units. 17. The semiconductor molded structure according to item 11 of the scope of patent application, wherein the wafer carrier is a thin ball grid array substrate. 18. The semiconductor molded structure according to item 11 of the scope of patent application, wherein a plurality of grid-like staggered predetermined cutting lines are formed on the wafer carrier, so that each package is defined by the predetermined cutting lines. unit. 19. The semiconductor molded structure according to item 11 of the scope of patent application, wherein the semiconductor wafer is electrically connected to the wafer carrier by a bonding wire. 17437 Joint Test.ptd Page 17