TWI229375B - Manufacturing method for distributing contacting parts of a semiconductor integrated component - Google Patents
Manufacturing method for distributing contacting parts of a semiconductor integrated component Download PDFInfo
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- TWI229375B TWI229375B TW092117340A TW92117340A TWI229375B TW I229375 B TWI229375 B TW I229375B TW 092117340 A TW092117340 A TW 092117340A TW 92117340 A TW92117340 A TW 92117340A TW I229375 B TWI229375 B TW I229375B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
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五 '發明說明(1) _ 本發明係一種與整人方 域產生接觸的方法,f: 冷體基材内的元件的數個區 --在半導體基材上:置一方二包括以下的步驟: 觸材料的第-個通路接觸孔在:緣緣V內並藉由内部充填接 一個作為形成第-個通路接罩幕亚在硬式罩幕内設置 口, 蜀孔之用的通往絕緣層的開 ――將第一個通路接觸孔向 接觸面為止, 蚀到到觸及待接觸的第一個 觸材料填入第一個通路接觸孔, 在一個線路層内形成與接觸材料連接的第一個線路。 件接::::f體基材内的元件具有若干個必須與其他元 按觸幵y成連接的區域。 電材剩1二SV 0 0 5 3 4 6 7 A1提出的方法是藉由填有一種導 又虚/_、k路接觸孔形成接觸。這種導電材料的另外一邊 -、一個或多個線路層連接。 怜胎ΐ果前面提及的元件是一種半導體元件(例如dram記 由閘帝朽播則此種元件具有一個設置在半導體基材上作為 極鱼:^構成之胞元電晶體的閘極的層堆疊,以及將閘電 /、千導體基材隔開(電絕緣)的閘極介質材料。 面的ί Γ為閘極的層堆疊(CG接觸)的接觸是作為連接在後 需$/中將產生的字線之用。為了要與層堆疊接觸,必 7·:立於層堆疊之上接觸區域的第一個絕緣層(例如以氮Five 'invention description (1) _ The present invention is a method for making contact with the whole human domain, f: several regions of the component in the cold body substrate-on the semiconductor substrate: one or two includes the following steps : The first contact hole of the contact material is in the edge V and is filled with one inside to form the first channel connection mask. The opening is set in the hard mask, and the hole for the Shu hole leads to the insulation layer. Open-etch the first via contact hole to the contact surface until it touches the first contact material to be contacted and fill the first via contact hole to form the first one connected to the contact material in a circuit layer line. Component connection :::: The component in the f-body substrate has several areas that must be connected with other elements by touching y. The method proposed by SV 0 0 5 3 4 6 7 A1 is to form a contact by filling a conductive / virtual / k / k contact hole. On the other side of this conductive material, one or more wiring layers are connected. The element mentioned earlier is a semiconductor element (for example, dram is recorded by the gate emperor. This type of element has a gate layer on a semiconductor substrate that acts as a pole fish: ^ Stack, and gate dielectric materials that separate (electrically-insulated) the gate / thousand-conductor substrate. The surface of Γ is the gate layer stack (CG contact). The contact is used as a connection. In order to make contact with the layer stack, it must be 7 ·: the first insulating layer (such as nitrogen
1229375 _^m_j211734〇 五、發明說明(2)1229375 _ ^ m_j211734〇 5. Description of the invention (2)
修正Amend
化物製成的絕緣層)的部分去除掉。氮化物是構成此種絶 緣層的一種適當的材料。 接著需要接觸在源極區/汲極區的半導體基材表面, 並在這個位置設定一個作為與一個位線(CB接觸)連接之用 的接觸。另外再設定一個與其他的擴散區(CD接觸)的接 觸,這個接觸亦同時接通半導體基材表面。Part of the insulating layer made of metal). A nitride is a suitable material for constituting such an insulating layer. Next, it is necessary to contact the surface of the semiconductor substrate in the source / drain region, and set a contact for connection to a bit line (CB contact) at this position. In addition, a contact with another diffusion region (CD contact) is set, and this contact also contacts the surface of the semiconductor substrate at the same time.
如德國專利登記1 0 1 2 7 8 8 8 . 8所述,可以藉由一個細 光蝕刻罩幕結構化的硬式罩幕(例如以多晶矽製成的罩幕二 來產生接觸。其步驟是首先在半導體基材上設置一個絕 層(例如TEOS層),以便將其後設置在這個絕緣層之上^ ! 體結構與半導體元件及導體隔開(電絕緣)。接著在這個^ 緣層上設置一個硬式罩幕,這個硬式掩模本身即具有供、'、巴 要產生的通路接觸孔之用的開口。 y、將 接著避開 表面所有未被 及C D接觸形成 在接下來 的通路接觸孔 如DE 1 0 0 53 4 6 7 A1所述,製造硬式罩幕的第一個, 驟是將硬式罩幕的材料以連續層的型式沉積出來。為了步 這個硬$罩幕層結構化,接著在這個硬式罩幕層上設置^ 個光刻膠層,然後對這個光刻膠層進行曝光,使 ^ 一 層供設置通路接觸孔之用的區域露空。經過蝕乎=幕 可形成這些接著使絕緣層露空的區域。 乂驟後即 氮化物層進行選擇性的蝕刻 氮化物層覆蓋的區域打開, 通路接觸孔。 的一個光蝕刻過程中’先將C B接觸乃 久LD接觸 以光刻膠填滿並覆蓋住。CD接觸之 、蜂接觸As described in German Patent Registration 1 0 1 2 7 8 8 8.8, contact can be made by a fine-light etched structured hard mask (such as mask 2 made of polycrystalline silicon). The steps are first An insulation layer (such as a TEOS layer) is provided on the semiconductor substrate so as to be disposed on top of the insulation layer ^! The bulk structure is separated from the semiconductor elements and conductors (electrically insulated). Next, the ^ A hard mask, the hard mask itself has openings for the via contact holes to be created. Y, will then avoid all contact holes on the surface that are not in contact with the CD to form the next via contact holes, such as According to DE 1 0 0 53 4 6 7 A1, the first method of manufacturing a hard mask is to deposit the material of the hard mask in a continuous layer. In order to structure this hard mask layer, then There are ^ photoresist layers on this hard mask curtain layer, and then this photoresist layer is exposed, leaving ^ a layer of area for the via contact holes to be exposed. After etching, these can be formed and then insulated. Dew empty area. After that, the nitride layer is selectively etched. The area covered by the nitride layer is opened, and the via contact hole is opened. During a photo-etching process, the CB contact, the LD contact, and the photoresist are used to fill and cover the CD contact. Bee contact
第6頁 1229375 修正 ____案號 92117340 _____ 年 月 五、發明說明(3) 孔的罩幕保持在開啟的狀態。接著就玎以經由麵刻步驟將 位於閘極(也就是層堆疊)上的絕緣層(例如氮化物層)去除 掉。 通路接觸孔完成結構化後,在其内部沒置一層隨後進 行化學分離所需的襯裡,並填入適當的導電材料(例如 鎢)。接著再將這些導電材料、位於導電材料之上的襯 裡、以及硬式罩幕去除。例如乾式蝕刻、濕式餘刻、或是 CMP方法(化學機械拋光法)均為適當的去除方法。接著即 可製作其他的線路層,但這需用用到另外一個硬式膜,因 此這種方法的缺點是需要另外再進行一次蝕刻步驟,以去 除這個硬式罩幕。 本發明的目的是要將與整合在半導體基材内的元件的 數個區域產生接觸的操作複雜性降到最低的程度。 為此本發明提出的方法是在將接觸材料填入第一個通 接^觸孔(4 )之前先進行以下的步驟: 將種抗反射塗層(ARC )材料填入第一個通路接肖 並在硬式罩幕⑺的表面上設置一個抗反射塗孔, ^ ^ ^ ^ ^ (ARC)Ji 4 # Λ A(ARC) 1 罩幕, 、、、策路、、去構的光刻膠 ^一將未被光刻膠罩幕覆蓋住的抗 下_方的硬式罩幕部分一起去除掉,射盒層(ARC)部分及其 將作為線路溝槽的未被光刻膠罩 下去除到觸及線路層為止, 勺絕緣層部分向 去除第一個通路接觸孔内的抗 久对塗層(ARC)材料,Page 6 1229375 Amendment ____ Case No. 92117340 _____ Year V. Description of the invention (3) The hood of the hole is kept open. Then, the insulating layer (such as a nitride layer) on the gate (ie, the layer stack) is removed by a face-etching step. After the via contact holes are structured, there is no layer inside them for subsequent chemical separation and filled with a suitable conductive material (such as tungsten). These conductive materials, the liner on top of the conductive materials, and the hard mask are then removed. For example, dry etching, wet etching, or CMP (chemical mechanical polishing) are suitable removal methods. Other circuit layers can then be made, but this requires the use of another hard film, so the disadvantage of this method is that an additional etching step is required to remove the hard mask. The object of the present invention is to minimize the operational complexity of making contact with several regions of a component integrated in a semiconductor substrate. To this end, the method proposed by the present invention is to perform the following steps before filling the contact material into the first through contact hole (4): filling an anti-reflective coating (ARC) material into the first via connection An anti-reflection coating hole is set on the surface of the hard mask curtain, ^ ^ ^ ^ ^ (ARC) Ji 4 # Λ A (ARC) 1 mask,,,, strategy, and deconstructed photoresist ^ As soon as the hard-resistant part of the underside that is not covered by the photoresist mask is removed, the ARC part and its unreacted photoresist as a line trench are removed to touch As far as the circuit layer is concerned, the insulation layer portion of the spoon is to remove the ARC material in the first via contact hole.
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-^^92117340 五、發明說明(4) 接著將接觸材料填入第一個 後再將接觸材料及硬式罩幕一觸孔及線路溝槽最 層表面為止。 起向下去除到至w、故 7 1 ^^ 芝少觸及絕緣 接著將接觸材料填入第_ 、 最後再將接觸材料及硬式罩 l路接觸孔及線路溝槽。 表面的^。 下韻刻到至少觸及絕緣層 在本發明提出的方法中, 、 第一個通路接觸孔的結構化之,硬式罩幕不但可作為 化線路。因此可以不必像現有I一 y以作為線路的結構 除硬式罩幕的步驟。 叮樣需要多進行一個去 本發明之方法的另外_個 填入的抗反射塗層(ARCm /驟疋將光刻膠罩幕及 去除#列BE W f A 起去除掉。 玄I示九刻膠罩幕的另外_ 完成線路結構的結構化後, 此、日守機是在硬式罩幕 去除光刻膠罩幕的第三個^將光刻膠軍幕去除掉。 及硬式罩幕一起去除掉, 二犯的時機是將光刻膠罩幕 刻膠罩幕去除掉。 /疋在去除硬式罩幕之前先將光 本:明的方法建議採用 罩幕。原因是以這種材料 式罩幕疋以多晶矽製成的 製程中的操作複雜性比較低夕。石夕)製成的罩幕在本發明的儀 在本發明之方法的一 是被一種傾斜蝕刻剖面結構化。’的實施方式中,硬式罩幕 這種傾斜蝕刻剖面可 ;k路接觸孔的結構化。相較 ,-^ 92117340 V. Explanation of the invention (4) Then fill the contact material into the first one, and then touch the contact material and the hard cover first contact hole and the top surface of the circuit trench. It is removed from the bottom to w, so 7 1 ^^ Zhi touches the insulation, then fills the contact material with the first _, and finally the contact material and the hard cover l the contact hole and the circuit trench. ^ On the surface. The rhyme is engraved to at least touch the insulation layer. In the method proposed in the present invention, the first via contact hole is structured, and the hard cover can not only be used as a circuit. Therefore, it is not necessary to remove the hard mask step as the structure of the existing I-y circuit. It is necessary to perform one more anti-reflection coating (ARCm / abruptly remove the photoresist mask and remove #column BE W f A from the method of the present invention). Xuan I shows 9 ticks After the structure of the circuit structure is completed, this machine is the third one to remove the photoresist mask from the hard mask. The photoresist military curtain is removed together with the hard mask. The timing of the second offense is to remove the photoresist mask and the engraved mask. / 疋 Before removing the hard mask, the light method is recommended. The method is recommended to use the mask. The reason is that this kind of material mask的 The operation complexity in the process made of polycrystalline silicon is relatively low. Shi Xi) The mask made in the apparatus of the present invention is one of the methods of the present invention structured by an oblique etching profile. In the embodiment of the embodiment, the oblique etching section of the hard mask can be structured as a k-channel contact hole. Compared to
第8頁 1229375 案號 92117341 修正 曰 五、發明說明(5) 使用傾斜兹刻剖面的好處是所形成的通 那個面上的”傾斜角,,呈現—偏向上緣的線路。緣層的 脾妗=—方面也可以利用這種傾斜蝕刻剖面的傾斜角作用 ^度調整的比較小。如果不使用這種方法斜= /、靶經由更複雜費事的光蝕刻步二i 的製程(例如以鎢—RIE、線路取二4上;:以更加複雜 % w 冰崎取代一般使用的鎢一雙波紋綠 =才能達到縮小線路寬度的目的。使用傾制刻剖面—線 -ΠΓ用比較簡單的方法達到縮小線路寬度的目的,另 半導體元件獲得較好的參數改善:較小,目此可以使 結構化。種有利的k擇疋採用乾式蝕刻方法使硬式罩幕 SF6、HBr、及/或He/〇枸可作 刻氣體,並依據所使用姓刻氣體的種=法用? 刻剖面或筆直蝕刻剖面。 禋頦决疋要使用傾斜蝕 為了避免不同材料之間發生化 材料之前在會與接觸材料接觸的表面上Z 1 ^填入接觸 裡。 仅®上光〉儿積出一層襯 欽(T i )或氮化鈦(τ丨N)均可 可以用鎢作為本發明之方法所\製作襯裡的材料。 本發明的另外一種實施方斤而的接觸材料。 拋光法^去_除接觸材料及硬式罩,幕中是以CMP方法(化學機械 通常每一個半導體元件都會 數個&域與半導體基材 1229375 案號 92117340 五、發明說明(6) 接觸,例如金屬氧化物 極。因此應以形成第一 一直通達到第二個待接 第一個通路接觸孔 接。第一種可能的方式Page 8 1229375 Case No. 92117341 Amendment V. Description of the invention (5) The advantage of using an oblique cut section is the "inclination angle" formed by that surface, which presents a line that is biased toward the upper edge. The spleen of the marginal layer =-It is also possible to use the tilt angle effect of this oblique etching profile to adjust the degree of adjustment relatively small. If this method is not used, oblique = /, the target is subjected to a more complicated and difficult photo-etching step (i.e., tungsten) —RIE, the line is taken from 2 to 4 ;: The more complex% w Bing Qi is used to replace the commonly used tungsten with a pair of corrugated green = to achieve the purpose of reducing the width of the line. Using the tilted carved profile—line-ΠΓ is achieved in a relatively simple way. The purpose of reducing the width of the circuit is to improve the parameters of the semiconductor device: smaller, so that the structure can be structured. A favorable option is to use a dry etching method to make the hard mask SF6, HBr, and / or He / 〇 Citronella can be used as an engraving gas, and it can be engraved or straight-etched according to the type of the engraved gas used. 禋 颏 Determine the use of oblique etching to avoid chemical contact between different materials. Z 1 ^ is filled into the contact surface of the material. Only ® glazing> a layer of lining (T i) or titanium nitride (τ 丨 N) can be used as the method of the present invention. The material of the lining. Another contact material that implements the present invention. Polishing method ^ remove_ except for contact material and hard cover, the method is CMP method (chemical machinery usually has several & domain and Semiconductor substrate 1229375 Case No. 92117340 V. Description of the invention (6) Contact, such as metal oxide electrode. Therefore, it should be connected to form the first through to the second via contact hole to be connected to the first via. The first possible the way
路隔開 的第二 第 料在另 特 晶體需 構造層 是:在 物層及 觸,所 同時以 個通路 將第一 覆蓋住 助材料 通路接 及第二 如 可能的 (電絕緣)並與第 個線路。 二種可能的方式 外一個線路層内 別是在 要與電 的層堆 半導體 一個覆 以要形 選擇性 接觸孔 個通路 ;接著 去除掉 觸孔進 個通路 同前面 方式與 與電晶體 晶體的閘 疊構成。 基材表面 蓋層構成 成通往閘 的蝕刻將 向下钱刻 接觸孔或 將覆蓋層 ;最後再 行如前面 接觸孔相 已經說明 外界形成 =t體(MOS)電晶體的源極和沒 ::路接觸孔相同的方法同 =面的第二個通路接觸孔。乂 有兩種可能的方式與外 是在絕緣層内形ώ ^ 电努 二個诵^: 2 個與第一個餐 路接觸孔内的接觸材料連襄 是使第二個通路接觸 與第二個導體連接。内的接觸和 的接觸中,在記憶胞元内 極接觸。鬥H ^ ^ Ί 往按觸閘極通常是由具有若+而 上設置-個至少?方式的特摆 的層堆疊;為了二:f問極“ 極乳化物層的第三個通路接曰為 第一,通路接觸孔或是第一及i 至覆盍層,‘然後再用 向下钱刻至問極氧化物層,The second material separated by the circuit in another special crystal needs to be a structural layer: in the physical layer and in contact, at the same time, the first covering the auxiliary material path is connected to the second if possible (electrically insulated) and connected to the first layer. Lines. There are two possible ways. In the outer layer of the circuit, the semiconductors in the layer stack to be electrically covered are covered with selective contact holes vias; then the contact holes are removed and the vias are removed. Fold composition. The cover layer on the surface of the substrate is structured so that the etching leading to the gate will engraving the contact hole or the cover layer; finally, as before, the contact hole phase has shown that the source of the external body = MOS (MOS) transistor and no: : Road contact hole The same way as the second via contact hole on the surface.乂 There are two possible ways and the outer shape is inside the insulation layer. ^ Electric Nu two recitations ^: 2 contact materials inside the contact hole of the first dining path. The second contact is to make the second path contact with the second Conductor connections. Among the contacts and the contacts, the polar contacts are in the memory cells. Bucket H ^ ^ Ί Pushing down the gate is usually set by having + if at least? The special pendulum layer stacking method; for the two: f question "the third path of the polar emulsion layer is connected as the first, the contact hole of the path or the first and i to the overlay layer, and then use the downward Money carved to the interlayer oxide layer,
塗層(ARC)材料對第三個 ί1 通路接觸孑L或是第 同的處理步驟。 &弟一 過的,第三個通路接觸 電連接。 有兩稽The coating (ARC) material makes contact with the third 通路 1 path or the same processing step. & Brother passed, the third path contacts the electrical connection. There are two
第10頁 1229375 五發明說明⑺ 案號 92117340Page 10 1229375 Description of the five inventions⑺ Case No. 92117340
修正 弟—種可能的方式是在絕緣層内形成 個 路或漦 層内形成一 孔:弟一及第二個線路隔開(電絕緣 3的接觸材料連接的第三個線路。 ^乐 料在^,種可能的方式是使第三個通路接 ^外一個線路層内與第三個導體連J觸孔 料,種有利的方式是以光刻膠作為前面所說 塗展欠外一種有利的方式是在光刻膠之下設置 曰(ARC),以便使去除光刻膠的工作 法。以下就按照第1圖至第11圖的順序說明本i 7第1圖所示,首先在半導體基材 設 絕緣層(2)係製作成以⑽層 上:,出-個由多晶石夕構成的硬式罩幕(7: 刻)/ 2圖戶斤示,接著進行CT光”(接觸至 第—個、s就是說在這個光蝕刻步驟中將產生形月 個通路接觸孔(4)、形成cD接觸的第二個主 丄二以及形成CG接觸的第三個通路接觸孔(6: 要將弟一個光刻膠罩幕(7)曝光。如第期所示 顯影完成後’接著經由-個乾式蝕刻步驟將硬 打開’此乾式蝕刻步驟使用之蝕刻氣體可以是 C12、及/或He/〇2。使用這些蝕刻氣體或是這些 混合氣體可以確保能夠避開位於下方的絕緣斤 擇性的姓刻。 ' 與第一個線 個通路接觸 内的接觸材 的輔助材 一個抗反射 ‘易。 &明的方 置一個絕緣 後在絕緣層 〇 電晶體光名虫 < CB接觸的 L路接觸孔 。為此首先 ’待光刻膠 式罩幕(3) SF6、HBr、 &刻氣體的 (2 )進行選 1229375 案號 92117340 、發明說明(8) 採 以 寸 置 致 可以視所使用的乾式蝕刻方法決定在硬式 =傾斜蝕刻剖面或筆直蝕刻剖面。採用 上^ 是在第酷光刻膠罩幕⑺及硬式罩幕 與硬式罩幕⑺的厚度相同。= =C)的厚度大 個 可 飿列t後接者就開始蝕刻硬式罩幕(3)。同樣的,這 ,利用其他的化學触刻方法進/。當然也 θ ARC )。絕緣層(2 )的露空區域合因為傾==二反射塗層 是所謂的Taper: —端成錐二;^田傾^餘刻邊(也就 ^面說明過的一樣使通路接觸孔的尺寸小。樣就叮 此時所:來的#驟是去除光刻膠罩*⑺。如目式所示, 1幕⑺造成任何不良影響的情況下進行。不曰對先 問極ΐ ^ : ΐ路接觸孔(6)的作用是形成CG接觸。由—個 層堆® 曰(9 )及一個位於其上的氮化物層(1 0 )構成ή6 首先ίΞΠ極⑻。由於㈣刻(接觸至電晶體姓刻)-孔(4)及氮化物進行蝕刻’因此只有第-個通路接3觸 電晶體:;個通路接觸孔(5)會被打開。⑽刻(接觸至 刻)^ 後接著進行CG光钱刻(接觸至閉極^ 的第一彳一種由光刻膠構成的辅助材料(11)將已彤成 蓋住。::::觸孔⑷及第二個通路接觸孔(5)填滿並覆 接者利用-種不會選擇性避開氣化物的餘刻方^Correct the brother-a possible way is to form a hole in the insulating layer or a hole in the layer: the brother and the second line are separated (the third line connected by the contact material of the electrical insulation 3. ^ 乐 料 在^, A possible way is to connect the third via ^ the outer circuit layer is connected to the third conductor J hole material, a favorable way is to use the photoresist as the aforementioned coating is less advantageous The method is to set (ARC) under the photoresist in order to make the photoresist removal method work. The following will be described in the order of Fig. 1 to Fig. 11 as shown in Fig. 1 of this i. The insulating layer (2) is made of a solid layer: a hard-type curtain made of polycrystalline stone (7: engraved) / 2 pictures, followed by CT light "(contact to the first One, s means that in this photo-etching step a zigzag via contact hole (4), a second main contact forming a cD contact, and a third via contact forming a CG contact (6: A photoresist mask (7) is exposed. As shown in the issue, after the development is completed, the substrate is hardened by a dry etching step. Turn on 'The etching gas used in this dry etching step can be C12, and / or He / 〇2. Using these etching gases or a mixture of these gases can ensure that the optional last name of the insulation can be avoided.' And the Auxiliary materials of the contact material inside the wire-to-channel contact are easy to reflect. &Amp; A square hole is placed in the insulation layer after the insulation. The phototransistor & CB contact L road contact hole. To this end, first 'To be photoresist-type mask (3) SF6, HBr, & (2) for gas engraving 1229375 case number 92117340, description of the invention (8) depending on the dry etching method used can be determined in Hard = oblique etched profile or straight etched profile. The above ^ is used in the thickness of the Di photoresist mask and the thickness of the hard mask and the hard mask. = = C) The thickness can be queued after t. The person begins to etch the hard mask (3). Similarly, this is done by using other chemical etching methods. Of course, θ ARC). The exposed area of the insulating layer (2) is combined with a tilt == two reflective coatings It ’s the so-called Taper: —end into a cone; ^ 余 刻 边 (The size of the via contact hole is also small as explained on the ^ surface. This is what I do now: the #step is to remove the photoresist cover * ⑺. As shown in the form, 1 act ⑺ It does not cause any adverse effects. It does not affect the first contact 问: The function of the contact hole (6) is to form a CG contact. A layer stack ® (9) and a nitride on it The layer (1 0) constitutes the first price. Firstly, because of the engraving (contact to the transistor name)-the hole (4) and the nitride are etched, so only the first via is connected to the 3 contact crystal :; the via contact hole (5) will be opened. Engraving (contact to engraving) ^ followed by CG light money engraving (the first contacting to the closed electrode ^ a kind of auxiliary material (11) composed of photoresist will cover it.) :::: contact hole ⑷ and the second via contact hole (5) is filled and covered by the user-a kind of remaining method that will not selectively avoid the gas ^
1229375 〜案號 9211^0 五、發明說明(9) 修正 曰 _月 氮化物層Γ〗η τ & 圖所示將^一 ^、画刻至閘極氧化物層(9),也就是如第6 在弟二個通路接觸孔(6)打開至閘極氧化物層㈠)。 射塗層A由光刻膠構成的辅助材料(1 1 )去除之後,用抗反 5,心填R:):!::2)將第-、二、三個通路接觸孔(4, 表面上形成*復有;车住开/j妾著在抗反射塗層(ARC)材料(12)的 (13)。接i r ^ t 線路結構的第二個光刻膠罩幕 化硬式I 圖所示,以第二個光刻膠罩幕(13>m 化更式罩幕(3)。此步驟首先是以一種齡六、鉍以“㈧…構 射塗層/ 種乾式蝕刻方法將反 可能出現=: 成的覆蓋層打開。為^ (ARC)持料搁(F^)”構造,可㈣ 用Η (12)另外進行一個後退(Recess)處理步驟。 法,例^種對多晶硬式罩幕(3)的適當的乾式餘刻方 以s F為蝕刻氣體的化學蝕刻法,可以爹成斗、览 内形成傾斜蝕刻剖面。視蝕刻過程及硬式n f %幕 可以在㈣剖面上形成不同的 坆種方式可以大幅縮小待形成線路的寬度。因又 所不(無傾斜蝕刻剖面),利用這種蝕刻方法可以Y回 準蝕刻方法(未使用硬式罩幕)更小的線路寬度。又于才示 另外一種縮小線路寬度的可能方法是在二° (ARC)材料(12)形成的覆蓋層時以適當的蝕刻材反^層 塗層(ARC)材料(12)上钱刻出傾斜的邊(也就是所謂的 Taper : —端成錐形逐漸變細),這樣就可以形 :線路溝槽(14),進而達到縮小待形成之線路ς目父小 的〇1229375 ~ Case No. 9211 ^ 0 V. Description of the invention (9) Revised _ month nitride layer Γ〗 η τ & As shown in the figure, ^ 一 ^ is drawn to the gate oxide layer (9), which is as follows The sixth via contact hole (6) opens to the gate oxide layer ㈠). After removing the auxiliary material (1 1) of the photoresist layer A made of photoresist, fill it with anti-reflection 5, core R:):! :: 2) and contact the first, second, and third via holes (4, surface On the top surface, there is a complex structure; the car stays open / j is held in (13) of the anti-reflective coating (ARC) material (12). The second photoresist cover of the ir ^ t circuit structure is hardened and the I type is shown in FIG. As shown in the figure, a second photoresist mask (13 > m) is used. This step is based on an age-six, bismuth coating with "㈧ ... Appear =: The cover layer is opened. For the ^ (ARC) holding structure (F ^) "structure, you can use) (12) to perform another Recess processing step. Method, example ^ Hard type for polycrystalline The appropriate dry type chemical etching method of the mask (3) using s F as an etching gas can form a slanted etching profile within the bucket. Depending on the etching process and the hard nf% curtain, different shapes can be formed on the cross section. This method can drastically reduce the width of the line to be formed. Because there is nothing (no inclined etching profile), this etching method can be used to align the etching method (without using a hard cover) (Curve) smaller circuit width. It is shown that another possible method to reduce the circuit width is to coat the layer (ARC) material with a suitable etching material when the cover layer formed by the 2 ° (ARC) material (12). (12) Sculpt the sloping edge (also called Taper: the end tapers and tapers) on the money, so that it can be shaped: the line groove (14), and then reduce the line to be formed 〇
第13頁 1229375 -Τ' 案號 92117340 五、發明說明(10) 接著搭配第二個光刻膠罩幕(1 3 )將線路溝槽(1 4 )高下 蝕刻至線路層(1 5 )。 待線路溝槽(1 4 )的結構化完成後,將第二個光刻膠罩 幕(1 3 )去除掉。在這個蝕刻過程中,閘極(8 )的氮化物層 (1 0 )會受到抗反射塗層(A R c )材料(1 2 )的保護。 如第1 0圖所示,待線路溝槽(丨4 )形成後,先在線路 槽部沉積出一層由氮化鈦(TiN)或鈦7氮化鈦 路溝槽(14)填滿。 々丧觸材枓(16)將線Page 13 1229375-T 'Case No. 92117340 V. Description of the invention (10) Next, the circuit trench (1 4) is etched to the circuit layer (1 5) with a second photoresist mask (1 3). After the structuring of the line trench (1 4) is completed, the second photoresist mask (1 3) is removed. During this etching process, the nitride layer (1 0) of the gate (8) is protected by the anti-reflection coating (A R c) material (1 2). As shown in Fig. 10, after the line trench (4) is formed, a layer of titanium nitride (TiN) or titanium 7 titanium nitride road trench (14) is deposited in the line trench portion. 々 mourning materials 枓 (16)
如第1 1圖所示,接著進行由兩個步驟 方法(化學機械拋光法)。首先進行 j的鎢--CMP 疋八孓的鎢--CMP方法(化學機械拋光法)。 個步驟,也就是硬式罩幕__CMP方法(化者進^弟一 將硬式罩幕(3)去除掉。由於以這種方士械抛光法), 在標機方法(化學機械抛光法)的過程中二式【3 需要另外增加一個去除硬式罩幕的步驟。卩,因此不As shown in Fig. 11, a two-step method (chemical mechanical polishing method) is performed next. First, a tungsten-CMP method of tungsten-CMP and a tungsten-CMP method (chemical mechanical polishing method) was performed. This step, that is, the hard mask __CMP method (remove the hard mask (3) by the chemist Jin Yiyi. Because of this alchemy polishing method), the process in the standard machine method (chemical mechanical polishing method) The Chinese style [3 requires an additional step to remove the hard cover. Alas, so not
第14頁 1229375 _案號 92117340_年月日__ 圖式簡單說明 第1圖··完成絕緣層及硬式罩幕之設置後半導體基材的斷 面圖。 第2圖:對第一個光刻膠罩幕完成曝光及顯影後半導體基 材的斷面圖。 第3圖:對硬式罩幕完成第一次結構化之後半導體基材的 斷面圖。 第4圖:經由一個蝕刻步驟形成第一及第二個通路接觸孔 後半導體基材的斷面圖。 第5圖:完成辅助層之設置後半導體基材的斷面圖。 第6圖:形成第三個通路接觸孔後半導體基材的斷面圖。 _ 第7圖··完成抗反射塗層(ARC)之設置及帶有結構化的第二 個光刻膠罩幕的半導 體基材的斷面圖。 第8圖:完成第二個光刻膠罩幕的結構化步驟後半導體基 材的斷面圖。 第9圖:向下蝕刻絕緣層至觸及線路層之後半導體基材的 斷面圖。 弟1 0圖·完成填充接觸材料之步驟後半導體基材的斷面 圖。 第1 1圖:向下去除接觸材料及硬式罩幕至觸及絕緣層表面 b 之後半導體基材的斷面圖。 元件符號說明:Page 14 1229375 _Case No. 92117340_Year Month Day__ Brief Description of Drawings Figure 1 ·· Sectional view of the semiconductor substrate after the installation of the insulating layer and the hard mask. Figure 2: A cross-sectional view of the semiconductor substrate after the first photoresist mask has been exposed and developed. Figure 3: A cross-sectional view of a semiconductor substrate after the first structuring of the hard mask. Figure 4: A cross-sectional view of the semiconductor substrate after the first and second via contact holes are formed through an etching step. Figure 5: A cross-sectional view of the semiconductor substrate after the setting of the auxiliary layer is completed. Fig. 6: A cross-sectional view of a semiconductor substrate after forming a third via contact hole. _ Figure 7 ·· Sectional view of the completion of the anti-reflection coating (ARC) setup and the semiconductor substrate with a structured second photoresist mask. Figure 8: A cross-sectional view of the semiconductor substrate after completing the structuring step of the second photoresist mask. Figure 9: A cross-sectional view of the semiconductor substrate after the insulating layer is etched down to touch the wiring layer. Figure 10 · A cross-sectional view of the semiconductor substrate after the step of filling the contact material is completed. Figure 11: A cross-sectional view of the semiconductor substrate after removing the contact material and the hard cover downward to reach the surface b of the insulating layer. Component symbol description:
第15頁 1229375 案號 92117340 年 月 修正 圖式簡單說明 I 半導體基材 3 硬式罩幕 5 第二個通路接觸孔 7 第一個光刻膠罩幕 9 閘極氧化物層 II 光刻膠構成的輔助材料 12 抗反射塗層(ARC)材料 1 5、1 6 接觸材料 2 絕緣層 4 第一個通路接觸孔 6 第三個通路接觸孔 8 閘極 10 氮化物層 14 線路層 13 第二個光刻膠層Page 15 1229375 Case No. 92117340 Revised diagrams Brief description I Semiconductor substrate 3 Hard mask 5 Second via contact hole 7 First photoresist mask 9 Gate oxide layer II Photoresist Auxiliary material 12 Anti-reflection coating (ARC) material 1 5, 1 6 Contact material 2 Insulating layer 4 First via contact hole 6 Third via contact hole 8 Gate 10 Nitride layer 14 Circuit layer 13 Second light Scoring
第16頁Page 16
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DE10229188A DE10229188A1 (en) | 2002-06-28 | 2002-06-28 | Method for producing contacts to parts of a component integrated in a semiconductor substrate |
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DE102005053537A1 (en) | 2005-11-08 | 2007-05-16 | Hauni Maschinenbau Ag | Device for optically monitoring a material strand of the tobacco processing industry |
DE102009046242B4 (en) * | 2009-10-30 | 2013-11-28 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | A method of manufacturing a semiconductor device having differently sized vias by splitting the via patterning process |
US9640538B2 (en) * | 2014-10-29 | 2017-05-02 | Globalfoundries Inc. | Embedded DRAM in replacement metal gate technology |
US9653345B1 (en) * | 2016-01-07 | 2017-05-16 | United Microelectronics Corp. | Method of fabricating semiconductor structure with improved critical dimension control |
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DE10053467A1 (en) | 2000-10-27 | 2002-05-16 | Infineon Technologies Ag | Forming contacts in ICs involves chemically-mechanically polishing structure resulting from applying mask layer, forming opening, etching contact hole, applying liner, contact material |
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2002
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US7396749B2 (en) | 2008-07-08 |
DE10229188A1 (en) | 2004-01-29 |
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