EP1518269A1 - Method for contacting parts of a component integrated into a semiconductor substrate - Google Patents
Method for contacting parts of a component integrated into a semiconductor substrateInfo
- Publication number
- EP1518269A1 EP1518269A1 EP03761426A EP03761426A EP1518269A1 EP 1518269 A1 EP1518269 A1 EP 1518269A1 EP 03761426 A EP03761426 A EP 03761426A EP 03761426 A EP03761426 A EP 03761426A EP 1518269 A1 EP1518269 A1 EP 1518269A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- contact
- contact hole
- hard mask
- line
- arc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10229188A DE10229188A1 (en) | 2002-06-28 | 2002-06-28 | Method for producing contacts to parts of a component integrated in a semiconductor substrate |
DE10229188 | 2002-06-28 | ||
PCT/DE2003/002104 WO2004003998A1 (en) | 2002-06-28 | 2003-06-24 | Method for contacting parts of a component integrated into a semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1518269A1 true EP1518269A1 (en) | 2005-03-30 |
Family
ID=29795988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03761426A Withdrawn EP1518269A1 (en) | 2002-06-28 | 2003-06-24 | Method for contacting parts of a component integrated into a semiconductor substrate |
Country Status (5)
Country | Link |
---|---|
US (1) | US7396749B2 (en) |
EP (1) | EP1518269A1 (en) |
DE (1) | DE10229188A1 (en) |
TW (1) | TWI229375B (en) |
WO (1) | WO2004003998A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1782703B1 (en) | 2005-11-08 | 2016-01-20 | Hauni Maschinenbau Aktiengesellschaft | Device for optical monitoring of a material strand of the tobacco processing industry |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102009046242B4 (en) * | 2009-10-30 | 2013-11-28 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | A method of manufacturing a semiconductor device having differently sized vias by splitting the via patterning process |
US9640538B2 (en) * | 2014-10-29 | 2017-05-02 | Globalfoundries Inc. | Embedded DRAM in replacement metal gate technology |
US9653345B1 (en) * | 2016-01-07 | 2017-05-16 | United Microelectronics Corp. | Method of fabricating semiconductor structure with improved critical dimension control |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
US5879866A (en) * | 1994-12-19 | 1999-03-09 | International Business Machines Corporation | Image recording process with improved image tolerances using embedded AR coatings |
KR0168346B1 (en) * | 1994-12-29 | 1998-12-15 | 김광호 | Capacitor using high deelectric material and its fabrication method |
US6008121A (en) * | 1996-03-19 | 1999-12-28 | Siemens Aktiengesellschaft | Etching high aspect contact holes in solid state devices |
TW377495B (en) * | 1996-10-04 | 1999-12-21 | Hitachi Ltd | Method of manufacturing semiconductor memory cells and the same apparatus |
US6238971B1 (en) * | 1997-02-11 | 2001-05-29 | Micron Technology, Inc. | Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures |
US6153490A (en) * | 1997-07-01 | 2000-11-28 | Texas Instruments Incorporated | Method for forming integrated circuit capacitor and memory |
EP0908945A3 (en) | 1997-09-29 | 2000-09-27 | Siemens Aktiengesellschaft | Dual damascene with self aligned via interconnects |
EP0915528A3 (en) | 1997-11-07 | 1999-08-11 | Nec Corporation | High frequency filter and frequency characteristics regulation method therefor |
JP3075237B2 (en) | 1997-11-07 | 2000-08-14 | 日本電気株式会社 | High frequency filter and method of adjusting frequency characteristics thereof |
JPH11154703A (en) * | 1997-11-20 | 1999-06-08 | Toshiba Corp | Manufacture of semiconductor device |
US5922515A (en) * | 1998-02-27 | 1999-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approaches to integrate the deep contact module |
US6103456A (en) | 1998-07-22 | 2000-08-15 | Siemens Aktiengesellschaft | Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication |
US6423627B1 (en) * | 1998-09-28 | 2002-07-23 | Texas Instruments Incorporated | Method for forming memory array and periphery contacts using a same mask |
US6287951B1 (en) * | 1998-12-07 | 2001-09-11 | Motorola Inc. | Process for forming a combination hardmask and antireflective layer |
US6235628B1 (en) * | 1999-01-05 | 2001-05-22 | Advanced Micro Devices, Inc. | Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer |
US6232238B1 (en) * | 1999-02-08 | 2001-05-15 | United Microelectronics Corp. | Method for preventing corrosion of bonding pad on a surface of a semiconductor wafer |
US6265296B1 (en) * | 1999-03-04 | 2001-07-24 | Vanguard International Semiconductor Corporation | Method for forming self-aligned contacts using a hard mask |
US6262484B1 (en) * | 1999-04-20 | 2001-07-17 | Advanced Micro Devices, Inc. | Dual damascene method for backened metallization using poly stop layers |
TW410400B (en) * | 1999-04-20 | 2000-11-01 | Winbond Electronics Corp | Method for improving step coverage of trench film deposition and its applications |
US6211068B1 (en) * | 1999-05-25 | 2001-04-03 | United Microelectronics Corp. | Dual damascene process for manufacturing interconnects |
DE19937994C2 (en) | 1999-08-11 | 2003-12-11 | Infineon Technologies Ag | Etching process for a dual damascene structuring of an insulating layer on a semiconductor structure |
US6727143B1 (en) * | 1999-11-30 | 2004-04-27 | Advanced Micro Devices, Inc. | Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation |
KR100327596B1 (en) * | 1999-12-31 | 2002-03-15 | 박종섭 | Method for fabricating contact plug of semiconductor device using Selective Epitaxial Growth of silicon process |
JP2001358216A (en) | 2000-06-16 | 2001-12-26 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device, burying material used for method for manufacturing semiconductor device and semiconductor device |
US6497993B1 (en) * | 2000-07-11 | 2002-12-24 | Taiwan Semiconductor Manufacturing Company | In situ dry etching procedure to form a borderless contact hole |
US6426298B1 (en) * | 2000-08-11 | 2002-07-30 | United Microelectronics Corp. | Method of patterning a dual damascene |
DE10053467A1 (en) | 2000-10-27 | 2002-05-16 | Infineon Technologies Ag | Forming contacts in ICs involves chemically-mechanically polishing structure resulting from applying mask layer, forming opening, etching contact hole, applying liner, contact material |
US6440753B1 (en) * | 2001-01-24 | 2002-08-27 | Infineon Technologies North America Corp. | Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines |
US6372631B1 (en) * | 2001-02-07 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of making a via filled dual damascene structure without middle stop layer |
DE10127888A1 (en) * | 2001-06-08 | 2002-12-19 | Infineon Technologies Ag | Process for forming contact holes in contact regions of components integrated in a substrate comprises applying an insulating layer on a substrate with the integrated components, and applying a mask with openings |
TW544857B (en) * | 2002-07-30 | 2003-08-01 | Promos Technologies Inc | Manufacturing method of dual damascene structure |
-
2002
- 2002-06-28 DE DE10229188A patent/DE10229188A1/en not_active Ceased
-
2003
- 2003-06-24 EP EP03761426A patent/EP1518269A1/en not_active Withdrawn
- 2003-06-24 WO PCT/DE2003/002104 patent/WO2004003998A1/en active Application Filing
- 2003-06-24 US US10/519,741 patent/US7396749B2/en not_active Expired - Lifetime
- 2003-06-25 TW TW092117340A patent/TWI229375B/en not_active IP Right Cessation
Non-Patent Citations (1)
Title |
---|
See references of WO2004003998A1 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1782703B1 (en) | 2005-11-08 | 2016-01-20 | Hauni Maschinenbau Aktiengesellschaft | Device for optical monitoring of a material strand of the tobacco processing industry |
Also Published As
Publication number | Publication date |
---|---|
TWI229375B (en) | 2005-03-11 |
US20060094217A1 (en) | 2006-05-04 |
TW200403734A (en) | 2004-03-01 |
WO2004003998A1 (en) | 2004-01-08 |
US7396749B2 (en) | 2008-07-08 |
DE10229188A1 (en) | 2004-01-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20050107 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IE IT |
|
RBV | Designated contracting states (corrected) |
Designated state(s): DE |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: GUSTIN, WOLFGANG Inventor name: DITTMAR, LUDWIG Inventor name: STEGEMANN, MAIK |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: GUSTIN, WOLFGANG Inventor name: DITTMAR, LUDWIG Inventor name: STEGEMANN, MAIK |
|
17Q | First examination report despatched |
Effective date: 20090623 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: INFINEON TECHNOLOGIES AG |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: QIMONDA AG |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20101228 |