TW201351487A - Fabricating method of semiconductor device and semiconductor device - Google Patents
Fabricating method of semiconductor device and semiconductor device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- 229920005591 polysilicon Polymers 0.000 claims abstract description 60
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000009792 diffusion process Methods 0.000 claims description 89
- 238000004519 manufacturing process Methods 0.000 claims description 57
- 229910052732 germanium Inorganic materials 0.000 claims description 30
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 30
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 229910052715 tantalum Inorganic materials 0.000 claims description 17
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 17
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 15
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 14
- 229910052707 ruthenium Inorganic materials 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 209
- 150000004767 nitrides Chemical class 0.000 description 15
- 239000000463 material Substances 0.000 description 9
- 238000009413 insulation Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
本發明是有關於一種半導體裝置的製造方法以及半導體裝置。 The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.
半導體積體電路、尤其使用金屬氧化物半導體(Metal Oxide Semiconductor，MOS)電晶體(transistor)的積體電路正趨於高積體化的方向。隨著該高積體化，MOS電晶體已微細化至奈米領域。當此種MOS電晶體的微細化發展時，存在下述問題，即：漏(leak)電流的抑制變得困難，從而會因確保必要電流量的要求而無法輕易減小電路的佔有面積。為了解決此種問題，提出有環繞閘極電晶體(Surrounding Gate Transistor，以下稱作「SGT」)，其採用下述結構，即：相對於基板而沿垂直方向配置源極(source)、閘極(gate)、汲極(drain)，且閘極電極圍繞柱狀半導體層(例如參照專利文獻1、專利文獻2、專利文獻3)。 A semiconductor integrated circuit, in particular, an integrated circuit using a metal oxide semiconductor (MOS) transistor is tending to be highly integrated. With this high integration, MOS transistors have been miniaturized into the nanometer field. When the miniaturization of such a MOS transistor progresses, there is a problem that the suppression of the leakage current becomes difficult, and the occupied area of the circuit cannot be easily reduced by securing the required amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as "SGT") has been proposed which has a structure in which a source and a gate are arranged in a vertical direction with respect to a substrate. (gate), drain, and the gate electrode surrounds the columnar semiconductor layer (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).
先前的SGT的製造方法中，形成氮化膜硬式遮罩(hard mask)呈柱狀地形成的矽(silicon)柱，並形成矽柱下部的擴散 層之後，堆積閘極材料，隨後對閘極材料進行平坦化並回蝕(etch back)，於矽柱與氮化膜硬式遮罩的側壁形成絕緣膜側牆(side wall)。隨後，形成用於閘極配線的抗蝕劑圖案(resist pattern)，對閘極材料進行蝕刻(etching)之後，去除氮化膜硬式遮罩，並於矽柱上部形成擴散層(例如參照專利文獻4)。 In the prior SGT manufacturing method, a nitride film formed by a hard mask of a nitride film in a columnar shape is formed, and diffusion of a lower portion of the mast is formed. After the layer, the gate material is deposited, and then the gate material is planarized and etched back, and an insulating film sidewall is formed on the sidewalls of the pillar and the nitride film hard mask. Subsequently, a resist pattern for the gate wiring is formed, after the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on the upper portion of the mast (for example, refer to the patent document 4).
此種方法中，當矽柱間隔變窄時，必須將厚的閘極材料 堆積於矽柱間，有時會於矽柱間形成被稱作空隙(void)的孔。當形成空隙時，在回蝕後於閘極材料中會出現孔。隨後為了形成絕緣膜側牆而堆積絕緣膜時，絕緣膜會堆積於空隙內。因而，閘極材料加工困難。 In this method, when the column spacing is narrowed, a thick gate material must be used. Stacked between the columns, sometimes a hole called a void is formed between the columns. When voids are formed, holes are formed in the gate material after etch back. Subsequently, when an insulating film is deposited in order to form the insulating film spacer, the insulating film is deposited in the gap. Therefore, the gate material processing is difficult.
因此，提出有一種方法：於矽柱形成後，形成閘極氧化 膜，堆積薄的多晶矽後，形成覆蓋矽柱上部並用於形成閘極配線的抗蝕劑，對閘極配線進行蝕刻，隨後，堆積厚的氧化膜，使矽柱上部露出，將矽柱上部的薄的多晶矽去除，並藉由濕式蝕刻(wet etching)來去除厚的氧化膜(例如參照非專利文獻1)。 Therefore, a method has been proposed to form gate oxidation after the formation of the column After depositing a thin polycrystalline germanium, a resist covering the upper portion of the mast and used to form the gate wiring is formed, and the gate wiring is etched, and then a thick oxide film is deposited to expose the upper portion of the mast, and the upper portion of the mast is exposed. The thin polycrystalline silicon is removed, and a thick oxide film is removed by wet etching (for example, refer to Non-Patent Document 1).
然而，並未提出用於對閘極電極使用金屬的方法。而 且，必須形成覆蓋矽柱上部並用於形成閘極配線的抗蝕劑，因而，必須覆蓋矽柱上部而非自對準製程(self-alignment process)。 However, a method for using a metal for a gate electrode has not been proposed. and Also, it is necessary to form a resist covering the upper portion of the mast and for forming the gate wiring, and therefore, it is necessary to cover the upper portion of the mast instead of the self-alignment process.
現有技術文獻 Prior art literature
專利文獻 Patent literature
專利文獻1：日本專利特開平2-71556號公報 Patent Document 1: Japanese Patent Laid-Open No. 2-71556
專利文獻2：日本專利特開平2-188966號公報 Patent Document 2: Japanese Patent Laid-Open No. Hei 2-188966
專利文獻3：日本專利特開平3-145761號公報 Patent Document 3: Japanese Patent Laid-Open No. Hei 3-145761
專利文獻4：日本專利特開2009-182317號公報 Patent Document 4: Japanese Patent Laid-Open Publication No. 2009-182317
非專利文獻 Non-patent literature
非專利文獻1：B.Yang,K.D.Buddharaju,S.H.G.Teo,N.Singh,G.D.Lo及D.L.Kwong,「垂直矽奈米線結構以及環繞閘極MOSFET(Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET)」,IEEE電子元件快報(IEEE Electron Device Letters),VOL.29,NO.7,2008年7月,pp791-794. Non-Patent Document 1: B. Yang, KDBuddharaju, SHGTeo, N. Singh, GDLo, and DL Kwong, "Vertical - Nanowire Structure and Circumpolar MOSFET (Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET) ), IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp 791-794.
因此，本發明的目的在於提供一種使用薄的閘極材、為金屬閘極且為自對準製程的SGT的製造方法與最終獲得的SGT的結構。 Accordingly, it is an object of the present invention to provide a method of manufacturing an SGT using a thin gate material, a metal gate, and a self-aligned process, and a structure of the finally obtained SGT.
本發明的第1觀點的半導體裝置的製造方法的特徵在於包括：第1步驟，於矽基板上形成平面狀矽層，並於上述平面狀矽層上形成第1柱狀矽層與第2柱狀矽層；第2步驟，於上述第1步驟之後，於上述第1柱狀矽層與上述第2柱狀矽層的周圍形成閘極絕緣膜，於上述閘極絕緣膜的周圍使金屬膜及多晶矽膜成膜，上述多晶矽膜的膜厚薄於上述第1柱狀矽層與上述第2柱狀 矽層之間的間隔的一半，形成用於形成閘極配線的第3抗蝕劑，藉由進行異向性蝕刻，從而形成上述閘極配線；以及第3步驟，於上述第2步驟之後，堆積第4抗蝕劑，使上述第1柱狀矽層與上述第2柱狀矽層上部側壁的上述多晶矽膜露出，藉由蝕刻來去除露出的上述多晶矽膜，剝離上述第4抗蝕劑，藉由蝕刻來去除上述金屬膜，從而形成連接於上述閘極配線的第1閘極電極與第2閘極電極。 A method of manufacturing a semiconductor device according to a first aspect of the present invention, characterized in that, in the first step, a planar germanium layer is formed on a germanium substrate, and a first columnar tantalum layer and a second pillar are formed on the planar germanium layer In the second step, after the first step, a gate insulating film is formed around the first columnar layer and the second columnar layer, and a metal film is formed around the gate insulating film. And forming a polycrystalline germanium film, wherein the thickness of the polysilicon film is thinner than the first columnar layer and the second column A third resist for forming a gate wiring is formed in half of the interval between the germanium layers, and the gate wiring is formed by performing anisotropic etching; and a third step, after the second step, Depositing the fourth resist, exposing the polycrystalline germanium film on the first columnar layer and the upper side wall of the second columnar layer, removing the exposed polysilicon film by etching, and peeling off the fourth resist The metal film is removed by etching to form a first gate electrode and a second gate electrode connected to the gate wiring.
而且，本發明的半導體裝置的製造方法中，藉由上述異向性蝕刻，上述第1柱狀矽層與上述第2柱狀矽層上部受到蝕刻。 Further, in the method of manufacturing a semiconductor device of the present invention, the first columnar layer and the second columnar layer are etched by the anisotropic etching.
而且，本發明的半導體裝置的製造方法中，用於形成上述閘極配線的上述第3抗蝕劑的上表面的高度，低於上述第1柱狀矽層與上述第2柱狀矽層上部的上述多晶矽膜的上表面的高度。 Further, in the method of manufacturing a semiconductor device of the present invention, the height of the upper surface of the third resist for forming the gate wiring is lower than the height of the first columnar layer and the second columnar layer The height of the upper surface of the above polysilicon film.
本發明的半導體裝置的製造方法更包括：第4步驟，於上述第1柱狀矽層的上部形成第1 n型擴散層，於上述第1柱狀矽層的下部與上述平面狀矽層的上部形成第2 n型擴散層，於上述第2柱狀矽層的上部形成第1 p型擴散層，於上述第2柱狀矽層的下部與上述平面狀矽層的上部形成第2 p型擴散層。 The method for fabricating a semiconductor device according to the present invention further includes a fourth step of forming a first n-type diffusion layer on an upper portion of the first columnar layer, and a lower portion of the first columnar layer and the planar layer a second n-type diffusion layer is formed on the upper portion, a first p-type diffusion layer is formed on the upper portion of the second columnar layer, and a second p-type is formed on a lower portion of the second columnar layer and the upper portion of the planar layer Diffusion layer.
本發明的半導體裝置的製造方法更包括：第5步驟，於上述第1 n型擴散層上、上述第2 n型擴散層上、 上述第1 p型擴散層、上述第2 p型擴散層上、與上述閘極配線形成矽化物。 The method of manufacturing a semiconductor device according to the present invention further includes a fifth step of: forming the first n-type diffusion layer on the second n-type diffusion layer; The first p-type diffusion layer and the second p-type diffusion layer form a telluride on the gate wiring.
而且，本發明的第2觀點的半導體裝置的特徵在於包括：平面狀矽層，形成於矽基板上；第1柱狀矽層及第2柱狀矽層，形成於上述平面狀矽層上；閘極絕緣膜，形成於上述第1柱狀矽層的周圍；第1閘極電極，包含金屬膜及多晶矽膜的積層結構，上述金屬膜及多晶矽膜形成於上述閘極絕緣膜的周圍；閘極絕緣膜，形成於上述第2柱狀矽層的周圍；第2閘極電極，包含金屬膜及多晶矽膜的積層結構，上述金屬膜及多晶矽膜形成於上述閘極絕緣膜的周圍，且上述多晶矽膜的膜厚薄於上述第1柱狀矽層與上述第2柱狀矽層之間的間隔的一半；閘極配線，連接於上述第1閘極電極及上述第2閘極電極，上述閘極配線的上表面的高度低於上述第1閘極電極及第2閘極電極的上表面的高度；第1 n型擴散層，形成於上述第1柱狀矽層的上部；第2 n型擴散層，形成於上述第1柱狀矽層的下部與上述平面狀矽層的上部；第1 p型擴散層，形成於上述第2柱狀矽層的上部；以及第2 p型擴散層，形成於上述第2柱狀矽層的下部與上述平面狀矽層的上部。 Further, a semiconductor device according to a second aspect of the present invention includes: a planar germanium layer formed on a germanium substrate; and a first columnar tantalum layer and a second columnar tantalum layer formed on the planar tantalum layer; a gate insulating film is formed around the first columnar layer; the first gate electrode includes a laminated structure of a metal film and a polysilicon film, and the metal film and the polysilicon film are formed around the gate insulating film; a pole insulating film is formed around the second columnar layer; the second gate electrode includes a laminated structure of a metal film and a polysilicon film, and the metal film and the polysilicon film are formed around the gate insulating film, and the above The thickness of the polysilicon film is thinner than half of the interval between the first columnar layer and the second columnar layer; the gate line is connected to the first gate electrode and the second gate electrode, and the gate is The height of the upper surface of the pole wiring is lower than the height of the upper surfaces of the first gate electrode and the second gate electrode; the first n-type diffusion layer is formed on the upper portion of the first columnar layer; the second n-type a diffusion layer formed on the first columnar layer a lower portion and an upper portion of the planar ruthenium layer; a first p-type diffusion layer formed on an upper portion of the second columnar ruthenium layer; and a second p-type diffusion layer formed on a lower portion of the second columnar ruthenium layer and The upper part of the planar enamel layer.
而且，本發明的半導體裝置中，上述閘極配線包含上述金屬膜與矽化物的積層結構。 Further, in the semiconductor device of the present invention, the gate wiring includes a laminated structure of the metal film and a germanide.
而且，本發明的半導體裝置中，於上述第1 n型擴散層側壁形成的絕緣膜側牆的膜厚，厚於上述金屬膜及多晶矽膜的膜厚之和。 Further, in the semiconductor device of the present invention, the thickness of the insulating film spacer formed on the sidewall of the first n-type diffusion layer is thicker than the sum of the thicknesses of the metal film and the polysilicon film.
而且，本發明的半導體裝置中，上述閘極配線的中心線相對於連結上述第1柱狀矽層的中心點與上述第2柱狀矽層的中心點的線，而偏移第1規定量。 Further, in the semiconductor device of the present invention, the center line of the gate wiring is shifted by the first predetermined amount with respect to a line connecting the center point of the first columnar layer and the center point of the second columnar layer. .
而且，本發明的半導體裝置包括：矽化物，形成於上述第1 n型擴散層及上述第2 n型擴散層上與上述第1 p型擴散層及上述第2 p型擴散層。 Further, the semiconductor device of the present invention includes: a telluride formed on the first n-type diffusion layer and the second n-type diffusion layer, the first p-type diffusion layer, and the second p-type diffusion layer.
根據本發明，可提供使用薄的閘極材、為金屬閘極且為自對準製程的SGT的製造方法與最終獲得的SGT的結構。 According to the present invention, it is possible to provide a method of manufacturing a SGT using a thin gate material, a metal gate, and a self-aligned process, and a structure of the finally obtained SGT.
藉由將第1柱狀矽層與第2柱狀矽層的高度設為所需的柱狀矽層高度、與隨後在閘極配線蝕刻中削除的高度之和，從而實現自對準製程。 The self-alignment process is realized by setting the heights of the first columnar layer and the second columnar layer to the sum of the desired columnar layer height and the height which is subsequently removed in the gate wiring etching.
而且，藉由第2步驟與第3步驟而實現自對準製程，上述第2步驟為：於上述第1柱狀矽層與上述第2柱狀矽層的周圍形成閘極絕緣膜，於上述閘極絕緣膜的周圍使金屬膜及多晶矽膜成膜， 上述多晶矽膜的膜厚薄於上述第1柱狀矽層與上述第2柱狀矽層之間的間隔的一半，形成用於形成閘極配線的第3抗蝕劑，藉由進行異向性蝕刻，從而形成上述閘極配線；上述第3步驟為：於上述第2步驟之後，堆積第4抗蝕劑，使上述第1柱狀矽層與上述第2柱狀矽層上部側壁的上述多晶矽膜露出，藉由蝕刻來去除露出的上述多晶矽膜，剝離上述第4抗蝕劑，藉由蝕刻來去除上述金屬膜，從而形成連接於上述閘極配線的第1閘極電極與第2閘極電極。 Further, the self-alignment process is performed by the second step and the third step, and the second step is to form a gate insulating film around the first columnar layer and the second columnar layer, The metal film and the polysilicon film are formed around the gate insulating film. The film thickness of the polysilicon film is thinner than half of the interval between the first columnar layer and the second columnar layer, and a third resist for forming a gate wiring is formed by anisotropic etching. The third step is to deposit a fourth resist after the second step to form the polycrystalline germanium film on the first columnar layer and the upper side wall of the second columnar layer Exposed, the exposed polysilicon film is removed by etching, the fourth resist is peeled off, and the metal film is removed by etching to form a first gate electrode and a second gate electrode connected to the gate line .
由於為自對準製程，因此高積體化成為可能。 Due to the self-aligned process, high integration is possible.
而且，上述閘極配線包含上述金屬膜與矽化物的積層結構。由於矽化物與金屬膜直接接觸，因此可實現低電阻化。 Further, the gate wiring includes a laminated structure of the metal film and the germanide. Since the telluride is in direct contact with the metal film, low resistance can be achieved.
於上述第1 n型擴散層側壁形成的絕緣膜側牆的膜厚，厚於上述金屬膜及多晶矽膜的膜厚之和。 The thickness of the insulating film spacer formed on the sidewall of the first n-type diffusion layer is thicker than the sum of the thicknesses of the metal film and the polysilicon film.
當用於形成接觸孔的抗蝕劑發生偏移且接觸(contact)孔蝕刻成為過蝕刻(over etch)時，可防止接觸部與閘極電極的短路。 When the resist for forming the contact hole is shifted and the contact hole is etched to be over etched, the short circuit between the contact portion and the gate electrode can be prevented.
上述閘極配線的中心線相對於連結上述第1柱狀矽層的中心點與上述第2柱狀矽層的中心點的線，而偏移第1規定量。 The center line of the gate wiring is shifted by a first predetermined amount with respect to a line connecting the center point of the first columnar layer and the center point of the second columnar layer.
容易形成連接第2 n型擴散層與第2 p型擴散層的矽化物。因而，可進行高積體化。 It is easy to form a telluride that connects the second n-type diffusion layer and the second p-type diffusion layer. Therefore, high integration can be performed.
101‧‧‧矽基板 101‧‧‧矽 substrate
102、103‧‧‧第1抗蝕劑 102, 103‧‧‧1st resist
104‧‧‧第1柱狀矽層 104‧‧‧1st columnar layer
105‧‧‧第2柱狀矽層 105‧‧‧2nd columnar layer
106‧‧‧第2抗蝕劑 106‧‧‧2nd resist
107‧‧‧平面狀矽層 107‧‧‧planar layer
108‧‧‧元件分離膜 108‧‧‧Component separation membrane
109‧‧‧閘極絕緣膜 109‧‧‧Gate insulation film
110、110a、110b、110c‧‧‧金屬膜 110, 110a, 110b, 110c‧‧‧ metal film
111、111a、111b‧‧‧多晶矽膜 111, 111a, 111b‧‧‧ polysilicon film
111c‧‧‧多晶矽膜配線 111c‧‧‧Polysilicon film wiring
112‧‧‧第3抗蝕劑 112‧‧‧3rd resist
113‧‧‧第4抗蝕劑 113‧‧‧4th resist
114a‧‧‧第2閘極電極 114a‧‧‧2nd gate electrode
114b‧‧‧第1閘極電極 114b‧‧‧1st gate electrode
114c‧‧‧閘極配線 114c‧‧‧gate wiring
115‧‧‧氧化膜 115‧‧‧Oxide film
116‧‧‧第5抗蝕劑 116‧‧‧5th resist
117‧‧‧第1 n型擴散層 117‧‧‧1 n-type diffusion layer
118‧‧‧第2 n型擴散層 118‧‧‧2nd n-type diffusion layer
119‧‧‧第6抗蝕劑 119‧‧‧6th resist
120‧‧‧第1 p型擴散層 120‧‧‧1st p-type diffusion layer
121‧‧‧第2 p型擴散層 121‧‧‧2nd p-type diffusion layer
122‧‧‧氮化膜 122‧‧‧ nitride film
123、124、125‧‧‧氮化膜側牆 123, 124, 125‧‧‧ nitride film side wall
126、127、128‧‧‧氧化膜側牆 126, 127, 128‧‧‧ oxide film side wall
129、130、131、132‧‧‧絕緣膜側牆 129, 130, 131, 132‧‧‧ insulating film side wall
133、134、135、136、137、138‧‧‧矽化物 133, 134, 135, 136, 137, 138‧‧‧ Telluride
139‧‧‧接觸阻擋層 139‧‧‧Contact barrier
140‧‧‧層間絕緣膜 140‧‧‧Interlayer insulating film
141‧‧‧第7抗蝕劑 141‧‧‧7th resist
142、143、145、146‧‧‧接觸孔 142, 143, 145, 146‧ ‧ contact holes
147、148、149、150‧‧‧接觸部 147, 148, 149, 150‧ ‧ contact
144‧‧‧第8抗蝕劑 144‧‧‧8th resist
151‧‧‧金屬 151‧‧‧Metal
152、153、154、155‧‧‧第9抗蝕劑 152, 153, 154, 155 ‧ ‧ 9th resist
156、157、158、159‧‧‧金屬配線 156, 157, 158, 159‧‧‧ metal wiring
圖1的(A)是本發明的實施方式的半導體裝置的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 Fig. 1(A) is a plan view showing a semiconductor device according to an embodiment of the present invention. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖2的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 2 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖3的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 3 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖4的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 4 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖5的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 5 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖6的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 6 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖7的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y' 線上的剖面圖。 (A) of FIG. 7 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is Y-Y' of (A) Sectional view on the line.
圖8的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 8 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖9的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 9 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖10的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 10 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖11的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 11 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖12的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 12 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖13的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 13 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖14的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 14 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖15的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 15 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖16的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 16 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖17的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 17 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖18的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 18 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖19的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 19 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖20的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 20 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖21的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 21 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖22的(A)是表示本實施方式的半導體裝置的製造方法的 平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 22 is a view showing a method of manufacturing the semiconductor device of the present embodiment. Floor plan. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖23的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 23 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖24的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 24 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖25的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 25 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖26的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 26 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖27的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 27 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖28的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 28 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖29的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y' 線上的剖面圖。 (A) of FIG. 29 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is Y-Y' of (A) Sectional view on the line.
圖30的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 30 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖31的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 31 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖32的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 32 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖33的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 33 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖34的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 34 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖35的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 35 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖36的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 36 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖37的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 37 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖38的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 38 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖39的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 39 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
圖40的(A)是表示本實施方式的半導體裝置的製造方法的平面圖。(B)是(A)的X-X'線上的剖面圖。(C)是(A)的Y-Y'線上的剖面圖。 (A) of FIG. 40 is a plan view showing a method of manufacturing the semiconductor device of the present embodiment. (B) is a cross-sectional view on the X-X' line of (A). (C) is a cross-sectional view on the Y-Y' line of (A).
以下，參照圖2的(A)、(B)、(C)~圖40的(A)、(B)、(C)，對本發明的實施方式的具有SGT結構的半導體裝置的製造步驟進行說明。 Hereinafter, a manufacturing procedure of a semiconductor device having an SGT structure according to an embodiment of the present invention will be described with reference to (A), (B), and (C) of FIG. 2 to (A), (B), and (C) of FIG. .
以下，表示第1步驟，即：於矽基板101上形成平面狀矽層107，並於平面狀矽層107上形成第1柱狀矽層104與第2柱狀矽層105。 Hereinafter, a first step of forming a planar tantalum layer 107 on the tantalum substrate 101 and forming a first columnar tantalum layer 104 and a second columnar tantalum layer 105 on the planar tantalum layer 107 will be described.
首先，如圖2的(A)、(B)、(C)所示，於矽基板101上形成第1抗蝕劑102、103，該第1抗蝕劑102、103用於形成第1柱狀矽層104與第2柱狀矽層105。 First, as shown in FIGS. 2(A), (B), and (C), first resists 102 and 103 are formed on the germanium substrate 101, and the first resists 102 and 103 are used to form the first pillars. The layer 104 and the second columnar layer 105.
繼而，如圖3的(A)、(B)、(C)所示，對矽基板101進行蝕刻，形成第1柱狀矽層104與第2柱狀矽層105。較為理想的是，第1柱狀矽層104與第2柱狀矽層105的高度是設為所需的柱狀矽層高度與隨後在閘極配線蝕刻中削除的高度之和。 Then, as shown in FIGS. 3(A), (B), and (C), the ruthenium substrate 101 is etched to form the first columnar layer 104 and the second columnar layer 105. Preferably, the height of the first columnar layer 104 and the second columnar layer 105 is the sum of the height of the columnar layer required and the height which is subsequently removed in the gate wiring etching.
繼而，如圖4的(A)、(B)、(C)所示，剝離第1抗蝕劑102、103。 Then, as shown in (A), (B), and (C) of FIG. 4, the first resists 102 and 103 are peeled off.
繼而，如圖5的(A)、(B)、(C)所示，形成用於形成平面狀矽層107的第2抗蝕劑106。 Then, as shown in (A), (B), and (C) of FIG. 5, the second resist 106 for forming the planar germanium layer 107 is formed.
繼而，如圖6的(A)、(B)、(C)所示，對矽基板101進行蝕刻，以形成平面狀矽層107。 Then, as shown in (A), (B), and (C) of FIG. 6, the germanium substrate 101 is etched to form a planar germanium layer 107.
繼而，如圖7的(A)、(B)、(C)所示，剝離第2抗蝕劑106。 Then, as shown in (A), (B), and (C) of FIG. 7, the second resist 106 is peeled off.
繼而，如圖8的(A)、(B)、(C)所示，於平面狀矽層107的周圍形成元件分離膜108。 Then, as shown in (A), (B), and (C) of FIG. 8, the element isolation film 108 is formed around the planar ruthenium layer 107.
藉由以上內容而示出第1步驟，即：於矽基板101上形成平面狀矽層107，並於平面狀矽層107上形成第1柱狀矽層104與第2柱狀矽層105。 The first step is the above, that is, the planar ruthenium layer 107 is formed on the ruthenium substrate 101, and the first columnar ruthenium layer 104 and the second columnar ruthenium layer 105 are formed on the planar ruthenium layer 107.
繼而，表示第2步驟，即：於上述第1柱狀矽層104與上述第2柱狀矽層105的周圍形成閘極絕緣膜109，於上述閘極絕緣膜109的周圍，使金屬膜110及多晶矽膜111成膜， 上述多晶矽膜111的膜厚薄於上述第1柱狀矽層104與上述第2柱狀矽層105之間的間隔的一半，形成用於形成閘極配線114c的第3抗蝕劑112，藉由進行異向性蝕刻，從而形成上述閘極配線114c。繼而，如圖9的(A)、(B)、(C)所示，於上述第1柱狀矽層104與上述第2柱狀矽層105的周圍，形成閘極絕緣膜109，於上述閘極絕緣膜109的周圍，使金屬膜110及多晶矽膜111成膜。此時，使用薄的多晶矽膜。因而，可防止於多晶矽膜中形成空隙。 In the second step, a gate insulating film 109 is formed around the first columnar layer 104 and the second columnar layer 105, and the metal film 110 is formed around the gate insulating film 109. And the polysilicon film 111 is formed into a film, The thickness of the polysilicon film 111 is thinner than half of the interval between the first columnar layer 104 and the second columnar layer 105, and the third resist 112 for forming the gate line 114c is formed by Anisotropic etching is performed to form the above-described gate wiring 114c. Then, as shown in FIGS. 9A (A), (B), and (C), a gate insulating film 109 is formed around the first columnar layer 104 and the second columnar layer 105. The metal film 110 and the polysilicon film 111 are formed around the gate insulating film 109. At this time, a thin polycrystalline germanium film was used. Thus, voids can be prevented from being formed in the polysilicon film.
金屬膜110只要是氮化鈦等被用於半導體步驟且設定電晶體的臨限值電壓的金屬即可。 The metal film 110 may be a metal that is used in a semiconductor step such as titanium nitride and that sets a threshold voltage of the transistor.
閘極絕緣膜109只要是氧化膜、氮氧化膜、高介電質膜等被用於半導體步驟的膜即可。 The gate insulating film 109 may be a film used for a semiconductor step, such as an oxide film, an oxynitride film, or a high dielectric film.
繼而，如圖10的(A)、(B)、(C)所示，形成用於形成閘極配線114c的第3抗蝕劑112。於本實施例中，以抗蝕劑高度低於柱狀矽層的方式進行記載。考慮其原因在於：當柱狀矽層的高度高時，柱狀矽層上部的抗蝕劑厚度變薄，或者，柱狀矽層上部的多晶矽會露出。隨著閘極配線寬度變細，柱狀矽層上部的多晶矽變得容易露出。 Then, as shown in (A), (B), and (C) of FIG. 10, the third resist 112 for forming the gate wiring 114c is formed. In the present embodiment, the description is made such that the resist height is lower than the columnar layer. The reason for this is considered to be that when the height of the columnar layer is high, the thickness of the resist on the upper portion of the columnar layer is thin, or the polysilicon in the upper portion of the columnar layer is exposed. As the width of the gate wiring becomes thinner, the polysilicon in the upper portion of the columnar layer is easily exposed.
抗蝕劑高度亦可高於柱狀矽層。 The resist height can also be higher than the columnar layer.
而且，此時，較佳的是，以用於閘極配線的第3抗蝕劑112的中心線相對於連結第1柱狀矽層104的中心點與第2柱狀矽 層105的中心點的線而偏移的方式，來形成第3抗蝕劑112。這是為了便於形成連接第2 n型擴散層118與第2 p型擴散層121的矽化物。 Further, in this case, it is preferable that the center line of the third resist 112 for the gate wiring is opposite to the center point and the second columnar line connecting the first columnar layer 104. The third resist 112 is formed in such a manner that the line of the center point of the layer 105 is shifted. This is for facilitating formation of a telluride that connects the second n-type diffusion layer 118 and the second p-type diffusion layer 121.
繼而，如圖11的(A)、(B)、(C)所示，對多晶矽膜111與金屬膜110進行蝕刻。 Then, as shown in (A), (B), and (C) of FIG. 11, the polysilicon film 111 and the metal film 110 are etched.
形成多晶矽膜111a、多晶矽膜111b、多晶矽膜配線111c。此時，若柱狀矽層上部的抗蝕劑厚度薄，或者柱狀矽層上部的多晶矽露出，則於蝕刻過程中，柱狀矽層上部有時會受到蝕刻。此時，只要在形成柱狀矽層時，將該柱狀矽層的高度設為所需的柱狀矽層高度與隨後在閘極配線蝕刻中削除的高度之和即可。因而，本發明的製造步驟成為自對準製程。 A polysilicon film 111a, a polysilicon film 111b, and a polysilicon film wiring 111c are formed. At this time, if the thickness of the resist on the upper portion of the columnar layer is thin or the polysilicon in the upper portion of the columnar layer is exposed, the upper portion of the columnar layer may be etched during the etching. At this time, as long as the columnar tantalum layer is formed, the height of the columnar tantalum layer may be set to the sum of the height of the desired columnar tantalum layer and the height which is subsequently removed in the gate wiring etching. Thus, the manufacturing steps of the present invention become a self-aligned process.
而且，由於隨後對金屬膜110進行蝕刻，因此亦可將本步驟設為多晶矽膜111的蝕刻。 Further, since the metal film 110 is subsequently etched, this step can also be performed as etching of the polysilicon film 111.
繼而，如圖12的(A)、(B)、(C)所示，剝離第3抗蝕劑112。 Then, as shown in (A), (B), and (C) of FIG. 12, the third resist 112 is peeled off.
藉由以上內容，示出第2步驟，即：於上述第1柱狀矽層104與上述第2柱狀矽層105的周圍形成閘極絕緣膜109，於上述閘極絕緣膜109的周圍，使金屬膜110及多晶矽膜111成膜，上述多晶矽膜111的膜厚薄於上述第1柱狀矽層104與上述第2柱狀矽層105之間的間隔的一半， 形成用於形成閘極配線114c的第3抗蝕劑112，藉由進行異向性蝕刻，從而形成上述閘極配線114c。 According to the above, the second step of forming the gate insulating film 109 around the first columnar layer 104 and the second columnar layer 105 is performed around the gate insulating film 109. The metal film 110 and the polysilicon film 111 are formed, and the thickness of the polysilicon film 111 is thinner than half the interval between the first columnar layer 104 and the second columnar layer 105. The third resist 112 for forming the gate wiring 114c is formed, and the gate wiring 114c is formed by performing anisotropic etching.
繼而，表示第3步驟，即：堆積第4抗蝕劑113，使上述第1柱狀矽層104與上述第2柱狀矽層105上部側壁的上述多晶矽膜111a、111b露出，藉由蝕刻來去除露出的上述多晶矽膜111a、111b，剝離上述第4抗蝕劑113，藉由蝕刻來去除上述金屬膜110，從而形成連接於上述閘極配線114c的第1閘極電極114b與第2閘極電極114a。 Then, in the third step, the fourth resist 113 is deposited, and the polycrystalline germanium films 111a and 111b on the upper side wall of the first columnar layer 104 and the second columnar layer 105 are exposed and etched. The exposed polysilicon films 111a and 111b are removed, the fourth resist 113 is peeled off, and the metal film 110 is removed by etching to form a first gate electrode 114b and a second gate connected to the gate line 114c. Electrode 114a.
如圖13的(A)、(B)、(C)所示，堆積第4抗蝕劑113，使上述第1柱狀矽層104與上述第2柱狀矽層105上部側壁的上述多晶矽膜111b、111a露出。較佳的是使用抗蝕劑回蝕。而且，亦可使用旋塗玻璃(spin-on-glass)等的塗佈膜。 As shown in (A), (B), and (C) of FIG. 13, the fourth resist 113 is deposited, and the polycrystalline tantalum film on the upper side wall of the first columnar layer 104 and the second columnar layer 105 is formed. 111b, 111a are exposed. It is preferred to use resist etch back. Further, a coating film of spin-on-glass or the like can also be used.
繼而，如圖14的(A)、(B)、(C)所示，藉由蝕刻來去除露出的上述多晶矽膜111a、111b。較佳的是等向性乾式蝕刻(dry etching)。 Then, as shown in (A), (B), and (C) of FIG. 14, the exposed polysilicon films 111a and 111b are removed by etching. Preferred is an isotropic dry etching.
繼而，如圖15的(A)、(B)、(C)所示，剝離第4抗蝕劑113。 Then, as shown in (A), (B), and (C) of FIG. 15, the fourth resist 113 is peeled off.
繼而，如圖16的(A)、(B)、(C)所示，藉由蝕刻來去除上述金屬膜110，從而在第1柱狀矽層104側壁形成金屬膜110b，在第2柱狀矽層105側壁形成金屬膜110a，在多晶矽膜配線111c下形成金屬膜110c。較佳的是等向性蝕刻。 Then, as shown in FIGS. 16(A), (B), and (C), the metal film 110 is removed by etching to form a metal film 110b on the sidewall of the first columnar layer 104, and is formed in the second columnar shape. A metal film 110a is formed on the sidewall of the germanium layer 105, and a metal film 110c is formed under the polysilicon film wiring 111c. An isotropic etching is preferred.
由金屬膜110b與多晶矽膜111b形成第1閘極電極114b， 由金屬膜110a與多晶矽膜111a形成第2閘極電極114a，由金屬膜110c與多晶矽膜配線111c形成閘極配線114c。因而，成為自對準製程。 The first gate electrode 114b is formed by the metal film 110b and the polysilicon film 111b, The second gate electrode 114a is formed by the metal film 110a and the polysilicon film 111a, and the gate wiring 114c is formed by the metal film 110c and the polysilicon film wiring 111c. Thus, it becomes a self-aligned process.
藉由以上內容，示出第3步驟，即：堆積第4抗蝕劑113，使上述第1柱狀矽層104與上述第2柱狀矽層105上部側壁的上述多晶矽膜111a、111b露出，藉由蝕刻來去除露出的上述多晶矽膜111a、111b，剝離上述第4抗蝕劑113，藉由蝕刻來去除上述金屬膜110，從而形成連接於上述閘極配線114c的第1閘極電極114b與第2閘極電極114a。 According to the above, the third step of depositing the fourth resist 113 exposes the polycrystalline germanium films 111a and 111b on the upper side wall of the first columnar layer 104 and the second columnar layer 105. The exposed polysilicon films 111a and 111b are removed by etching, the fourth resist 113 is peeled off, and the metal film 110 is removed by etching to form the first gate electrode 114b connected to the gate line 114c. The second gate electrode 114a.
繼而，表示第4步驟，即：於第1柱狀矽層104的上部形成第1 n型擴散層117，於第1柱狀矽層104的下部與平面狀矽層107的上部形成第2 n型擴散層118，於第2柱狀矽層105的上部形成第1 p型擴散層120，於第2柱狀矽層105的下部與平面狀矽層107的上部形成第2 p型擴散層121。 Next, the fourth step is shown in which the first n-type diffusion layer 117 is formed on the upper portion of the first columnar layer 104, and the second portion is formed on the lower portion of the first columnar layer 104 and the upper portion of the planar layer 107. In the type diffusion layer 118, the first p-type diffusion layer 120 is formed on the upper portion of the second columnar layer 105, and the second p-type diffusion layer 121 is formed on the lower portion of the second columnar layer 105 and the upper portion of the planar layer 107. .
如圖17的(A)、(B)、(C)所示，堆積氧化膜115。 As shown in (A), (B), and (C) of Fig. 17, an oxide film 115 is deposited.
繼而，如圖18的(A)、(B)、(C)所示，形成第5抗蝕劑116，該第5抗蝕劑116用於形成第1 n型擴散層117與第2 n型擴散層118。 Then, as shown in (A), (B), and (C) of FIG. 18, a fifth resist 116 for forming the first n-type diffusion layer 117 and the second n-type is formed. Diffusion layer 118.
繼而，如圖19的(A)、(B)、(C)所示，注入砷，形成第1 n型擴散層117與第2 n型擴散層118。 Then, as shown in (A), (B), and (C) of FIG. 19, arsenic is implanted to form the first n-type diffusion layer 117 and the second n-type diffusion layer 118.
繼而，如圖20的(A)、(B)、(C)所示，剝離第5抗 蝕劑116。 Then, as shown in (A), (B), and (C) of FIG. 20, the fifth antibody was peeled off. Etchant 116.
繼而，如圖21的(A)、(B)、(C)所示，形成第6抗 蝕劑119，該第6抗蝕劑119用於形成第1 p型擴散層120與第2 p型擴散層121。 Then, as shown in (A), (B), and (C) of FIG. 21, the sixth antibody is formed. The sixth resist 119 is used to form the first p-type diffusion layer 120 and the second p-type diffusion layer 121.
繼而，如圖22的(A)、(B)、(C)所示，注入硼或氟 化硼，形成第1 p型擴散層120與第2 p型擴散層121。 Then, as shown in (A), (B), and (C) of FIG. 22, boron or fluorine is implanted. Boron is formed to form the first p-type diffusion layer 120 and the second p-type diffusion layer 121.
繼而，如圖23的(A)、(B)、(C)所示，剝離第6抗 蝕劑119。 Then, as shown in (A), (B), and (C) of FIG. 23, the sixth antibody is peeled off. Etchant 119.
繼而，如圖24的(A)、(B)、(C)所示，堆積氮化膜 122，並進行熱處理。 Then, as shown in (A), (B), and (C) of FIG. 24, a nitride film is deposited. 122, and heat treatment.
藉由以上內容，示出第4步驟，即：於第1柱狀矽層104的上部形成第1 n型擴散層117，於第1柱狀矽層104的下部與平面狀矽層107的上部形成第2 n型擴散層118，於第2柱狀矽層105的上部形成第1 p型擴散層120，於第2柱狀矽層105的下部與平面狀矽層107的上部形成第2 p型擴散層121。 According to the above, the fourth step is to form the first n-type diffusion layer 117 on the upper portion of the first columnar layer 104, and the lower portion of the first columnar layer 104 and the upper portion of the planar layer 107. The second n-type diffusion layer 118 is formed, the first p-type diffusion layer 120 is formed on the upper portion of the second columnar layer 105, and the second p is formed on the lower portion of the second columnar layer 105 and the upper portion of the planar layer 107. Type diffusion layer 121.
繼而，表示第5步驟，即：於第1 n型擴散層117上、第2 n型擴散層118上、第1 p型擴散層120、第2 p型擴散層121上與閘極配線114c形成矽化物。 Then, the fifth step, that is, the first n-type diffusion layer 117, the second n-type diffusion layer 118, the first p-type diffusion layer 120, and the second p-type diffusion layer 121 are formed on the gate wiring 114c. Telluride.
如圖25的(A)、(B)、(C)所示，對氮化膜122進行 蝕刻，形成氮化膜側牆123、124、125。 As shown in (A), (B), and (C) of FIG. 25, the nitride film 122 is performed. Etching forms nitride film sidewalls 123, 124, 125.
繼而，如圖26的(A)、(B)、(C)所示，對氧化膜進行蝕刻，形成氧化膜側牆127、126、128。由氮化膜側牆123與氧化膜側牆127構成絕緣膜側牆129，由氮化膜側牆124與氧化膜側牆126構成絕緣膜側牆130，由第1柱狀矽層104側壁的氮化膜側牆125與氧化膜側牆128構成絕緣膜側牆131，由第2柱狀矽層105側壁的氮化膜側牆125與氧化膜側牆128構成絕緣膜側牆132。 Then, as shown in (A), (B), and (C) of FIG. 26, the oxide film is etched to form oxide film spacers 127, 126, and 128. The insulating film spacer 129 is formed by the nitride film spacer 123 and the oxide spacer sidewall 127, and the insulating film spacer 130 is formed by the nitride film spacer 124 and the oxide spacer sidewall 126, and is formed by the sidewall of the first columnar layer 104. The nitride film side wall 125 and the oxide film side wall 128 constitute an insulating film spacer 131, and the nitride film spacer 125 and the oxide film spacer 128 on the sidewall of the second columnar layer 105 constitute an insulating film spacer 132.
此時，較佳的是，於第1 n型擴散層117側壁形成的絕緣膜側牆129的膜厚，厚於金屬膜110b及多晶矽膜111b的膜厚之和。 At this time, it is preferable that the thickness of the insulating film spacer 129 formed on the sidewall of the first n-type diffusion layer 117 is thicker than the sum of the thicknesses of the metal film 110b and the polysilicon film 111b.
若於第1 n型擴散層117側壁形成的絕緣膜側牆129的膜厚，厚於金屬膜110b及多晶矽膜111b的膜厚之和，則於形成接觸部時，接觸部與閘極電極114b的絕緣變得容易。 When the thickness of the insulating film spacer 129 formed on the sidewall of the first n-type diffusion layer 117 is thicker than the sum of the thicknesses of the metal film 110b and the polysilicon film 111b, the contact portion and the gate electrode 114b are formed when the contact portion is formed. The insulation becomes easy.
繼而，如圖27的(A)、(B)、(C)所示，堆積金屬並進行熱處理，並去除未反應的金屬，藉此，於第1 n型擴散層117上、第2 n型擴散層118上、第1 p型擴散層120、第2 p型擴散層121上與閘極配線114c形成矽化物134、138、136、137、133、135。 Then, as shown in (A), (B), and (C) of FIG. 27, the metal is deposited and heat-treated, and the unreacted metal is removed, thereby forming the second n-type on the first n-type diffusion layer 117. On the diffusion layer 118, the first p-type diffusion layer 120 and the second p-type diffusion layer 121 form germanium 134, 138, 136, 137, 133, and 135 on the gate line 114c.
第2 n型擴散層118與第2 p型擴散層121將藉由矽化物138而連接。閘極配線114c的中心線相對於連結第1柱狀矽層104的中心點與第2柱狀矽層105的中心點的線而偏移，因此容易形成矽化物138。因而，可進行高積體化。 The second n-type diffusion layer 118 and the second p-type diffusion layer 121 are connected by a telluride 138. The center line of the gate wiring 114c is shifted with respect to the line connecting the center point of the first columnar layer 104 and the center point of the second columnar layer 105, so that the germanide 138 is easily formed. Therefore, high integration can be performed.
而且，由於多晶矽膜配線111c薄，因此閘極配線114c 容易成為金屬膜110c與矽化物133的積層結構。由於矽化物133與金屬膜110c直接接觸，因此可實現低電阻化。 Moreover, since the polysilicon film wiring 111c is thin, the gate wiring 114c It is easy to form a laminated structure of the metal film 110c and the telluride 133. Since the telluride 133 is in direct contact with the metal film 110c, it is possible to achieve low resistance.
藉由以上內容，示出第5步驟，即：於第1 n型擴散層 117上、第2 n型擴散層118上、第1 p型擴散層120、第2 p型擴散層121上與閘極配線114c形成矽化物。 From the above, the fifth step is shown, that is, the first n-type diffusion layer On the 117 upper and second n-type diffusion layers 118, the first p-type diffusion layer 120 and the second p-type diffusion layer 121 form a telluride with the gate wiring 114c.
繼而，如圖28的(A)、(B)、(C)所示，使氮化膜等 接觸阻擋層(contact stopper)139成膜，形成層間絕緣膜140。 Then, as shown in (A), (B), and (C) of FIG. 28, a nitride film or the like is formed. A contact stopper 139 is formed into a film to form an interlayer insulating film 140.
繼而，如圖29的(A)、(B)、(C)所示，形成用於形 成接觸孔142、143的第7抗蝕劑141。 Then, as shown in (A), (B), and (C) of FIG. 29, it is formed for the shape. The seventh resist 141 is formed as a contact hole 142, 143.
繼而，如圖30的(A)、(B)、(C)所示，對層間絕緣 膜140進行蝕刻，從而形成接觸孔142、143。若於第1 n型擴散層117側壁形成的絕緣膜側牆129的膜厚，厚於金屬膜110b及多晶矽膜111b的膜厚之和，則當第7抗蝕劑發生偏移且接觸孔蝕刻成為過蝕刻時，可防止接觸部與閘極電極114b的短路。 Then, as shown in (A), (B), and (C) of FIG. 30, the interlayer insulation is applied. The film 140 is etched to form contact holes 142, 143. If the film thickness of the insulating film spacer 129 formed on the sidewall of the first n-type diffusion layer 117 is thicker than the sum of the film thicknesses of the metal film 110b and the polysilicon film 111b, the seventh resist is offset and the contact hole is etched. When over-etching is performed, short-circuiting between the contact portion and the gate electrode 114b can be prevented.
繼而，如圖31的(A)、(B)、(C)所示，剝離第7抗 蝕劑141。 Then, as shown in (A), (B), and (C) of FIG. 31, the seventh antibody is peeled off. Etchant 141.
繼而，如圖32的(A)、(B)、(C)所示，形成用於形 成接觸孔145、146的第8抗蝕劑144。 Then, as shown in (A), (B), and (C) of FIG. 32, it is formed for the shape. The eighth resist 144 is formed in the contact holes 145, 146.
繼而，如圖33的(A)、(B)、(C)所示，對層間絕緣 膜140進行蝕刻，形成接觸孔145、146。 Then, as shown in (A), (B), and (C) of FIG. 33, the interlayer insulation is applied. The film 140 is etched to form contact holes 145, 146.
繼而，如圖34的(A)、(B)、(C)所示，剝離第8抗 蝕劑144。 Then, as shown in (A), (B), and (C) of FIG. 34, the eighth antibody was peeled off. Etchant 144.
繼而，如圖35的(A)、(B)、(C)所示，對接觸阻擋 層139進行蝕刻，去除接觸孔142、143、接觸孔145、146下的接觸阻擋層139。 Then, as shown in (A), (B), and (C) of FIG. 35, the contact is blocked. Layer 139 is etched to remove contact holes 142, 143, and contact barrier layer 139 under contact holes 145, 146.
繼而，如圖36的(A)、(B)、(C)所示，堆積金屬， 形成接觸部147、148、149、150。 Then, as shown in (A), (B), and (C) of FIG. 36, the metal is deposited, Contact portions 147, 148, 149, 150 are formed.
繼而，如圖37的(A)、(B)、(C)所示，堆積用於金 屬配線的金屬151。 Then, as shown in (A), (B), and (C) of FIG. 37, stacked for gold It is a metal 151 of wiring.
繼而，如圖38的(A)、(B)、(C)所示，形成用於形 成金屬配線的第9抗蝕劑152、153、154、155。 Then, as shown in (A), (B), and (C) of FIG. 38, it is formed for the shape. The ninth resists 152, 153, 154, and 155 of the metal wiring.
繼而，如圖39的(A)、(B)、(C)所示，對金屬151 進行蝕刻，形成金屬配線156、157、158、159。 Then, as shown in (A), (B), and (C) of FIG. 39, the metal 151 is applied. Etching is performed to form metal wirings 156, 157, 158, and 159.
繼而，如圖40的(A)、(B)、(C)所示，剝離第9抗 蝕劑152、153、154、155。 Then, as shown in (A), (B), and (C) of FIG. 40, the ninth antibody was peeled off. Etchants 152, 153, 154, 155.
藉由以上內容，示出使用薄的閘極材、為金屬閘極且 為自對準製程的SGT的製造方法。 From the above, it is shown that a thin gate material is used, which is a metal gate and It is a manufacturing method of SGT for self-aligned process.
圖1的(A)、(B)、(C)表示藉由上述製造方法而獲 得的半導體裝置的結構。 (A), (B), and (C) of FIG. 1 are obtained by the above manufacturing method. The structure of the resulting semiconductor device.
如圖1的(A)、(B)、(C)所示，半導體裝置包括：平面狀矽層107，形成於矽基板101上；第1柱狀矽層104及第2柱狀矽層105，形成於上述平面狀矽層107上； 閘極絕緣膜109，形成於上述第1柱狀矽層104的周圍；第1閘極電極114b，包含金屬膜110b及多晶矽膜111b的積層結構，該金屬膜110b及多晶矽膜111b形成於上述閘極絕緣膜109的周圍；閘極絕緣膜109，形成於上述第2柱狀矽層105的周圍；第2閘極電極114a，包含金屬膜110a及多晶矽膜111a的積層結構，該金屬膜110a及多晶矽膜111a形成於上述閘極絕緣膜109的周圍，且上述多晶矽膜111b、111a的膜厚薄於上述第1柱狀矽層104與上述第2柱狀矽層105之間的間隔的一半；閘極配線114c，連接於上述第1閘極電極114b及上述第2閘極電極114a，上述閘極配線114c的上表面的高度低於上述第1閘極電極114b及第2閘極電極114a的上表面的高度；第1 n型擴散層117，形成於上述第1柱狀矽層104的上部；第2 n型擴散層118，形成於上述第1柱狀矽層104的下部與上述平面狀矽層107的上部；第1 p型擴散層120，形成於上述第2柱狀矽層105的上部；以及第2 p型擴散層121，形成於上述第2柱狀矽層105的下部與上述平面狀矽層107的上部。 As shown in FIGS. 1(A), (B), and (C), the semiconductor device includes a planar germanium layer 107 formed on the germanium substrate 101, and a first columnar layer 104 and a second columnar layer 105. Formed on the planar crucible layer 107; The gate insulating film 109 is formed around the first columnar layer 104, and the first gate electrode 114b includes a laminated structure of a metal film 110b and a polysilicon film 111b. The metal film 110b and the polysilicon film 111b are formed on the gate. The gate insulating film 109 is formed around the second columnar layer 105; the second gate electrode 114a includes a laminated structure of the metal film 110a and the polysilicon film 111a, and the metal film 110a and The polysilicon film 111a is formed around the gate insulating film 109, and the thickness of the polysilicon films 111b and 111a is thinner than half of the interval between the first columnar layer 104 and the second columnar layer 105. The pole wiring 114c is connected to the first gate electrode 114b and the second gate electrode 114a, and the height of the upper surface of the gate wiring 114c is lower than that of the first gate electrode 114b and the second gate electrode 114a. a height of the surface; a first n-type diffusion layer 117 formed on an upper portion of the first columnar layer 104; and a second n-type diffusion layer 118 formed on a lower portion of the first columnar layer 104 and the planar germanium An upper portion of the layer 107; a first p-type diffusion layer 120 formed on the upper portion An upper portion of the second columnar silicon layer 105; and a second P-type diffusion layer 121 formed on a lower portion of the first columnar silicon layer 105 and an upper portion of the planar silicon layer 107.
而且，上述閘極配線114c包含上述金屬膜110c與矽 化物133的積層結構。由於矽化物133與金屬膜110c直接接觸，因此可實現低電阻化。 Further, the gate wiring 114c includes the above-described metal film 110c and 矽 The laminate structure of the compound 133. Since the telluride 133 is in direct contact with the metal film 110c, it is possible to achieve low resistance.
於上述第1 n型擴散層117側壁形成的絕緣膜側牆129的膜厚，厚於上述金屬膜110b及多晶矽膜111b的膜厚之和。 The thickness of the insulating film spacer 129 formed on the sidewall of the first n-type diffusion layer 117 is thicker than the sum of the thicknesses of the metal film 110b and the polysilicon film 111b.
當第7抗蝕劑發生偏移且接觸孔蝕刻成為過蝕刻時，可防止接觸部148與閘極電極114b的短路。 When the seventh resist is displaced and the contact hole is etched to be over-etched, short-circuiting between the contact portion 148 and the gate electrode 114b can be prevented.
上述閘極配線114c的中心線相對於連結上述第1柱狀矽層104的中心點與上述第2柱狀矽層105的中心點的線，而偏移第1規定量。 The center line of the gate wiring 114c is shifted by a first predetermined amount with respect to a line connecting the center point of the first columnar layer 104 and the center point of the second columnar layer 105.
容易形成連接第2 n型擴散層118與第2 p型擴散層121的矽化物138。因而，可進行高積體化。 The telluride 138 that connects the second n-type diffusion layer 118 and the second p-type diffusion layer 121 is easily formed. Therefore, high integration can be performed.
再者，本發明並不脫離其廣義的精神與範圍，可採用各種實施方式以及變形。而且，上述實施方式是用於說明本發明的一實施例，並不限定本發明的範圍。 Further, the present invention is not to be construed as being limited to Further, the above embodiment is for explaining an embodiment of the present invention, and does not limit the scope of the present invention.
例如，於上述實施例中，將p型(包括p+型)與n型(包括n+型)分別設為相反的導電型的半導體裝置的製造方法、以及藉由該方法獲得的半導體裝置當然亦包含於本發明的技術範圍內。 For example, in the above embodiment, a method of manufacturing a semiconductor device in which a p-type (including p + type) and an n-type (including n + type) are respectively opposite conductivity types, and a semiconductor device obtained by the method are of course It is also included in the technical scope of the present invention.
101‧‧‧矽基板 101‧‧‧矽 substrate
104‧‧‧第1柱狀矽層 104‧‧‧1st columnar layer
105‧‧‧第2柱狀矽層 105‧‧‧2nd columnar layer
107‧‧‧平面狀矽層 107‧‧‧planar layer
108‧‧‧元件分離膜 108‧‧‧Component separation membrane
109‧‧‧閘極絕緣膜 109‧‧‧Gate insulation film
110、110a、110b、110c‧‧‧金屬膜 110, 110a, 110b, 110c‧‧‧ metal film
111、111a、111b‧‧‧多晶矽膜 111, 111a, 111b‧‧‧ polysilicon film
114a‧‧‧第2閘極電極 114a‧‧‧2nd gate electrode
114b‧‧‧第1閘極電極 114b‧‧‧1st gate electrode
114c‧‧‧閘極配線 114c‧‧‧gate wiring
117‧‧‧第1 n型擴散層 117‧‧‧1 n-type diffusion layer
118‧‧‧第2 n型擴散層 118‧‧‧2nd n-type diffusion layer
120‧‧‧第1 p型擴散層 120‧‧‧1st p-type diffusion layer
121‧‧‧第2 p型擴散層 121‧‧‧2nd p-type diffusion layer
123、124、125‧‧‧氮化膜側牆 123, 124, 125‧‧‧ nitride film side wall
126、127、128‧‧‧氧化膜側牆 126, 127, 128‧‧‧ oxide film side wall
129、130、131、132‧‧‧絕緣膜側牆 129, 130, 131, 132‧‧‧ insulating film side wall
133、134、135、136、137‧‧‧矽化物 133, 134, 135, 136, 137‧‧‧ Telluride
139‧‧‧接觸阻擋層 139‧‧‧Contact barrier
140‧‧‧層間絕緣膜 140‧‧‧Interlayer insulating film
147、148、149、150‧‧‧接觸部 147, 148, 149, 150‧ ‧ contact
151‧‧‧金屬 151‧‧‧Metal
156、157、158、159‧‧‧金屬配線 156, 157, 158, 159‧‧‧ metal wiring
Claims (10)
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| PCT/JP2012/064760 WO2013183158A1 (en) | 2012-06-08 | 2012-06-08 | Semiconductor device manufacturing method, and semiconductor device |
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