TW201419548A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

A method for manufacturing semiconductor device is provided, including a first step of forming a fin-shaped silicon layer on a silicon substrate by using a first resist, and forming a first insulating film in the periphery of the fin-shaped silicon layer; and a second step of forming a second insulating film in the periphery of the fin-shaped silicon layer, etching the second insulating film such that the remnant of the second insulating film exists on a side wall of the fin-shaped silicon layer, accumulating a third insulating film on the second insulating film, the fin-shaped silicon layer and the first insulating film, then forming a second resist for forming a gate wiring and a columnar silicon layer along a direction perpendicular to a direction that the fin-shaped silicon layer extends, etching the second insulating film, the third insulating film and the fin-shaped silicon layer by using the second resist, and removing the second insulating film, thereby forming a columnar silicon layer and a dummy gate including the third insulating film.

Description

Semiconductor device manufacturing method and semiconductor device

The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.

A semiconductor integrated circuit, in particular, an integrated circuit using a metal oxide semiconductor (MOS) transistor is tending to be highly integrated. Along with such high integration, the MOS transistor used in the integrated circuit has been miniaturized to the field of nano.

When the miniaturization of such an MOS transistor is developed, it is difficult to suppress the leakage current, and it is difficult to reduce the occupied area of the circuit by securing the required amount of current.

In this regard, a surrounding gate transistor (hereinafter referred to as "SGT (Surrounding Gate Transistor)") having a structure in which a source and a gate are arranged in a vertical direction with respect to a substrate is proposed. A structure in which a gate electrode surrounds a columnar semiconductor layer (silicon column) (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

Previously, the SGT was manufactured by using a first mask for drawing a mast to form a hard mask having a nitride film formed in a columnar shape. a column, and then, by using a second mask for drawing a planar germanium layer, a planar germanium layer is formed on the bottom of the mast, and further, by using a third mask for drawing the gate wiring Thus, a gate wiring is formed (for example, refer to Patent Document 4).

That is, the mast, the planar tantalum layer, and the gate wiring are formed by using three masks.

Further, in the above-described manufacturing method of the SGT, since the depth of the contact is different, it is necessary to form a contact hole between the contact hole on the upper portion of the mast and the flat layer on the lower portion of the mast (for example, see Patent Document 5). Since the contact holes are formed separately in this way, the number of steps required for manufacturing will increase.

Further, in order to reduce the parasitic capacitance between the gate wiring and the substrate, the first insulating film is used for the MOS transistor. For example, in a Fin Field-Effect Transistor (FINFET) (see, for example, Non-Patent Document 1), a first insulating film is formed around a fin-shaped semiconductor layer, and the first insulating film is formed. The insulating film is etched back to expose the fin-shaped semiconductor layer, thereby reducing the parasitic capacitance between the gate wiring and the substrate. Therefore, in the SGT, in order to reduce the parasitic capacitance between the gate wiring and the substrate, it is necessary to use the first insulating film. In the SGT, in addition to the fin-shaped semiconductor layer, a columnar semiconductor layer is present, and therefore a method for forming the columnar semiconductor layer is required.

Prior art literature

Patent literature

Patent Document 1: Japanese Patent Laid-Open No. 2-71556

Patent Document 2: Japanese Patent Laid-Open No. Hei 2-188966

Patent Document 3: Japanese Patent Laid-Open No. Hei 3-145761

Patent Document 4: Japanese Patent Laid-Open Publication No. 2009-182317

Patent Document 5: Japanese Patent Laid-Open Publication No. 2012-004244

Non-patent literature

Non-Patent Document 1: High performance 22/20 nm FinFET CMOS devices with advanced high-K/metal gate scheme with advanced high dielectric constant/metal gate design , International Electronic Components Conference (IEDM) 2010CC.Wu, etc., 27.1.1-27.1.4.

Accordingly, an object of the present invention is to provide a method for manufacturing an SGT capable of reducing the number of steps required to manufacture an SGT, and a configuration of an SGT obtained by the method for manufacturing the SGT.

In the method of manufacturing a semiconductor device according to the first aspect of the invention, the semiconductor device includes: a fin-shaped germanium layer formed on the germanium substrate; a first insulating film formed around the fin-shaped germanium layer; and a columnar germanium layer; Formed on the finned layer; the gate insulating film is formed around the columnar layer; a gate electrode formed around the gate insulating film; and a gate wiring connected to the gate electrode and extending in a second direction orthogonal to a first direction in which the fin-shaped germanium layer extends, the semiconductor In the method of manufacturing a device, the fin layer is formed using a first mask, and the columnar layer and the gate line are formed using a second mask.

A method of manufacturing a semiconductor device according to a second aspect of the present invention includes the first step of forming a fin-shaped germanium layer on a germanium substrate by using a first mask, and forming a first insulating layer around the fin-shaped germanium layer a second step of forming a second insulating film around the finned layer and etching the second insulating film to leave the second insulating film on the sidewall of the fin layer The third insulating film is deposited on the second insulating film, on the fin-shaped germanium layer, and on the first insulating film, and extends in a second direction orthogonal to a first direction in which the fin-shaped germanium layer extends. In the method, a resist for forming a gate wiring and a columnar layer is formed, and after the resist is used as a second mask, the second insulating film and the third insulating film are etched. The fin layer is etched to remove the second insulating film, thereby forming the columnar layer and a dummy gate including the third insulating film.

Preferably, the etching rate for etching the second insulating film is higher than the etching rate for etching the third insulating film.

Preferably, after depositing a third insulating film on the second insulating film, the fin layer and the first insulating film, depositing a fourth insulating film on the third insulating film to form the resist The second etching film, the third insulating film, and the fourth insulating film are etched as the second mask.

Preferably, the method for fabricating the semiconductor device further includes a third step of forming a gate insulating film after the second step, forming a gate conductive film around the gate insulating film, and conducting the gate electrode The film is etched, whereby the gate conductive film remains on the dummy gate and the sidewall of the columnar layer, thereby forming a gate electrode and a gate wiring.

Preferably, the method for fabricating the semiconductor device further includes a fourth step of depositing a first nitride film after the third step, and etching the first nitride film to form the first nitride film The gate electrode and the sidewall of the gate wiring remain, and the upper portion of the gate conductive film is exposed, and the upper portion of the exposed gate conductive film is removed by etching.

Preferably, the method of manufacturing a semiconductor device further includes a fifth step of depositing an interlayer insulating film and planarizing a surface of the interlayer insulating film after the fourth step, thereby performing etchback of the interlayer insulating film. After the upper portion of the columnar layer is exposed, a third resist for forming the first contact is formed, and the interlayer insulating film is etched to form a contact hole in the contact hole. After the metal material is deposited, a fourth resist for forming a metal wiring is formed on the fin-shaped germanium layer, and the metal wiring is formed by etching.

A semiconductor device according to a third aspect of the present invention includes a fin-shaped semiconductor layer formed on a semiconductor substrate, a first insulating film formed around the fin-shaped semiconductor layer, and a columnar semiconductor layer formed on the fin-shaped surface a semiconductor layer having a width equal to a width of the fin-shaped semiconductor layer; a gate insulating film formed around the columnar semiconductor layer; a gate electrode formed around the gate insulating film; and a gate wiring The gate electrode is connected to the gate electrode and extends in a second direction orthogonal to the first direction in which the fin-shaped semiconductor layer extends, and is formed in a side wall shape on the sidewall of the dummy gate; The diffusion layer is formed on an upper portion of the columnar semiconductor layer, and the second diffusion layer is formed on an upper portion of the fin-shaped semiconductor layer and a lower portion of the columnar semiconductor layer.

According to the present invention, it is possible to provide a method of manufacturing an SGT capable of reducing the number of steps required to manufacture an SGT, and a configuration of an SGT obtained by the method of manufacturing the SGT.

101‧‧‧矽 substrate

102‧‧‧1st resist

103‧‧‧Finned layer

104‧‧‧1st insulating film

105‧‧‧2nd insulating film

106‧‧‧3rd insulating film (virtual gate)

107‧‧‧4th insulating film

108‧‧‧2nd resist

109‧‧‧ Columnar layer

110‧‧‧gate insulating film

111‧‧‧gate conductive film

111a‧‧‧gate electrode

111b‧‧‧ gate wiring

112‧‧‧1st nitride film

113‧‧‧1st diffusion layer

114‧‧‧2nd diffusion layer

115‧‧‧Oxide film

116‧‧‧2nd telluride

117‧‧‧1st compound

118‧‧‧Contact barrier

119‧‧‧Interlayer insulating film

120‧‧‧3rd resist

121, 122‧‧‧ contact holes

123‧‧‧Contact barrier

124‧‧‧Metal materials

125, 126, 127‧‧‧ 4th resist

128, 129, 130‧‧‧Metal wiring

131, 132‧‧‧ first contact

X-x', y-y'‧‧‧ line

1(a) is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a cross-sectional view taken along line x-x' of FIG. 1(a), and FIG. 1(c) is a view of FIG. 1(a) Sectional view on the y-y' line.

2(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 2(b) is a cross-sectional view taken along the line x-x' of FIG. 2(a), and FIG. 2(c) is a view of FIG. A) A section of the y-y' line.

3(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 3(b) is a cross-sectional view taken along the line x-x' of FIG. 3(a), and FIG. 3(c) is a view of FIG. A) A section of the y-y' line.

4(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 4(b) is a cross-sectional view taken along the line x-x' of FIG. 4(a), and FIG. 4(c) is a view of FIG. A) A section of the y-y' line.

5(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 5(b) is a cross-sectional view taken along the line x-x' of FIG. 5(a), and FIG. 5(c) is a view of FIG. A) A section of the y-y' line.

6(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 6(b) is a cross-sectional view taken along the line x-x' of FIG. 6(a), and FIG. 6(c) is a view of FIG. A) A section of the y-y' line.

Fig. 7 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, Fig. 7 (b) is a cross-sectional view taken along the line x-x' of Fig. 7 (a), and Fig. 7 (c) is a view of Fig. 7 ( A) A section of the y-y' line.

8(a) is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 8(b) is a cross-sectional view taken along line xx' of FIG. 8(a), and FIG. 8(c) is a cross-sectional view taken along line y-y' of FIG. 8(a).

9(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 9(b) is a cross-sectional view taken along the line x-x' of FIG. 9(a), and FIG. 9(c) is a view of FIG. A) A section of the y-y' line.

Fig. 10 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 10 (b) is a cross-sectional view taken along the line x-x' of Fig. 10 (a), and Fig. 10 (c) is a view of Fig. 10 ( A) A section of the y-y' line.

Fig. 11 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 11 (b) is a cross-sectional view taken along the line x-x' of Fig. 11 (a), and Fig. 11 (c) is a view of Fig. 11 ( A) A section of the y-y' line.

Fig. 12 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 12 (b) is a cross-sectional view taken along the line x-x' of Fig. 12 (a), and Fig. 12 (c) is a view of Fig. 12 ( A) A section of the y-y' line.

Fig. 13 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 13 (b) is a cross-sectional view taken along the line x-x' of Fig. 13 (a), and Fig. 13 (c) is a view of Fig. 13 ( A) A section of the y-y' line.

Fig. 14 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 14 (b) is a cross-sectional view taken along the line x-x' of Fig. 14 (a), and Fig. 14 (c) is a view of Fig. 14 ( A) A section of the y-y' line.

Fig. 15 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and Fig. 15 (b) is a cross-sectional view taken along line x-x' of Fig. 15 (a), and Fig. 15 (c) It is a cross-sectional view on the y-y' line of Fig. 15(a).

Fig. 16 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 16 (b) is a cross-sectional view taken along the line x-x' of Fig. 16 (a), and Fig. 16 (c) is a view of Fig. 16 ( A) A section of the y-y' line.

Fig. 17 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, Fig. 17 (b) is a cross-sectional view taken along the line x-x' of Fig. 17 (a), and Fig. 17 (c) is a view of Fig. 17 ( A) A section of the y-y' line.

18(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 18(b) is a cross-sectional view taken along line x-x' of FIG. 18(a), and FIG. 18(c) is FIG. A) A section of the y-y' line.

Fig. 19 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 19 (b) is a cross-sectional view taken along the line x-x' of Fig. 19 (a), and Fig. 19 (c) is a view of Fig. 19 ( A) A section of the y-y' line.

20(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 20(b) is a cross-sectional view taken along the line x-x' of FIG. 20(a), and FIG. 20(c) is a view of FIG. A) A section of the y-y' line.

Fig. 21 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 21 (b) is a cross-sectional view taken along the line x-x' of Fig. 21 (a), and Fig. 21 (c) is a view of Fig. 21 ( A) A section of the y-y' line.

Fig. 22 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 22 (b) is a cross-sectional view taken along the line x-x' of Fig. 22 (a), and Fig. 22 (c) is a view of Fig. 22 ( A) A section of the y-y' line.

Fig. 23 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 23 (b) is a cross-sectional view taken along the line x-x' of Fig. 23 (a), and Fig. 23 (c) is a view of Fig. 23 ( A) A section of the y-y' line.

Fig. 24 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, Fig. 24 (b) is a cross-sectional view taken along the line x-x' of Fig. 24 (a), and Fig. 24 (c) is a view of Fig. 24 ( A) A section of the y-y' line.

Fig. 25 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 25 (b) is a cross-sectional view taken along the line x-x' of Fig. 25 (a), and Fig. 25 (c) is a view of Fig. 25 ( A) A section of the y-y' line.

Fig. 26 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 26 (b) is a cross-sectional view taken along the line x-x' of Fig. 26 (a), and Fig. 26 (c) is a view of Fig. 26 ( A) A section of the y-y' line.

Fig. 27 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, Fig. 27 (b) is a cross-sectional view taken along the line x-x' of Fig. 27 (a), and Fig. 27 (c) is a view of Fig. 27 ( A) A section of the y-y' line.

28(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 28(b) is a cross-sectional view taken along the line x-x' of FIG. 28(a), and FIG. 28(c) is a view of FIG. A) A section of the y-y' line.

Fig. 29 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 29 (b) is a cross-sectional view taken along the line x-x' of Fig. 29 (a), and Fig. 29 (c) is a view of Fig. 29 ( A) A section of the y-y' line.

FIG. 30(a) shows the flattening method of the semiconductor device according to the embodiment of the present invention. 30(b) is a cross-sectional view taken along line xx' of FIG. 30(a), and FIG. 30(c) is a cross-sectional view taken along line y-y' of FIG. 30(a).

Fig. 31 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 31 (b) is a cross-sectional view taken along the line x-x' of Fig. 31 (a), and Fig. 31 (c) is a view of Fig. 31 ( A) A section of the y-y' line.

32(a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 32(b) is a cross-sectional view taken along the line x-x' of FIG. 32(a), and FIG. 32(c) is a view of FIG. A) A section of the y-y' line.

Fig. 33 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, Fig. 33 (b) is a cross-sectional view taken along the line x-x' of Fig. 33 (a), and Fig. 33 (c) is a view of Fig. 33 ( A) A section of the y-y' line.

Fig. 34 (a) is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein Fig. 34 (b) is a cross-sectional view taken along the line x-x' of Fig. 34 (a), and Fig. 34 (c) is a view of Fig. 34 ( A) A section of the y-y' line.

Hereinafter, a semiconductor device (SGT) according to an embodiment of the present invention will be described with reference to FIGS. 2(a), 2(b), 2(c) to 34(a), 34(b), and 34(c). The manufacturing method of the manufacturing method and the structure of the semiconductor device (SGT) obtained by the manufacturing method.

First, a first step of forming a fin-shaped germanium layer 103 on the germanium substrate 101 and forming a first insulating film 104 around the fin-shaped germanium layer 103 is shown using the first mask.

That is, as shown in FIGS. 2(a), 2(b), and 2(c), the first resist 102 for forming the fin-shaped germanium layer 103 is formed on the germanium substrate 101.

Then, as shown in FIGS. 3(a), 3(b), and 3(c), the first resist 102 is used as the first mask, and the germanium substrate 101 is etched to form the fin-shaped germanium layer 103. Here, the fin-shaped germanium layer 103 is formed by using a resist as the first mask. However, a hard mask such as an oxide film or a nitride film may be used for the first mask.

Then, as shown in FIGS. 4(a), 4(b), and 4(c), the first resist 102 is removed.

Then, as shown in FIGS. 5(a), 5(b), and 5(c), the first insulating film 104 is deposited around the fin-shaped germanium layer 103. As the first insulating film 104, an oxide film formed by high-density plasma or an oxide film formed by low-pressure chemical vapor deposition (CVD) may be used.

Then, as shown in FIGS. 6(a), 6(b), and 6(c), the first insulating film 104 is etched back to expose the upper portion of the fin-shaped germanium layer 103. The steps up to here are the same as the method of manufacturing the fin-shaped layer disclosed in Non-Patent Document 1.

According to the above, the first step of the present embodiment is shown in which the first resist 102 is used as the first mask, and the fin-shaped germanium layer 103 is formed on the germanium substrate 101, and the fin-shaped germanium layer is formed on the germanium substrate 101. The first insulating film 104 is formed around the 103.

Hereinafter, the second step of the present embodiment is described in which the second insulating film 105 is formed around the fin-shaped germanium layer 103, and the second insulating film 105 is etched, whereby the second insulating film 105 remains in the second insulating film 105. The sidewall of the fin-shaped germanium layer 103 is subsequently deposited on the second insulating film 105, the fin-shaped germanium layer 103, and the first insulating film 104. The insulating film 106. Subsequently, the gate wiring 111b and the columnar layer 109 are formed so as to extend in the second direction (front-rear direction) orthogonal to the first direction (left-right direction) in which the fin-shaped layer 103 extends. After the second resist 108 is used as the second mask, the second insulating film 105 and the third insulating film 106 are etched, and then the fin layer 103 is etched. The second insulating film 105 is removed, thereby forming a columnar layer 109 and a dummy gate including the third insulating film 106.

That is, as shown in FIGS. 7(a), 7(b), and 7(c), the second insulating film 105 is formed around the fin-shaped germanium layer 103. Preferably, the second insulating film 105 is an oxide film formed by a normal pressure CVD (Chemical Vapor Deposition) having a fast wet etching speed. Further, as an alternative, the second insulating film 105 may be an oxide film formed by low pressure CVD (Chemical Vapor Deposition).

Then, as shown in FIGS. 8(a), 8(b), and 8(c), the second insulating film 105 is etched to leave the second insulating film 105 in the fin layer 103. Side wall.

Then, as shown in FIG. 9(a), FIG. 9(b), and FIG. 9(c), a third insulating film is deposited on the second insulating film 105, the fin-shaped germanium layer 103, and the first insulating film 104. 106. Subsequently, the surface of the third insulating film 106 is planarized by a chemical mechanical polishing (CMP) method or the like. As the third insulating film 106, an insulating film having an etching rate lower than the etching rate of the second insulating film 105 is preferably used. That is, for example, in the second insulating film 105 In the case of an oxide film formed by atmospheric pressure CVD, the third insulating film 106 is preferably an oxide film formed by high-density plasma or an oxide film or a nitride film formed by low-pressure CVD. Further, when the second insulating film 105 is an oxide film formed by low-pressure CVD, the third insulating film 106 is preferably a nitride film.

Then, as shown in FIGS. 10(a), 10(b), and 10(c), the fourth insulating film 107 is deposited on the laminated body. The fourth insulating film 107 is preferably an oxide film formed by atmospheric pressure CVD (Chemical Vapor Deposition) having a large wet etching rate, similarly to the second insulating film 105. Furthermore, the formation of the fourth insulating film 107 can be omitted. Further, as a substitute for the oxide film, the fourth insulating film 107 may be a nitride film.

Then, as shown in FIGS. 11( a ), 11 ( b ), and 11 ( c ), the second direction orthogonal to the first direction (left-right direction) extending with respect to the fin-shaped layer 103 ( The second resist 108 for forming the gate wiring 111b and the columnar layer 109 is formed in a manner of extending in the front-rear direction.

Then, as shown in FIG. 12(a), FIG. 12(b), and FIG. 12(c), the second insulating film 105 and the third insulating film 106 are used by using the second resist 108 as the second mask. The fourth insulating film 107 is etched.

Then, as shown in FIGS. 13(a), 13(b), and 13(c), the fin layer 103 is formed by etching the fin layer 103.

Then, as shown in FIGS. 14(a), 14(b), and 14(c), the second resist 108 is removed.

Then, as shown in FIG. 15(a), FIG. 15(b), and FIG. 15(c), the removal is performed. The second insulating film 105. Here, since the fourth insulating film 107 is formed of the same material as the second insulating film 105 (here, an oxide film formed by atmospheric pressure CVD), the fourth insulating film is removed when the second insulating film 105 is removed. The film 107 is also removed. The second insulating film 105 and the fourth insulating film 107 are preferably removed by wet etching. Further, since the etching rate of the third insulating film 106 is smaller than the etching rate of the second insulating film 105, the third insulating film 106 remains as a dummy gate.

From the above, the second step of the present embodiment is shown in which the second insulating film 105 is formed around the fin-shaped germanium layer 103, and the second insulating film 105 is etched to thereby make the second insulating film. The film 105 remains on the sidewall of the fin-shaped germanium layer 103, and then the third insulating film 106 is deposited on the second insulating film 105, the fin-shaped germanium layer 103, and the first insulating film 104, and then along the fins The second resist 108 for forming the gate wiring 111b and the columnar layer 109 is formed so that the first direction (left-right direction) in which the layer 103 extends and the second direction (front-rear direction) orthogonal to each other is formed. Then, the second insulating film 108 is used as the second mask, and the second insulating film 105 and the third insulating film 106 are etched, and then the fin layer 103 is etched, and the second insulating film is removed. 105, thereby forming a columnar layer 109 and a dummy gate including the third insulating film 106.

Hereinafter, a third step of the present embodiment, that is, after the second step, a gate insulating film 110 is formed, a gate conductive film 111 is formed around the gate insulating film 110, and the gate conductive film 111 is formed. Etching is performed to leave the gate conductive film 111 on the dummy gate including the third insulating film 106 and the sidewall of the columnar layer 109, thereby forming the gate electrode 111a and the gate wiring 111b.

That is, as shown in Fig. 16 (a), Fig. 16 (b), and Fig. 16 (a), the gate insulating film 110 is formed on the laminated body, and further, the gate conductive is formed around the gate insulating film 110. Film 111. Here, as the gate conductive film 111, it is preferable to use a metal material which is used in the manufacturing process of the semiconductor and which sets the threshold voltage of the transistor, such as titanium nitride, titanium, tantalum nitride, tantalum, etc. . Among them, for the gate conductive film 111, it is particularly preferable to use a material having an etching rate greater than 矽 during wet etching.

Further, as the gate insulating film 110, a material which is used in a semiconductor manufacturing step, such as an oxide film, an oxynitride film, or a high dielectric film, is preferably used.

Then, as shown in FIGS. 17(a), 17(b), and 17(c), a predetermined region of the gate conductive film 111 is etched to leave a part of the gate conductive film 111 in the first portion. 3 a dummy gate of the insulating film 106 and a sidewall of the columnar layer 109. Thereby, the gate electrode 111a is formed on the side wall of the columnar layer 109, and the gate line 111b is formed in a side wall shape on the side wall of the dummy gate including the third insulating film 106.

According to the present embodiment, as described above, the fin-shaped germanium layer 103, the pillar-shaped germanium layer 109, and the gate wiring 111b can be formed by using two masks. Thereby, the number of steps required for the manufacture of the semiconductor device (SGT) can be reduced. Further, according to the present embodiment, the position at which the columnar layer 109 is formed and the position at which the gate line 111b is formed are aligned in a line, and thus the positional deviation of the columnar layer 109 and the gate line 111b is eliminated.

From the above, the third step of the present embodiment is shown, that is, the gate insulating film 110 is formed, and a gate conductive film is formed around the gate insulating film 110. 111, the gate conductive film 111 is etched, thereby forming a gate electrode 111a on the sidewall of the columnar layer 109, and a sidewall wall on the sidewall of the dummy gate including the third insulating film 106. The gate wiring 111b is formed in the ground.

Hereinafter, a fourth step of the present embodiment is described in which after the third step, the first nitride film 112 is deposited, and the first nitride film 112 is etched, whereby the first nitride film 112 is formed. The gate electrode 111a and the sidewall of the gate wiring 111b remain, and the upper portion of the gate conductive film 111 is exposed, and the exposed upper portion of the gate conductive film 111 is removed by etching.

That is, as shown in FIGS. 18(a), 18(b), and 18(c), the first nitride film 112 is deposited on the laminate.

Then, as shown in FIGS. 19(a), 19(b), and 19(c), the first nitride film 112 is etched, whereby the first nitride film 112 remains on the gate electrode 111a. And a side wall of the gate wiring 111b, and an upper portion of the gate conductive film 111 is exposed.

Then, as shown in FIGS. 20(a), 20(b), and 20(c), the upper portion of the exposed gate conductive film 111 is removed by etching.

According to the above, the fourth step of the present embodiment is shown in which the first nitride film 112 is deposited and the first nitride film 112 is etched, whereby the first nitride film 112 remains in the gate. The side walls of the electrode electrode 111a and the gate line 111b are exposed, and the upper portion of the gate conductive film 111 is exposed, and the upper portion of the exposed gate conductive film 111 is removed by etching.

The steps shown in Fig. 20 (a), Fig. 20 (b), and Fig. 20 (c) are as follows. As shown in FIGS. 21(a), 21(b), and 21(c), arsenic (As) is implanted into a predetermined position of the columnar layer 109 to form the first diffusion layer 113 and the second diffusion layer 114. Here, nMOS is formed, and when pMOS is formed, boron or boron fluoride is implanted.

Then, as shown in Fig. 22 (a), Fig. 22 (b), and Fig. 22 (c), after the oxide film 115 is deposited on the laminate, heat treatment is performed. Here, a nitride film may be used instead of the oxide film.

Then, as shown in FIGS. 23(a), 23(b), and 23(c), the oxide film 115 is removed by etching, but a part of the oxide film 115 remains. Here, wet etching is preferably used. Thereby, the oxide film 115 remains between the first nitride film 112 and the columnar layer 109, and between the first nitride film 112 and the dummy gate including the third insulating film 106. Further, dry etching may be used instead of wet etching.

Then, as shown in FIGS. 24(a), 24(b), and 24(c), a metal material is deposited at a predetermined position of the laminate, and after the heat treatment, the unreacted metal material is removed. Thereby, the first silicide 117 and the second germanide 116 are formed on the first diffusion layer 113 and the second diffusion layer 114, respectively.

In the fifth step of the present embodiment, the interlayer insulating film 119 is deposited after the fourth step, and the surface of the interlayer insulating film 119 is planarized by a CMP (Chemical Mechanical Polishing) method or the like. Further, etchback of the interlayer insulating film 119 is performed, whereby the third resist 120 for forming the first contacts 131 and 132 is formed after the upper portion of the columnar layer 109 is exposed, and the interlayer insulating film 119 is formed. Etching, thereby forming contact holes 121, 122. Subsequently, The metal material 124 is deposited in the contact holes 121 and 122, whereby the first contact 131 is formed on the fin-shaped germanium layer 103, and the first contact 132 is formed on the gate wiring 111b. Subsequently, fourth resists 125, 126, and 127 for forming the metal wirings 128, 129, and 130 are formed, and the metal wirings 128, 129, and 130 are formed by etching.

That is, as shown in Fig. 25 (a), Fig. 25 (b), and Fig. 25 (c), a contact stopper 118 is formed in a predetermined region of the laminated body using a nitride film or the like, and is covered by a cover contact. The interlayer insulating film 119 is deposited in the form of the layer 118. Subsequently, the surface of the interlayer insulating film 119 is planarized by a CMP (Chemical Mechanical Polishing) method or the like.

Then, as shown in FIGS. 26(a), 26(b), and 26(c), the interlayer insulating film 119 is etched back, and the contact barrier layer 118 on the columnar layer 109 and the third insulating film are included. A contact barrier layer 118 on the virtual gate of 106 is exposed.

Then, as shown in FIGS. 27(a), 27(b), and 27(c), the third resist 120 for forming the contact holes 121 and 122 is formed at a predetermined position of the laminated body.

Then, as shown in FIGS. 28(a), 28(b), and 28(c), the interlayer insulating film 119 exposed from the third resist 120 is etched to form the contact holes 121 and 122.

Then, as shown in FIGS. 29(a), 29(b), and 29(c), the third resist 120 is peeled off.

Then, as shown in FIGS. 30(a), 30(b), and 30(c), the contact barrier layer 118 is etched, whereby the contact barrier layer 118 and the columnar layer of the bottom of the contact hole 121 are removed. The top end portion of 109 contacts the barrier layer 118. And, at this time, The case where the contact barrier layer 123 remains on the side wall of the columnar layer 109 (see FIGS. 30(a), 30(b), and 30(c)).

Then, as shown in FIGS. 31(a), 31(b), and 31(c), the metal material 124 is deposited so as to fill the contact holes 121 and 122, whereby the contact holes 121 and 122 respectively The first contacts 131 and 132 are formed, and the metal material 124 is formed so as to be connected to the first contacts 131 and 132 and the first germanide 117 on the upper portion of the columnar layer 109.

Then, as shown in FIG. 32(a), FIG. 32(b), and FIG. 32(c), the fourth resist 125 for forming the metal wirings 128, 129, and 130 is formed at a predetermined position on the laminated body. 126, 127.

Then, as shown in FIGS. 33(a), 33(b), and 33(c), the metal material 124 exposed from the fourth resists 125, 126, and 127 is etched to form metal wirings 128 and 129. 130.

Then, as shown in FIGS. 34(a), 34(b), and 34(c), the fourth resists 125, 126, and 127 are peeled off.

According to the above steps, the metal wires 128, 129, 130 including the metal material 124 and the upper portion of the columnar layer 109 are not directly electrically connected via contact, and therefore it is not necessary to separately form a contact on the upper portion of the columnar layer 109. step. Further, since the contact holes 121 and 122 forming the first contacts 131 and 132 are formed above the fin-shaped layer 103, the depth of the contact holes 121 and 122 can be made shallow. Therefore, the contact holes 121 and 122 are easily formed, and the contact holes 121 and 122 are easily filled with the metal material 124.

In the fifth step of the present embodiment, the interlayer insulating film 119 is deposited on the laminated body, and the surface of the interlayer insulating film 119 is subjected to CMP (Chemical Mechanical Polishing) or the like. After planarization, the interlayer insulating film 119 is etched back, whereby the upper portion of the columnar layer 109 is exposed, and then the third resist 120 for forming the first contacts 131 and 132 is formed, and the interlayer insulating film 119 is formed. The contact holes 121 and 122 are formed by etching, and the metal material 124 is deposited in the contact holes 121 and 122, whereby the first contacts 131 and 132 are formed on the fin layer 103. Subsequently, fourth resists 125, 126, and 127 for forming the metal wirings 128, 129, and 130 are formed, and the metal wirings 128, 129, and 130 are formed by etching.

From the above, a method of manufacturing a semiconductor device (SGT) in which a fin-shaped germanium layer 103, a pillar-shaped germanium layer 109, and a gate wiring 111b can be formed by using two masks is shown. Further, according to the manufacturing method of the SGT, the entire SGT can be formed by a total of four masks.

1(a), 1(b), and 1(c) show the configuration of a semiconductor device of the present embodiment obtained by the above-described method of manufacturing a semiconductor device.

As shown in FIG. 1(a), FIG. 1(b), and FIG. 1(c), the semiconductor device of the present embodiment includes a fin-shaped germanium layer 103 formed on the germanium substrate 101, and a first insulating film 104 formed on the first insulating film 104. The periphery of the finned layer 103 and the columnar layer 109 are formed on the fin layer 103. The width of the columnar layer 109 is equal to the width of the fin layer 103. The semiconductor device of the present embodiment further includes: a gate insulating film 110 formed around the columnar layer 109; and a gate electrode 111a formed around the gate insulating film 110; The gate wiring 111b is connected to the gate electrode 111a and extends in a second direction (front-rear direction) orthogonal to the first direction (left-right direction) in which the fin-shaped layer 103 extends. The gate wiring 111b is formed in a side wall shape on the side wall of the dummy gate including the third insulating film 106. The semiconductor device of the present embodiment further includes a first diffusion layer 113 formed on an upper portion of the columnar layer 109, and a second diffusion layer 114 formed over the upper portion of the fin-shaped layer 103 and the lower portion of the columnar layer 109. .

According to the above-described embodiment, the gate wiring 111b is formed in a side wall shape on the side wall of the dummy gate including the third insulating film 106. Therefore, the gate wiring is determined by the height of the dummy gate including the third insulating film 106. The resistance value of 111b. Therefore, the electric resistance of the gate wiring 111b can be suppressed lower than when the thin gate wiring is formed in a planar shape.

According to the above embodiment, the method of manufacturing a semiconductor device includes forming the fin-shaped germanium layer 103 on the germanium substrate 101 using the first resist 102 as the first mask, and forming the first layer around the fin-shaped germanium layer 103. The insulating film 104 is formed on the periphery of the fin-shaped germanium layer 103, and the second insulating film 105 is etched to leave the second insulating film 105 on the sidewall of the fin-shaped germanium layer 103. Subsequently, the third insulating film 106 is deposited on the second insulating film 105, the fin-shaped germanium layer 103, and the first insulating film 104, and then orthogonally in a direction extending with respect to the fin-shaped germanium layer 109. The second resist 108 for forming the gate wiring 111b and the columnar layer 109 is formed in a manner of extending in the two directions (front-rear direction), and the second resist 108 is used as the second mask to the second insulation. The film 105 and the third insulating film 106 are etched. Thereafter, the fin layer 103 is etched to remove the second insulating film 105. A columnar tantalum layer 109 and a dummy gate including the third insulating film 106 are formed. Subsequently, the gate insulating film 110 is formed, the gate conductive film 111 is formed around the gate insulating film 110, and the gate conductive film 111 is etched, whereby the gate conductive film 111 remains in the columnar layer 109. The sidewall and the sidewall of the dummy gate including the third insulating film 106 form a gate electrode 111a and a gate wiring 111b on the sidewall of the columnar layer 109 and the sidewall of the third insulating film 106, respectively.

According to the above embodiment, as described above, the finned layer 103, the columnar layer 109, and the gate line 111b can be formed by using two masks (the first mask and the second mask). Thereby, the number of steps required for the manufacture of the semiconductor device can be reduced.

Further, according to the above embodiment, the position at which the columnar layer 109 is formed and the position at which the gate line 111b is formed are aligned in a line, so that the positional deviation of the columnar layer 109 and the gate line 111b can be eliminated.

Further, since the gate wiring 111b is formed in a side wall shape on the side wall of the dummy gate including the third insulating film 106, the resistance of the gate wiring 111b is determined by the height of the dummy gate including the third insulating film 106. value. Therefore, the electric resistance of the gate wiring 111b can be suppressed lower than when the thin gate wiring 111b is formed in a planar shape.

Further, various embodiments and modifications may be employed without departing from the spirit and scope of the invention. Further, the above embodiment is for explaining an embodiment of the present invention, and does not limit the scope of the present invention.

For example, in the above embodiments, a method of manufacturing a semiconductor device in which a p-type (including a p ⁺ type) and an n-type (including an n ⁺ type) are respectively opposite conductivity types, and a semiconductor device obtained by the method are of course It is also included in the technical scope of the present invention.

103‧‧‧Finned layer

106‧‧‧3rd insulating film (virtual gate)

109‧‧‧ Columnar layer

110‧‧‧gate insulating film

111‧‧‧gate conductive film

111a‧‧‧gate electrode

111b‧‧‧ gate wiring

128, 129, 130‧‧‧Metal wiring

131, 132‧‧‧ first contact

X-x', y-y'‧‧‧ line

Claims (8)

A method of manufacturing a semiconductor device, comprising: a fin-shaped germanium layer formed on a germanium substrate; a first insulating film formed around the fin-shaped germanium layer; and a columnar germanium layer formed on the fin-shaped germanium layer a gate insulating film formed around the columnar layer; a gate electrode formed around the gate insulating film; and a gate wiring connected to the gate electrode and along the finned fin The semiconductor device manufacturing method of the semiconductor device is characterized in that the fin layer is formed by using a first mask and the columnar crucible is formed by using a second mask. The layer is connected to the above gate wiring. A method of manufacturing a semiconductor device, comprising: forming a fin-shaped germanium layer on a germanium substrate using a first mask, and forming a first insulating film around the fin-shaped germanium layer; and second a step of forming a second insulating film around the fin-shaped germanium layer and etching the second insulating film to leave the second insulating film on a sidewall of the fin-shaped germanium layer on the second insulating film The third insulating film is deposited on the upper fin-shaped layer and the first insulating film, and is formed to extend in a second direction orthogonal to the first direction in which the fin-shaped layer extends. a resist for forming a gate wiring and a columnar layer, After the resist is used as the second mask, the second insulating film and the third insulating film are etched, and then the fin-shaped germanium layer is etched to remove the second insulating film, thereby forming the columnar shape. The germanium layer and the dummy gate including the third insulating film. The method of manufacturing a semiconductor device according to claim 2, wherein an etching rate for etching the second insulating film is larger than an etching rate for etching the third insulating film. The method of manufacturing a semiconductor device according to claim 2, wherein the third insulating film is deposited on the second insulating film, the fin layer and the first insulating film, and then the third insulating layer A fourth insulating film is deposited on the film, and the resist is used as a second mask, and the second insulating film, the third insulating film, and the fourth insulating film are etched. The method of manufacturing a semiconductor device according to claim 2, further comprising: a third step of forming a gate insulating film after the second step, and forming a gate conductive film around the gate insulating film; The gate conductive film is etched to leave the gate conductive film on the dummy gate and the sidewall of the columnar layer, thereby forming a gate electrode and a gate wiring. The method of manufacturing a semiconductor device according to claim 5, further comprising: In the fourth step, after the third step, the first nitride film is deposited, and the first nitride film is etched to leave the first nitride film on the sidewalls of the gate electrode and the gate wiring. Further, an upper portion of the gate conductive film is exposed, and the exposed upper portion of the gate conductive film is removed by etching. The method of manufacturing a semiconductor device according to claim 6, further comprising: a fifth step of: after the fourth step, depositing an interlayer insulating film and planarizing a surface of the interlayer insulating film to perform the interlayer insulating After the film is etched back, the upper portion of the columnar layer is exposed, a third resist for forming the first contact is formed, and the interlayer insulating film is etched to form a contact hole in the contact hole. After the metal material is deposited, a fourth resist for forming a metal wiring is formed on the fin-shaped germanium layer, and the metal wiring is formed by etching. A semiconductor device comprising: a fin-shaped semiconductor layer formed on a semiconductor substrate; a first insulating film formed around the fin-shaped semiconductor layer; and a columnar semiconductor layer formed on the fin-shaped semiconductor layer; Having a width equal to the width of the fin-shaped semiconductor layer; a gate insulating film formed around the columnar semiconductor layer; a gate electrode formed around the gate insulating film; and a gate wiring connected to the gate The pole electrode extends in a second direction orthogonal to the first direction in which the fin-shaped semiconductor layer extends, and is on the sidewall of the dummy gate The first diffusion layer is formed on an upper portion of the columnar semiconductor layer, and the second diffusion layer is formed on an upper portion of the fin-shaped semiconductor layer and a lower portion of the columnar semiconductor layer.