TWI228770B - All-in-one polishing process for a semiconductor wafer - Google Patents

Abstract

A semiconductor wafer has a top surface and an edge bevel surface, and a first material layer and a second material layer are respectively formed on the top surface and the edge bevel surface. A surface chemical mechanical polishing (surface CMP) process is performed to polish and remove portions of the first material layer down to a first thickness, and a rim CMP process is performed to completely remove the second material layer on the edge bevel surface down to the edge bevel surface thereafter to achieve a smooth surface of the edge bevel surface. Finally, a chemical cleaning process is performed to clean the rim surface and the top surface, and the semiconductor wafer is dried thereafter.

Description

1228770 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention provides a full-function semiconductor wafer polishing process, especially a process using two chemical mechanical polishing (chemica 1 mechanica 1 pol i shi ng, CMP) processes. A method of grinding one top surface and one edge bevel surface of the semiconductor wafer, and then cleaning and drying the semiconductor wafer. [Previous technology] At present, a 'multilevel metallization process', which uses a plurality of layers of metal interconnect layers and dielectric materials (dielectrics) having a lower dielectric constant to connect each semiconductor element on a semiconductor wafer to each other It is connected in series to complete the entire stacked circuit architecture, which has been widely used in the process of very large scale integration (VLSI). However, in the general process, these metal lines and semiconductor components will cause the surface of the integrated circuit to show a severe topography of undulations, which increases the occurrence of bumps during subsequent deposition or pattern transfer processes. Disadvantages such as overhang, void, or difficulty in focusing and difficulty in etching. Therefore, after entering the deep sub-micron semiconductor process, most of the semiconductor industry will use chemical mechanical polishing (CMP) process with better planarization effect to uniformly remove targets with irregular surfaces on a semiconductor wafer.

Page 7 1228770 V. Description of the invention (2) The thin film layer (target thin film) enables the semiconductor wafer to have a flat and regular surface after the chemical mechanical polishing process, so as to achieve a comprehensive planarization of the surface of the semiconductor wafer to ensure that The yield of subsequent processes is 0. Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are respectively a method for cleaning and cleaning a semiconductor wafer 10, and a schematic diagram and a cross-sectional view of the semiconductor wafer 10, to be polished and cleaned. As shown in FIGS. 1 and 2, the semiconductor wafer 10 includes a top surface 10a, an edge bevel surface 10b, and a bottom surface 1 Oc, and the crystal edge surface 10b includes a At least one front side bevel 10bl, one backside bevel 10b2, and one side edge 10b3 are formed on the upper surface 10a to be ground to a first thickness, and the interior includes at least one _ The first material layer 12 of the conductor structure (such as a double damascene structure or a capacitor structure, which is not shown), that is, the surface 1 0 b contains a layer that is formed before the first material layer 12 Or, the second material layer 14 is formed at the same time as the second side material layer 12 which is not required by the product and needs to be completely removed. The first layer 12 and the second material layer 14 may each be a subject layer formed by a chemical vapor deposition (CVD) process and an electric copper plating (ECP) process. Each can also be an interposer formed by a chemical vapor deposition process. Generally, the first material layer 12 and the second material layer 4 are different from each other.

1228770 V. Description of the invention (3) Materials, composition, but depending on the actual conditions of the process, the first material layer j 2 and the second material layer 14 can also be composed of two identical materials. Besides, the side 10b3 of the semiconductor wafer 10 includes a positioning notch 16 for fixing the coordinates of the semiconductor wafer 10 during the grinding of the semiconductor wafer 10. Please refer to Fig. 3. The chemical mechanical polishing machine device, CMP devi mechanical polishing mechanism 2 package 22, one tiled on the grinding body wafer 10, pressed on the ground to supply the polishing semiconductor (slurry supply tube (cleaning so 1 section) The surface of the polishing pad 24 also includes a semiconductor wafer 10 with a supporting portion for grinding. The material layer 12 is provided with a liquid supply tube 32, which is provided with a deionized water (liquid (not shown)). A schematic diagram of cleaning the semiconductor wafer 100 (chemical mechanical polishing ce) 2 0. As shown in FIG. 3, the chemical contains a polishing pad 24 on a polishing plate platform 22, and a semiconductor polishing pad 24 The above wafer carrier (head) 28, the polishing liquid supply tube tube 30 of the polishing liquid of the integrated wafer 10, a deionized water or cleaning solution supply tube 26, and a conditioner 32. The wafer carrier has a 28-position (holder, not shown) for fixing to be researched. The slurry supply pipe 30 is used to grind the first slurry (s 1 urry, not shown), and clean for cleaning semiconductors. crystal Wafer 1 〇 and grinding 塾 2 4 Deionized water (DI water) or cleaning First of all, the polishing slurry is added on the top surface 10a of the semiconductor wafer 10

1228770

After 'according to the product, you need to use the gray star ★ 夂 ΓΟ / »¢-, polishing pad 2 4 for JL # A in sub-mechanical polishing mechanism 2 0 of 岍 熘 翌 * Z4 for the first material on the upper surface 10a by mechanical polishing Process to remove the upper part and the heart μ = 瑨 1 2 into a chemical machine and a thick product, and then drive the lane ο surface 10 to a material layer 12 to the first; i 塾 tLt ft sheet-10 transfer "'Different materials and softer sound tubes 2 and 6 are used for ordering and polishing. With a deionized water or a cleaning solution (as should be known to head 26, the cleaning solution, a surface cleaning polishing i: Second flute: 1 Μ) process' to remove the surface of semiconductor wafer 10, grind the residue (fUke) of material layer 12 and the remaining residue, and perform a chemical cleaning and drying process to clean and dry the semiconductor wafer 1 0, and complete the conventional method of grinding and cleaning semiconductor wafers 10, and the cross-sectional schematic diagram of the semiconductor wafers at this time is shown in Figure 4 0. However, as shown in Figure 4, after the chemical mechanical polishing process is completed, After removing the first material layer 12 on the upper surface 10a to the first thickness and cleaning the semiconductor wafer 10 The second material layer i 4, which is not required for the product and should be completely removed, still adheres to the crystal edge surface 10 b, so that in subsequent subsequent semiconductor processes, the second material layer 4 is often subjected to thermal stress ( thermal stress) or other factors that cause the phenomenon of peeling, which in turn causes the second material layer 14 to crack and generate f lake or particles. Especially when the whole batch (batch) Semiconductor wafers are placed in chemical vapor deposition

1228770 V. Description of the invention (5) During the CVD process in a vapor deposition (CVD) mechanism, if this type of peeling occurs on a semiconductor wafer located relatively above / it will seriously contaminate the surface of a semiconductor wafer located relatively below and cause defects ( defect). In addition, when the semiconductor wafer is moved according to the needs of the process, the debris of the material layer 14 is often dropped onto the surface 10 a above the semiconductor chip 10 and contaminates the product, thereby further contaminating the product. Affect the product's function. [Abstract] Therefore, the main purpose of the present invention is to provide a full-function (a 丨 1 — in one) semiconductor wafer polishing process to solve the conventional grinding and cleaning of semiconductor wafers. 1 In the method of 0, the problem of the second material layer 1 / cannot be completely removed. In a preferred embodiment of the present invention, the semiconductor wafer is placed on a wafer stage of a chemical mechanical polishing device (CMP device) and the semiconductor wafer includes an upper surface. (Top surface), bottom surface and edge bevel surface. A first material layer is formed on the upper surface, and a second material layer is formed on the crystal edge surface. First, using a polishing pad of one of the chemical mechanical polishing mechanisms,

1228770 V. Description of the invention (6) A surface chemical mechanical polishing (surf ace CMP) process to remove the first material layer on the upper surface to a first thickness. Next, a crystal edge chemical mechanical polishing (rim CMP) process is performed to completely remove the second material layer on the surface of the crystal edge. Next, the surface is polished and the residue of the polishing liquid is removed, and the semiconductor wafer is cleaned with deionized water or a cleaning liquid spray (cleaninS). Finally, the semiconductor wafer is cleaned by a well-known chemical cleaning process, and the semiconductor wafer is dried. Due to the machine learning to this layer, the invention of the crystal edge manufacturing process of the lotion film was first researched and the technology provided by the chemistry mentioned above is the thickness of the tube. The first grinding that can be achieved is for the surfaceization to separate and completely remove the chemical machinery using the same two clears including washing can, the extremely practical process machine, the upper crystal edge grinding machine, and the surface chemistry. The mechanism on the upper surface of the mechanical polishing surface performs another cleaning process of the chemical-chemical machine ^ I AL. The full power month process includes the cleaning and cleaning process, the type research, and the crystal edge material layer Φ first second Until the half-process grinding the first grinding technology material, there is one less conductor crystal, so this process, the cleaning process. Grinding process avoids thermally generated debris d. In addition to 彳 · 彳 buju mechanical research, the present invention uses the crystal edge 1 m 丄 π ^ u JrL field, so it can completely remove the crystal edge surface. In the second material & technology, the remaining second material layer is later produced thermal stress and peeled off (Peali ^ At (flake)), which contaminates the product and affects the yield of the product. (performance) Questions 0

Page 121228770 V. Description of the invention (7) [Embodiment] Please refer to FIG. 5 and FIG. 6. FIG. 5 and FIG. 6 are respectively a full-function semiconductor wafer polishing process of the present invention. Top schematic view and cross-sectional view of a semiconductor wafer 50 to be ground and cleaned. As shown in Figs. 5 and 6, the semiconductor wafer 50 includes a top surface 50a-an edge bevel surface 50b and a bottom surface located at the edge of the semiconductor wafer 50 and a few centimeters wide. ) 5 0c, and the crystal edge surface 50b includes a front side bevel 50bl, a backside bevel 50b2, and an edge 50b3. At least one first material layer 52 is formed on the upper surface 50a to be ground to a first thickness and contains at least one semiconductor structure (not shown). The first material layer 52 is formed first or at the same time as the first material layer 52, but it is not the second material layer 54 that is required for the product and is to be completely removed. Among them, the crystal edge surface 50b is used as a target for positioning (a1ign) the semiconductor wafer 50 during various processes of the semiconductor wafer 50, and the first material layer 52 and the second material layer 5 4 is formed by a full coverage (fu 1 1 coverage) process, and each can be a chemical vapor deposition (: VD) process or an electric copper plating (ECP) The metal layers formed in the process may each be a dielectric formed by a chemical vapor deposition process.

Page 13 1228770 V. Description of the invention (8) In the preferred embodiment of the present invention, 'the first material layer 52 and the second material R > 1 -c. S -V ύ' Α ^ Lit layer η 口 ' The bamboo material layer and the second material layer 54 are composed of two different materials, and in another embodiment of the present invention, the first material layer 52 and the second material layer 54 are also composed of two identical materials. Made up. In addition, the side 50b3 of the semiconductor wafer 50 includes a positioning notch 56 for fixing the coordinates of the semiconductor wafer 50 during the process of grinding and cleaning the semiconductor wafer 50. First, "a first slurry (not shown) is added to the upper surface 50a of the semiconductor wafer 50, and then a surface chemical mechanical polishing (surface CMP) process is performed according to the specifications required by the product". To remove the first material layer 52 on the upper surface 50a to the first thickness. Subsequently, using deionized water (DI water) as a first cleaning solution (not shown), a surface cleaning process is performed on the upper surface 50a of the semiconductor wafer 50 to remove the semiconductor wafer 50. The flakes of the first material layer 52 on the upper surface 50a and the first polishing slurry remain. Cheng Ru system. Grinding and researching the surface of the machine, the surface of the machine is 50% of the surface, and the crystals are guided halfway through. It is the last seven processes. For the seven-pass process, please refer to the surface process and the system. Grinding a grind ο ο stone 5 mechanical surface machine chemistry on the surface ο 5 surface piece of the crystal body leading into the half-in,, after the show shows the seven washing pictures

Leveling-In order to form the P table, the application and procedure should be based on the mechanical aspects of mechanical engineering, such as the Mo Tongyan. The process of entering the surface into the table \) y at 1 clean the C side

Page 14 1228770 V. Description of the invention (9) Known technology, so I will not repeat it here. Please refer to the grinding mechan. Not intended for a wafer (buff rollers, side b bevel, less one research, cleaning LCD round load, and the base 6 2 Please refer to FIG. 8 in the manufacturing process for the second clearing of the slurry semiconductor on the semiconductor. FIG. 8 is a rim chemical polishing device (rim CMP device) 60 used in the full-function semiconductor wafer process of the present invention. As shown in FIG. 8, the crystal edge chemical mechanical polishing mechanism 60 includes a wafer stage 62, a polishing pad 64, a notch pad 66, a plurality of rollers 68, and at least one Front bevel pad 70, at least bottom bevel pad 72, at least one edge pad 74, slurry supply tube 76 and at least one Supplying tube (cleaning solution supply tube) 78. The tool 6 2 is used to carry the semiconductor wafer 50, and the positioning rod 66 is used to position the notch 5 6 to position the semiconductor wafer 5 〇 In the coordinates of the wafer, as for the plurality of rollers 6 8, it can be used to strengthen the fixing The wafer 50 is on the wafer carrier 62. The polishing slurry supply pipe 76 is used to provide a second polishing slurry when the second material layer 54 is used (second j is not shown), and the cleaning liquid supply pipe 78 is used to provide a wafer cleaning wafer 50. A lotion made of deionized water or chemicals (not shown). Figure 9] Figure 9 is a full-featured semiconductor wafer polishing of the present invention

Page 15 1228770 Fifth, the invention description (ίο) mechanical polishing 'rim CMP) process method without thinking. As shown in FIG. 9, the second polishing slurry is added to the crystal edge surface 50 ◦ to perform the chemical mechanical polishing process of the crystal edge, and the chemical mechanical polishing mechanism 60 is used for upper bevel grinding 70 and lower bevel grinding 塾. 7 2 and the side grinding 7 4 grinding the semiconductor wafer 50 above the bevel 5 0 b 1, the lower bevel 5 0 b 2 and the side 5 0b 3 to completely remove the upper bevel 50bl, the lower bevel 50b2 and The second material layer 54 of the side 50b3. It is worth noting that, in order to match the slope of the upper bevel 50b 1 and the lower bevel 50b2, the upper bevel polishing pad 70 and the lower

The bevel polishing pads 72 are formed at an angle of about 15 to 28 degrees with the semiconductor wafer 50. In order to make the upper surface 50a of the semiconductor wafer more flat, a buffing CMP process may be performed on the upper surface 50a simultaneously or sequentially using the polishing pad 64. Then, a crystal surface and crystal edge cleaning or spray cleaning (surfaceandedge bevelcleaning) process is performed to clean the upper bevel 50 bl, the lower bevel 50 b 2 and the side 50 b 3 and the crystal plane of the semiconductor wafer 50 to completely remove Crystal edge surface 50a, the upper surface 50a, the upper oblique angle 50bl, the lower oblique angle 50b2, the side edge 50b3, and the residue of the second material layer 54 on the crystal surface and the remaining second abrasive polymer. As shown in FIG. 9, after the crystal edge chemical mechanical polishing process, the polishing and grinding process, and the crystal edge cleaning process are performed, the semiconductor wafer 50 has an upper oblique angle 50bl, a lower oblique angle 50b2, and a side edge 50. There is no second material layer 54 remaining on b3 and the crystal plane, as shown in FIG. 9. Finally, a chemical cleaning and drying (d r y i n g) process is performed to completely remove

P.16 ◦ Half-pass 50 mills 0 mill ^ Production of film research crystal research and washing ^ Day to day to learn to learn ί Leadership learn at 1 ° Guide assembly half-load A3 from the half-wash on grinding i. I ’m going to study Q in advance. I ’m going to use the crystal dart # '晶 不可 50 The body is also guided by the surface and i. For example, grinding crystal grinding 50 dry research and research of the research surface and the actual machine 50 mechanical table washing the previous machine, the supernatant of the machine as if you learned crystallography, the incarnation, 50 program bright edge guide sheet, square hair crystal half table The crystal drying line should wash the body and dry it in the clearing line. 1228770 V. Description of the invention (11) The polishing liquid and the semiconductor wafer 50 are dried, and the method for grinding and cleaning the semiconductor wafer 50 according to the present invention is completed. Compared with the conventional technology, the present invention uses the surface chemical mechanical polishing process and the crystal edge chemical mechanical polishing process to respectively grind the first material layer 52 on the upper surface 50a to the first thickness and completely remove the crystal edges. The second material layer 54 on the surface 50b, and the used crystal edge chemical mechanical polishing mechanism 60 includes at least one polishing pad 64, so that it can be produced without adding additional equipment or process stations. The same machine is used for the surface cleaning and polishing process and the crystal edge grinding and cleaning process. Therefore, the technology provided by the present invention including the surface chemical mechanical polishing process and the crystal edge chemical mechanical polishing process is an extreme Practical full-featured U 1 1 -in-One) semiconductor wafer polishing technology. In addition, since the present invention uses the crystal edge chemical mechanical polishing process to completely remove the second material layer 54 on the crystal edge surface 50b, the rough longitude of the crystal edge surface 50b can be reduced, thereby avoiding conventional techniques. The remaining second material layer

Page 17 1228770 V. Description of the invention (12) In the subsequent system, due to thermal stress (t h e r m a 1 s t r e s s) peeling (pealing) generates flakes, which causes the problem of contaminating the product and affecting the performance of the product. The above are only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

1228770 Brief description of the drawings Brief description of the drawings Figure 1 is a schematic top view of the semiconductor wafer to be ground and cleaned in the conventional method for grinding and cleaning a semiconductor wafer. FIG. 2 is a schematic cross-sectional view of the semiconductor wafer to be ground and cleaned in the conventional method for grinding and cleaning the semiconductor wafer. FIG. 3 is a schematic diagram of a conventional chemical mechanical grinding mechanism for grinding and cleaning the semiconductor wafer. FIG. 4 is a schematic cross-sectional view of the semiconductor wafer after the conventional method of grinding and cleaning the semiconductor wafer is completed. FIG. 5 is a schematic top view of the semiconductor wafer to be ground and cleaned in the method for grinding and cleaning a semiconductor wafer according to the present invention. FIG. 6 is a schematic cross-sectional view of the semiconductor wafer to be ground and cleaned in the method for grinding and cleaning the semiconductor wafer according to the present invention. FIG. 7 is a schematic cross-sectional view of a semiconductor wafer 50 after the surface chemical mechanical polishing process and the surface cleaning process are performed. FIG. 8 is a schematic diagram of a crystal edge chemical mechanical polishing mechanism used in the full-function semiconductor wafer polishing process of the present invention. FIG. 9 is a schematic diagram of a method of chemical-mechanical polishing of crystal edges included in the full-function semiconductor wafer polishing process of the present invention. Description of Symbols for Drawings 10 Upper Surface of Semiconductor Wafer 10a

Page 19 1228770 Brief description of the diagram 10b Crystal edge surface 10c Lower surface 1 Obi Upper bevel 1 0b2 Lower bevel 1 0b3 Side edge 12 First material layer 14 Second material layer 16 Positioning gap σ 20 Chemical mechanical polishing mechanism 22 Grinding Platform 24 Polishing pad 26 Cleaning liquid supply tube 28 Wafer carrier 30 Polishing slurry supply tube 32 Adjusting ΛΛ * ie 50 Semiconductor wafer 50a Upper surface 50b Crystal edge surface 50c Lower surface 50bl Upper bevel 50b2 Lower bevel 50b3 Side edge 52 One material layer 54 Second material layer 56 Positioning defect a 60 Edge chemical mechanical polishing mechanism 62 Wafer carrier 64 Polishing polishing pad 66 Positioning rod 68 Roller 70 Upper bevel polishing pad 72 Lower bevel polishing pad 74 Side polishing pad 76 Slurry supply pipe 78 Cleaning liquid supply pipe

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Claims (1)

1228770 6. Scope of patent application 1. A full-function (al 1-in-one) semiconductor wafer polishing process, the semiconductor wafer is placed on a polishing platform of a chemical mechanical polishing device (CMP device) (Polishing platen), the semiconductor wafer includes a top surface, a bottom surface, and an edge bevel surface, and the crystal edge surface includes a front side bevel, a A bevel and an edge, the semiconductor wafer further includes at least a first material layer formed on the upper surface and a second material layer formed on the upper surface On the surface of the crystal edge, the polishing process includes the following steps: A polishing pad is used to perform a surface CMP process to remove the first material layer on the upper surface to a First thickness; performing a rim CMP process to completely remove the upper bevel, the lower bevel and the side The second material layer on the substrate; performing a first cleaning process to clean the upper surface, the upper bevel, the lower bevel, and the side and crystal plane of the semiconductor wafer; and drying the Semiconductor wafer. 2. The grinding process according to item 1 of the patent application, wherein each of the first and second material layers comprises a dielectric layer or a metal layer. 1228770 6. Scope of patent application 3. The grinding process of item 1 in the scope of patent application, wherein the method of forming the first and second material layers includes a chemical vapor deposition (CVD) process or a copper process. Electric copper plating (ECP) process. 4. The polishing process of item 1 in the patent application scope, wherein the surface chemical mechanical polishing process and the crystal edge chemical mechanical polishing process are both after adding a slurry (s 1 urry) to the semiconductor wafer, using the chemical This is done with a mechanical grinding mechanism. 5. The polishing process according to item 4 of the patent application scope, wherein the crystal edge chemical mechanical polishing process uses at least one front side bevel pad and at least one bevel polishing of the chemical mechanical polishing mechanism, respectively. The backside bevel pad and at least one side edge polishing pad (ground pad) grind the upper bevel, the lower bevel, and the side of the semiconductor wafer, respectively, to completely remove the second material layer. 6 · If the polishing process of item 4 of the patent scope is applied, after the surface chemical mechanical polishing process is performed, a second cleaning (second c 1 e a n i n g) process is required to clean the upper surface of the semiconductor wafer. Page 22 1228770 VI. Patent application scope water, DI water) to remove the flakes and residuals of the first and second material layers on the upper surface and the edge surface of the semiconductor wafer The slurry. 8. If the polishing process of item 7 of the patent scope is applied, after the second cleaning process is completed, a buffing polishing of the upper surface of the semiconductor wafer by a buffing pad is required. )Process. 9. A full-function grinding device for grinding a semiconductor wafer, the semiconductor wafer including an upper surface, a lower surface, and a crystal edge surface, the crystal edge surface including an upper bevel, a lower bevel, and a side edge, the semiconductor The wafer further includes at least a first material layer formed on the upper surface and a second material layer formed on the crystal edge surface. The device includes: a polishing platform; and a wafer carrier for carrying the semiconductor wafer. A polishing pad for polishing the material layer on the upper surface of the semiconductor wafer to a first thickness; a positioning rod for positioning the coordinates of the semiconductor wafer on the wafer carrier; a plurality of rollers (ro 1 1 er) for strengthening and fixing the semiconductor wafer on the wafer carrier; at least one upper bevel polishing pad for completely removing the second material layer on the upper bevel of the semiconductor wafer; Page 23 1228770 6. The scope of the patent application is at least one bevel polishing pad to completely remove the second material layer on the lower bevel of the semiconductor wafer; at least one edge polishing pad to completely remove the semiconductor wafer The second material layer on the side; and at least one polishing slurry supply pipe for providing a polishing slurry on the semiconductor wafer and the polishing pad, the upper bevel polishing pad, the lower bevel polishing pad, and the Between the side polishing pads; and at least one cleaning liquid supply pipe for providing a cleaning liquid for cleaning the semiconductor wafer. 10. The device according to item 9 of the patent application scope, wherein the side of the semiconductor wafer includes a positioning notch for interacting with the positioning rod to position the coordinates of the semiconductor wafer on the wafer carrier. 11. The device according to item 9 of the scope of patent application, wherein each of the first and second material layers comprises a dielectric layer or a metal layer. 1 2. The device according to item 9 of the patent application, wherein the method of forming the first and second material layers comprises a chemical vapor deposition process or a copper electroplating process. 1 3. The device according to item 9 of the scope of patent application, wherein the cleaning liquid is deionized water for cleaning the upper surface, the upper bevel, the lower bevel, and the side of the semiconductor wafer to remove The above table of the semiconductor wafer Page 24 1228770 VI. Scope of patent application The residue of the surface, the upper bevel, the lower bevel and the first and second material layers on the side and the residual slurry. 14. The device according to item 9 of the scope of patent application, wherein the full-function polishing device includes a polishing pad for performing a polishing process on the upper surface of the semiconductor wafer. 1 5. A full-function semiconductor wafer polishing process. The semiconductor wafer is placed on a polishing platform of a chemical mechanical polishing mechanism. The semiconductor wafer includes an upper surface, a lower surface, and a crystal edge surface. The crystal edge The surface includes an upper bevel, a lower bevel, and a side, and the side includes a positioning gap for interacting with a positioning rod of the chemical mechanical polishing mechanism to position the semiconductor wafer on the wafer carrier. Coordinate, the semiconductor wafer further includes at least a first material layer formed on the upper surface and a second material layer formed on the crystal edge surface. The grinding process includes the following steps: ^ performing a chemical edge mechanical polishing of the crystal edge Process to completely remove the upper bevel, the lower bevel, and the second material layer on the side; perform a first cleaning process to clean the upper surface, the upper bevel, and the bottom of the semiconductor wafer The bevel and the side; and drying the semiconductor wafer. 16. The grinding process according to item 15 of the scope of patent application, wherein each of the first and second material layers includes a dielectric layer or a metal layer. Page 25 1228770 6. Scope of patent application 1 7. The grinding process according to item 15 of the scope of patent application, wherein the method of forming the first and second material layers includes a chemical vapor deposition process or a copper electroplating process. 18 · According to the polishing process of claim 15 in the scope of patent application, wherein the method includes a polishing pad to remove the first surface on the upper surface before the crystal edge chemical mechanical polishing process is performed. The surface chemical mechanical polishing process from the material layer to a first thickness, and the surface chemical mechanical polishing process is performed by adding a polishing slurry to the semiconductor wafer, using the chemical mechanical polishing mechanism, and after performing the surface chemical After the mechanical polishing process, a second cleaning process is required to clean the upper surface of the semiconductor wafer with deionized water. 19. The polishing process according to item 18 of the scope of patent application, wherein after the second cleaning process is completed, a polishing polishing process is further performed on the upper surface of the semiconductor wafer with a polishing pad. 20. The grinding process according to item 15 of the scope of patent application, wherein the method after performing the crystal edge chemical mechanical grinding process comprises a grinding process to remove the first surface on the upper surface. The surface chemical mechanical polishing process from the material layer to a first thickness, and the surface chemical mechanical polishing process is performed by adding a polishing slurry to the semiconductor wafer, using the chemical mechanical polishing mechanism, and after performing the surface chemical machine Page 26 1228770 6. Scope of patent application After the mechanical grinding process, a second cleaning process is required to clean the upper surface of the semiconductor wafer with deionized water. 2 1. If the polishing process of item 20 of the scope of patent application is applied, after the second cleaning process is completed, a polishing process is further performed on the upper surface of the semiconductor wafer by a polishing pad. 2 2. The polishing process according to item 15 of the scope of patent application, wherein the crystal edge chemical mechanical polishing process uses at least one upper-angle bevel grind of the chemical mechanical polishing mechanism, at least one lower-angle bevel polishing pad, and at least one side. Edge grinding: grinding the upper bevel, the lower bevel, and the side of the semiconductor wafer respectively to completely remove the second material layer. 2 3. The polishing process according to item 22 of the patent application scope, wherein the crystal edge chemical mechanical polishing process is performed by adding a polishing slurry to the semiconductor wafer and then using the chemical mechanical polishing mechanism. 2 4. The method according to item 23 of the scope of patent application, wherein the crystal edge cleaning process is performed using a deionized water to remove residues and residues of the second material layer on the surface of the crystal edge of the semiconductor wafer. The slurry. Page 27