TWI228770B - All-in-one polishing process for a semiconductor wafer - Google Patents

All-in-one polishing process for a semiconductor wafer Download PDF

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TWI228770B
TWI228770B TW93101410A TW93101410A TWI228770B TW I228770 B TWI228770 B TW I228770B TW 93101410 A TW93101410 A TW 93101410A TW 93101410 A TW93101410 A TW 93101410A TW I228770 B TWI228770 B TW I228770B
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semiconductor wafer
polishing
bevel
material layer
patent application
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TW93101410A
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Chinese (zh)
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TW200525623A (en
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Mu-Liang Liao
Chi-Piao Cheng
Te-Sung Hung
Yung-Chieh Kuo
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United Microelectronics Corp
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Abstract

A semiconductor wafer has a top surface and an edge bevel surface, and a first material layer and a second material layer are respectively formed on the top surface and the edge bevel surface. A surface chemical mechanical polishing (surface CMP) process is performed to polish and remove portions of the first material layer down to a first thickness, and a rim CMP process is performed to completely remove the second material layer on the edge bevel surface down to the edge bevel surface thereafter to achieve a smooth surface of the edge bevel surface. Finally, a chemical cleaning process is performed to clean the rim surface and the top surface, and the semiconductor wafer is dried thereafter.

Description

1228770 五、發明說明(1) 【發明所屬之技術領域】 本發明提供一種全功能式半導體晶片研磨製程,尤指一 種利用兩次化學機械研磨(c h e m i c a 1 m e c h a n i c a 1 pol i shi ng,CMP )製程分別研磨該半導體晶片之一上表 面(top surface)與一晶邊表面(edge bevel surface )後,再清洗並乾燥該半導體晶片的方法。 【先前技術】 目前’多層金屬化製程(multilevel metallization process ),這種利用複數層的金屬内連線層以及介電常 數較低之介電材料(dielectrics)來將半導體晶片上之 各個半導體元件彼此串接起來而完成整個堆疊化之迴路 架構,已被廣泛地應用在超大型積體電路(very large scale integration ’VLSI)的製程上。然而在一般製程 中,這些金屬線及半導體元件會使積體電路的表面呈現 高低起伏的陡靖形貌(severe topography),增加後續 在進行沉積或圖案轉移(pattern transfer)製程時, 產生有突懸(overhang)、孔洞(void)或者聚焦不易 以及蝕刻困難等缺點。所以在進入深次微米的半導體製 程之後,半導體業者大多會使用平坦化效果較佳的化學 機械研磨(chemical mechanical polishing,CMP)製 程來均勻地去除一半導體晶片上具有不規則表面的目標1228770 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention provides a full-function semiconductor wafer polishing process, especially a process using two chemical mechanical polishing (chemica 1 mechanica 1 pol i shi ng, CMP) processes. A method of grinding one top surface and one edge bevel surface of the semiconductor wafer, and then cleaning and drying the semiconductor wafer. [Previous technology] At present, a 'multilevel metallization process', which uses a plurality of layers of metal interconnect layers and dielectric materials (dielectrics) having a lower dielectric constant to connect each semiconductor element on a semiconductor wafer to each other It is connected in series to complete the entire stacked circuit architecture, which has been widely used in the process of very large scale integration (VLSI). However, in the general process, these metal lines and semiconductor components will cause the surface of the integrated circuit to show a severe topography of undulations, which increases the occurrence of bumps during subsequent deposition or pattern transfer processes. Disadvantages such as overhang, void, or difficulty in focusing and difficulty in etching. Therefore, after entering the deep sub-micron semiconductor process, most of the semiconductor industry will use chemical mechanical polishing (CMP) process with better planarization effect to uniformly remove targets with irregular surfaces on a semiconductor wafer.

第7頁 1228770 五、發明說明(2) 薄膜層(target thin fi lm ),使半導體晶片在經過化 學機械研磨製程後能夠具有一平坦且規則的表面,達到 半導體晶片表面的全面平坦化,以確保後續製程之良 率0 請參考圖一與圖二,圖一與圖二分別為暨清洗 一半導體晶片1 〇之方法中,待研磨暨清洗^半導體晶片 1 〇之上視示意圖與剖面示意圖。如圖一與圖二所示,半 導體晶片10包含有一上表面(top surface)lOa、一晶 邊表面(edge bevel surface) 10b 與一下表面(bottom surface ) 1 Oc,而晶邊表面10b則包含有一上斜角 (front side bevel )10bl 、 一下斜角(backside bevel ) 10b2與一側邊(edge) 10b3 °上表面l〇a上形成 有至少一待研磨至一第一厚度,且内部包含有至少_ 導體結構(諸如一雙鑲嵌結構或一電容結構等,未顯牛 示)之第一材料層(first material layer) 12,曰 表面1 0 b上則包含有一較第一材料層1 2先形成或與第曰二邊 料層1 2同時形成’卻並非產品所需而待完全去除之第材 材料層(second material layer) 14。其中,第—一 層1 2與第二材料層1 4各可為一由一化學氣相沉積 材料 (chemical vapor deposition ,CVD)製程志一少 (electric copper plating,ECP)製程所形成之 题 層,亦各可為一由一化學氣相沉積製程所形成之介屬 層。通常第一材料層1 2與第二材料層丨4係由兩種相異Page 7 1228770 V. Description of the invention (2) The thin film layer (target thin film) enables the semiconductor wafer to have a flat and regular surface after the chemical mechanical polishing process, so as to achieve a comprehensive planarization of the surface of the semiconductor wafer to ensure that The yield of subsequent processes is 0. Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are respectively a method for cleaning and cleaning a semiconductor wafer 10, and a schematic diagram and a cross-sectional view of the semiconductor wafer 10, to be polished and cleaned. As shown in FIGS. 1 and 2, the semiconductor wafer 10 includes a top surface 10a, an edge bevel surface 10b, and a bottom surface 1 Oc, and the crystal edge surface 10b includes a At least one front side bevel 10bl, one backside bevel 10b2, and one side edge 10b3 are formed on the upper surface 10a to be ground to a first thickness, and the interior includes at least one _ The first material layer 12 of the conductor structure (such as a double damascene structure or a capacitor structure, which is not shown), that is, the surface 1 0 b contains a layer that is formed before the first material layer 12 Or, the second material layer 14 is formed at the same time as the second side material layer 12 which is not required by the product and needs to be completely removed. The first layer 12 and the second material layer 14 may each be a subject layer formed by a chemical vapor deposition (CVD) process and an electric copper plating (ECP) process. Each can also be an interposer formed by a chemical vapor deposition process. Generally, the first material layer 12 and the second material layer 4 are different from each other.

1228770 五、發明說明(3) 材,所構成,惟視製程進行之實際狀況,第一材料層j 2 與第二材料層1 4亦可由兩種相同之材料所構成。除此之 外’半導體晶片1〇之側邊l〇b3包含有一定位缺口16,用 於在研磨半導體晶片1 0之過程中固定半導體晶片1 〇之座 標。 請參考圖三,圖三 之化學機械研磨機 device,CMP d e v i 機械研磨機構2 〇包 22、一平鋪於研磨 體晶片1 0按壓於研 用以供給研磨半導 (slurry supply 管(cleaning so 1 節研磨墊24表面之 又包含有一支撐部 磨之半導體晶片1 〇 材料層1 2時提供一 液供應管3 2則係用 提供一去離子水( 液(未顯示)。 為習知用以研磨暨清洗半導體晶片1 〇 才籌(chemical mechanical polishing c e ) 2 0之示意圖。如圖三所示,化學 含有一研磨平台(polishing plate) 平台22上之研磨墊24、一用以將半導 磨墊24之上之晶圓載具(head)28、一 體晶片1 0之研磨液之研磨液供應管 tube ) 30、一去離子水或清洗液供應 ution supply tube)26 以及一用來調 調節器(conditioner)32。晶圓載具28 位(holder,未顯示),用以固定待研 。研磨漿供應管3 0係用以於研磨第一 研磨漿(s 1 u r r y,未顯示),而清洗 以於清洗半導體晶片1 〇及研磨塾2 4時 deionized water ,DI water)或清洗 首先’在於半導體晶片l〇之上表面l〇a上加入該研磨漿1228770 V. Description of the invention (3) Materials, composition, but depending on the actual conditions of the process, the first material layer j 2 and the second material layer 14 can also be composed of two identical materials. Besides, the side 10b3 of the semiconductor wafer 10 includes a positioning notch 16 for fixing the coordinates of the semiconductor wafer 10 during the grinding of the semiconductor wafer 10. Please refer to Fig. 3. The chemical mechanical polishing machine device, CMP devi mechanical polishing mechanism 2 package 22, one tiled on the grinding body wafer 10, pressed on the ground to supply the polishing semiconductor (slurry supply tube (cleaning so 1 section) The surface of the polishing pad 24 also includes a semiconductor wafer 10 with a supporting portion for grinding. The material layer 12 is provided with a liquid supply tube 32, which is provided with a deionized water (liquid (not shown)). A schematic diagram of cleaning the semiconductor wafer 100 (chemical mechanical polishing ce) 2 0. As shown in FIG. 3, the chemical contains a polishing pad 24 on a polishing plate platform 22, and a semiconductor polishing pad 24 The above wafer carrier (head) 28, the polishing liquid supply tube tube 30 of the polishing liquid of the integrated wafer 10, a deionized water or cleaning solution supply tube 26, and a conditioner 32. The wafer carrier has a 28-position (holder, not shown) for fixing to be researched. The slurry supply pipe 30 is used to grind the first slurry (s 1 urry, not shown), and clean for cleaning semiconductors. crystal Wafer 1 〇 and grinding 塾 2 4 Deionized water (DI water) or cleaning First of all, the polishing slurry is added on the top surface 10a of the semiconductor wafer 10

12287701228770

後’依據產品要灰夕招★夂 ΓΟ /» ¢-, 研磨墊2 4,對JL # A i n 子機械研磨機構2 0之 岍熘翌*Z4對上表面10a上之第一材料芦 械研磨製程,以去除上矣而】心μ =瑨1 2進仃一化學機 一厚产,再將车道ί 表面1 〇上苐一材料層1 2至該第 之;i塾tLt ft片-10傳送”'不同材質且較軟 供声管2 6所接供下)進订拋光。藉由去離子水或清洗液 (、應目26所知,、之該清洗液,進行一表面清洗拋光 i:二笛:1 Μ )製程’以去除半導體晶片10之上表 ί磨將 材料層12之殘渣(fUke)以及殘餘之該 ,,進行曰化學清洗及乾燥(d r y i n g )製程以清洗及乾 燥半導體晶片1 0 ,而完成習知研磨暨清洗半導體晶片1 〇 之方法’而此時半導體晶片丨〇之剖面示意圖則如圖四所 示0 然而’如圖四所示,在進行完該化學機械研磨製程以去 除上表面10a上之第一材料層12至該第一厚度並清洗半導 體晶片1 0後’非產品所需而應完全去除之第二材料層i 4 卻依然附著於晶邊表面1 〇 b上,使得後續在進行其他的半 導體製程時,第二材料層丨4經常會因為受到熱應力 (thermal stress)或其他因素而發生剝落(pealing) 的現象,進而造成第二材料層14碎裂(crack)而產生碎 屑(f lake )或顆粒(particle )。尤其是當整批 (batch)之半導體晶片放置於化學氣相沉積(chemicalAfter 'according to the product, you need to use the gray star ★ 夂 ΓΟ / »¢-, polishing pad 2 4 for JL # A in sub-mechanical polishing mechanism 2 0 of 岍 熘 翌 * Z4 for the first material on the upper surface 10a by mechanical polishing Process to remove the upper part and the heart μ = 瑨 1 2 into a chemical machine and a thick product, and then drive the lane ο surface 10 to a material layer 12 to the first; i 塾 tLt ft sheet-10 transfer "'Different materials and softer sound tubes 2 and 6 are used for ordering and polishing. With a deionized water or a cleaning solution (as should be known to head 26, the cleaning solution, a surface cleaning polishing i: Second flute: 1 Μ) process' to remove the surface of semiconductor wafer 10, grind the residue (fUke) of material layer 12 and the remaining residue, and perform a chemical cleaning and drying process to clean and dry the semiconductor wafer 1 0, and complete the conventional method of grinding and cleaning semiconductor wafers 10, and the cross-sectional schematic diagram of the semiconductor wafers at this time is shown in Figure 4 0. However, as shown in Figure 4, after the chemical mechanical polishing process is completed, After removing the first material layer 12 on the upper surface 10a to the first thickness and cleaning the semiconductor wafer 10 The second material layer i 4, which is not required for the product and should be completely removed, still adheres to the crystal edge surface 10 b, so that in subsequent subsequent semiconductor processes, the second material layer 4 is often subjected to thermal stress ( thermal stress) or other factors that cause the phenomenon of peeling, which in turn causes the second material layer 14 to crack and generate f lake or particles. Especially when the whole batch (batch) Semiconductor wafers are placed in chemical vapor deposition

1228770 五、發明說明(5) vapor deposition,CVD)機構中進行CVD製程時,位置 相對上方的半導體晶片若發生這種剝落的現象/將會嚴 重污染其他位置相對下方的半導體晶片表面,造成缺陷 (d e f e c t )。此外,在因應製程所需而移動半導體晶片i 〇 時’此一苐一材料層1 4之碎屑亦往往會掉落至半導體曰 片1 0之上表面1 0 a之上而污染產品,進而影響產品的功能 (performance ) 〇 【發明内容】 因此本發明之主要目的在於提供一種全功能式(a丨1 — i n 一 one )之半導體晶片研磨製程,以解決上述習知研磨暨清 洗半導體晶片1 0之方法中,無法完全去除第二材料層1 / 的問題。 胃 在本發明的最佳實施例中,該半導體晶片係置於一化學 機械研磨機構(chemical mechanical polishing device,CMP device)之一晶圓載座(wafer stage) 上’且该半導體晶片包含有一上表面(top surface)、 一下表面(bottom surface)與一晶邊表面(edge bevel surface )。該上表面上形成有一第一材料層 (first material layer),而該晶邊表面上則形成有 一第二材料層(second material layer)。首先利用該 化學機械研磨機構之一研磨墊(polishing pad),進行1228770 V. Description of the invention (5) During the CVD process in a vapor deposition (CVD) mechanism, if this type of peeling occurs on a semiconductor wafer located relatively above / it will seriously contaminate the surface of a semiconductor wafer located relatively below and cause defects ( defect). In addition, when the semiconductor wafer is moved according to the needs of the process, the debris of the material layer 14 is often dropped onto the surface 10 a above the semiconductor chip 10 and contaminates the product, thereby further contaminating the product. Affect the product's function. [Abstract] Therefore, the main purpose of the present invention is to provide a full-function (a 丨 1 — in one) semiconductor wafer polishing process to solve the conventional grinding and cleaning of semiconductor wafers. 1 In the method of 0, the problem of the second material layer 1 / cannot be completely removed. In a preferred embodiment of the present invention, the semiconductor wafer is placed on a wafer stage of a chemical mechanical polishing device (CMP device) and the semiconductor wafer includes an upper surface. (Top surface), bottom surface and edge bevel surface. A first material layer is formed on the upper surface, and a second material layer is formed on the crystal edge surface. First, using a polishing pad of one of the chemical mechanical polishing mechanisms,

1228770 五、發明說明(6) 一表面化學機械研磨(surf ace CMP )製程,以去除該上 表面上之該第一材料層至一第一厚度。接著進行一晶邊 化學機械研磨(rim CMP )製程,以完全去除該晶邊表面 上之該第二材料層。接著進行表面拋光並去除研磨液殘 渣,伴以去離子水或清洗液喷清洗(cleaninS )該半導 體晶片。最後再經以熟知之化學清洗製程以清洗該半導 體晶片,並乾燥該半導體晶片。 由於 學機 至該 層, 洗液 片之 發明 晶邊 製程 本發 械研 第一 且所 供應 該上 所提 化學 之技 明係 磨製 厚度 採用 管而 表面 供之 機械 術, 利用 程, 與完 之該 得以 之第 此一 研磨 乃為 該表面化 分別研磨 全去除該 化學機械 使用同一 二清 包含 洗製 可該 、該 一極為實 製程 學機 該上 晶邊 研磨 機台 程與 表面 化學 用之 械研磨 表面上 表面上 機構又 進行一 該化學 化學機 清洗製 ^ I AL· 全功月匕 製程 之該 之該 包含 清洗 清洗 械研 程與 式研 與該晶邊化 材料層 Φ 第一 第二 有至 該半 製程 磨製 該第 磨技 材料 少一清 導體晶 ,故本 程、該 -—清洗 術。 磨製程 避免習 受到熱 生碎屑 d,ϋ·彳卜舉機械研 除此之外,由於本發明係利用該晶邊1 m丄π ^ u JrL场,因此可 以全去除該晶邊表面上之該第二材枓續& 士 m炎 知技術中,殘存之該第二材料層於後)產 應力(thermal stress)而剝落(Peali^At (flake),進而污染產品並影響產0口的 (performance )的問題01228770 V. Description of the invention (6) A surface chemical mechanical polishing (surf ace CMP) process to remove the first material layer on the upper surface to a first thickness. Next, a crystal edge chemical mechanical polishing (rim CMP) process is performed to completely remove the second material layer on the surface of the crystal edge. Next, the surface is polished and the residue of the polishing liquid is removed, and the semiconductor wafer is cleaned with deionized water or a cleaning liquid spray (cleaninS). Finally, the semiconductor wafer is cleaned by a well-known chemical cleaning process, and the semiconductor wafer is dried. Due to the machine learning to this layer, the invention of the crystal edge manufacturing process of the lotion film was first researched and the technology provided by the chemistry mentioned above is the thickness of the tube. The first grinding that can be achieved is for the surfaceization to separate and completely remove the chemical machinery using the same two clears including washing can, the extremely practical process machine, the upper crystal edge grinding machine, and the surface chemistry. The mechanism on the upper surface of the mechanical polishing surface performs another cleaning process of the chemical-chemical machine ^ I AL. The full power month process includes the cleaning and cleaning process, the type research, and the crystal edge material layer Φ first second Until the half-process grinding the first grinding technology material, there is one less conductor crystal, so this process, the cleaning process. Grinding process avoids thermally generated debris d. In addition to 彳 · 彳 buju mechanical research, the present invention uses the crystal edge 1 m 丄 π ^ u JrL field, so it can completely remove the crystal edge surface. In the second material & technology, the remaining second material layer is later produced thermal stress and peeled off (Peali ^ At (flake)), which contaminates the product and affects the yield of the product. (performance) Questions 0

第12頁 1228770 五、發明說明(7) 【實施方式】 請參考圖五與圖六,圖五與圖六分別為本發明全功能式 (al卜in-one )之半導體晶片研磨製裎中,待研磨暨清 洗之半導體晶片5 0之上視示意圖與剖面示意圖。如圖五 與圖六所示’半導體晶片50包含有一上表面(top surface ) 50a - 一位於半導體晶片5 0之邊緣且寬約數釐 米之晶邊表面(edge bevel surface) 50b與一下表面 (bottom surface) 5 0c,而晶邊表面50b則包含有一上 斜角(front side bevel )50bl 、 一 下斜角(backside bevel )50b2與一側邊(edge) 50b3。上表面50a上形成 有至少一待研磨至一第一厚度,且内部包含有至少一半 導體結構(未顯示)之第一材料層(first material layer )52,而晶邊表面50b上則包含有一較第一材料層 5 2先形成或與第一材料層5 2同時形成,卻並非產品所需 而待完全去除之第二材料層(second material layer) 5 4。其中,晶邊表面5 0 b係於對半導體晶片5 0進行各項製 程時用作一定位(a 1 i gn )半導體晶片5 0之標的,而第一 材料層5 2與第二材料層5 4則係藉由一全覆蓋(f u 1 1 coverage )製程而形成,而各可為一由一化學氣相沉積 (chemical vapor deposition,(:VD)製程或一銅電鍍 (electric copper plating ,ECP)製程所形成之金屬 層,亦各可為一由一化學氣相沉積製程所形成之介電Page 121228770 V. Description of the invention (7) [Embodiment] Please refer to FIG. 5 and FIG. 6. FIG. 5 and FIG. 6 are respectively a full-function semiconductor wafer polishing process of the present invention. Top schematic view and cross-sectional view of a semiconductor wafer 50 to be ground and cleaned. As shown in Figs. 5 and 6, the semiconductor wafer 50 includes a top surface 50a-an edge bevel surface 50b and a bottom surface located at the edge of the semiconductor wafer 50 and a few centimeters wide. ) 5 0c, and the crystal edge surface 50b includes a front side bevel 50bl, a backside bevel 50b2, and an edge 50b3. At least one first material layer 52 is formed on the upper surface 50a to be ground to a first thickness and contains at least one semiconductor structure (not shown). The first material layer 52 is formed first or at the same time as the first material layer 52, but it is not the second material layer 54 that is required for the product and is to be completely removed. Among them, the crystal edge surface 50b is used as a target for positioning (a1ign) the semiconductor wafer 50 during various processes of the semiconductor wafer 50, and the first material layer 52 and the second material layer 5 4 is formed by a full coverage (fu 1 1 coverage) process, and each can be a chemical vapor deposition (: VD) process or an electric copper plating (ECP) The metal layers formed in the process may each be a dielectric formed by a chemical vapor deposition process.

第13頁 1228770 五、發明說明(8) 在本發明之最佳實施例中’第—材料層52與第二材 R >1 -c. S -V ύί'Α ^ Lit 層 η 口 ' 个 竹料層興第二 料層54係由兩種相異之材料所構成,而在本發明之另一 實施例中,第一材料層52與第二材料層54亦;由兩種相 同之材料所構成。除此之外,半導體晶片5〇之側邊5〇b3 包含有一定位缺口 56,用於在研磨與清洗半導體晶片5〇 之過程中固定半導體晶片5 0之座標。 首先’在於半導體晶片50之上表面5〇a上加入一第一研磨 浆(first slurry,未顯示)後,依據產品要求之規 格’進行一表面化學機械研磨(surface chemical mechanical polishing,surface CMP)製程,以去除上 表面5 0a上之第一材料層52至該第一厚度。隨後以去離子 水(deionized water ,DI water)作為一第一清洗液 、(未顯示),於半導體晶片50之上表面50a上進行一表面 清洗(surface cleaning)製程,以去除半導體晶片5〇 之上表面50a上之第一材料層52之殘渣(flake)以及殘 餘之該第一研磨漿。 程如 製。 磨圖 研意 械示 機面 學剖 化之 面50 表片 該晶 完體 行導 進半 在, 為後 七程 圖製 ,洗 七清 圖面 考表 參該 請與 面 表 該 與 程 製 磨a 研ο 石5 械面 機表 學上 化之 面ο 5 表片 該晶 完體 行導 進半 在, ,後 示程 所製 七洗 圖清Page 13 1228770 V. Description of the invention (8) In the preferred embodiment of the present invention, 'the first material layer 52 and the second material R > 1 -c. S -V ύ' Α ^ Lit layer η 口 ' The bamboo material layer and the second material layer 54 are composed of two different materials, and in another embodiment of the present invention, the first material layer 52 and the second material layer 54 are also composed of two identical materials. Made up. In addition, the side 50b3 of the semiconductor wafer 50 includes a positioning notch 56 for fixing the coordinates of the semiconductor wafer 50 during the process of grinding and cleaning the semiconductor wafer 50. First, "a first slurry (not shown) is added to the upper surface 50a of the semiconductor wafer 50, and then a surface chemical mechanical polishing (surface CMP) process is performed according to the specifications required by the product". To remove the first material layer 52 on the upper surface 50a to the first thickness. Subsequently, using deionized water (DI water) as a first cleaning solution (not shown), a surface cleaning process is performed on the upper surface 50a of the semiconductor wafer 50 to remove the semiconductor wafer 50. The flakes of the first material layer 52 on the upper surface 50a and the first polishing slurry remain. Cheng Ru system. Grinding and researching the surface of the machine, the surface of the machine is 50% of the surface, and the crystals are guided halfway through. It is the last seven processes. For the seven-pass process, please refer to the surface process and the system. Grinding a grind ο ο stone 5 mechanical surface machine chemistry on the surface ο 5 surface piece of the crystal body leading into the half-in,, after the show shows the seven washing pictures

整 平 - 為 成 P 表習 該之 與案 程本 製於 磨同 研等 械構 機機 學之 化用 面使 表所 該與 於式 由方 。行 面進 表之 之程 \)y at洗 1 清 C面Leveling-In order to form the P table, the application and procedure should be based on the mechanical aspects of mechanical engineering, such as the Mo Tongyan. The process of entering the surface into the table \) y at 1 clean the C side

第14頁 1228770 五、發明說明(9) 知技術,故在此不另行贅述 請參考 研磨製 mechan 不意圖 一晶圓 (buff 個滾軸 side b bevel 少一研 清洗液 晶圓載 用來與 座6 2上 半導體 於研磨 slurry 半導體 第二清 請參考 製程中 圖八,圖八為用於本發明全功能式之半導體晶片 程中之晶邊化學機械研磨機構(rim chemical ical polishing device ,rim CMP device )60 之 。如圖八所示,晶邊化學機械研磨機構6〇包含有 載具(wafer stage) 62、一拋光研磨墊 ing pad)64、一 定位桿(notch pad)66、複數 (roller ) 68、至少一上斜角研磨塾(front evel pad)70、至少一下斜角研磨墊(backside pad)72、至少一側邊研磨墊(edge pad)74、至 磨聚供應管(slurry supply tube) 76與至少一 供應管(cleaning solution supply tube) 78 。 具6 2係用以承載半導體晶片5 0,而定位桿6 6則係 定位缺口 5 6相作用以定位半導體晶片5 〇在晶圓載 之座標’至於複數個滾軸6 8,則可用以加強固定 晶片5 0於晶圓載座6 2上。研磨漿供應管7 6係用以 第二材料層54時,提供與一第二研磨漿(second j未顯示),而清洗液供應管7 8則係用以於清洗 晶片5 0時提供一由去離子水或化學藥劑所構成之 洗液(未顯示)。 圖九]圖九為本發明全功能式之半導體晶片研磨 所包含之之晶邊化學機械研磨(rim chemicalPage 14 1228770 V. Description of the invention (9) Known technology, so I will not repeat it here. Please refer to the grinding mechan. Not intended for a wafer (buff rollers, side b bevel, less one research, cleaning LCD round load, and the base 6 2 Please refer to FIG. 8 in the manufacturing process for the second clearing of the slurry semiconductor on the semiconductor. FIG. 8 is a rim chemical polishing device (rim CMP device) 60 used in the full-function semiconductor wafer process of the present invention. As shown in FIG. 8, the crystal edge chemical mechanical polishing mechanism 60 includes a wafer stage 62, a polishing pad 64, a notch pad 66, a plurality of rollers 68, and at least one Front bevel pad 70, at least bottom bevel pad 72, at least one edge pad 74, slurry supply tube 76 and at least one Supplying tube (cleaning solution supply tube) 78. The tool 6 2 is used to carry the semiconductor wafer 50, and the positioning rod 66 is used to position the notch 5 6 to position the semiconductor wafer 5 〇 In the coordinates of the wafer, as for the plurality of rollers 6 8, it can be used to strengthen the fixing The wafer 50 is on the wafer carrier 62. The polishing slurry supply pipe 76 is used to provide a second polishing slurry when the second material layer 54 is used (second j is not shown), and the cleaning liquid supply pipe 78 is used to provide a wafer cleaning wafer 50. A lotion made of deionized water or chemicals (not shown). Figure 9] Figure 9 is a full-featured semiconductor wafer polishing of the present invention

第15頁 1228770 五、發明說明(ίο) mechanical polishing ’rim CMP)製程之方法不思圖。 如圖九所示,在於晶邊表面5 〇 b上加入該第二研磨漿’進 行該晶邊化學機械研磨製程,利用化學機械研磨機構6 0 之上斜角研磨塾70、下斜角研磨塾7 2與側邊研磨整7 4分 別研磨半導體晶片5 0之上斜角5 0 b 1、下斜角5 0 b 2與側邊 5 0b3,以完全去除上斜角50bl、下斜角50b2與側邊50b3 之第二材料層54。值得注意的是,為配合上斜角50b 1與 下斜角50b2之斜度(slope ),此時上斜角研磨墊70與下Page 15 1228770 Fifth, the invention description (ίο) mechanical polishing 'rim CMP) process method without thinking. As shown in FIG. 9, the second polishing slurry is added to the crystal edge surface 50 ◦ to perform the chemical mechanical polishing process of the crystal edge, and the chemical mechanical polishing mechanism 60 is used for upper bevel grinding 70 and lower bevel grinding 塾. 7 2 and the side grinding 7 4 grinding the semiconductor wafer 50 above the bevel 5 0 b 1, the lower bevel 5 0 b 2 and the side 5 0b 3 to completely remove the upper bevel 50bl, the lower bevel 50b2 and The second material layer 54 of the side 50b3. It is worth noting that, in order to match the slope of the upper bevel 50b 1 and the lower bevel 50b2, the upper bevel polishing pad 70 and the lower

斜角研磨墊72皆係約與半導體晶片50之間呈15至28度角 (degree )。為使半導體晶片之上表面50a更加平整,此 時可同步或依序利用拋光研磨墊6 4對上表面5 0 a進行一拋 光研磨(buff ing CMP )製程。 隨即進行一晶面暨晶邊清洗或喷洗(s u r f a c e a n d e d g e bevelcleaning)製程清洗半導體晶片50之上斜角5〇bl、 下斜角5 0 b 2與側邊5 0 b 3及晶面,以徹底去除晶邊表面5 〇 b 之上表面50a、上斜角50bl、下斜角50b2與側邊50b3及晶 面上之第二材料層5 4之殘渣以及殘餘之該第二研磨聚。 如圖九所示,在進行完該晶邊化學機械研磨製程、該拋 光研磨製程與該晶邊清洗製程後,半導體晶片5 〇之上斜 角50bl 、下斜角5〇b2與側邊5〇b3及晶面上已無殘存任何 之第二材料層54,如圖九所示。 最後進行一化學清洗及乾燥(d r y i n g )製程以完全去除The bevel polishing pads 72 are formed at an angle of about 15 to 28 degrees with the semiconductor wafer 50. In order to make the upper surface 50a of the semiconductor wafer more flat, a buffing CMP process may be performed on the upper surface 50a simultaneously or sequentially using the polishing pad 64. Then, a crystal surface and crystal edge cleaning or spray cleaning (surfaceandedge bevelcleaning) process is performed to clean the upper bevel 50 bl, the lower bevel 50 b 2 and the side 50 b 3 and the crystal plane of the semiconductor wafer 50 to completely remove Crystal edge surface 50a, the upper surface 50a, the upper oblique angle 50bl, the lower oblique angle 50b2, the side edge 50b3, and the residue of the second material layer 54 on the crystal surface and the remaining second abrasive polymer. As shown in FIG. 9, after the crystal edge chemical mechanical polishing process, the polishing and grinding process, and the crystal edge cleaning process are performed, the semiconductor wafer 50 has an upper oblique angle 50bl, a lower oblique angle 50b2, and a side edge 50. There is no second material layer 54 remaining on b3 and the crystal plane, as shown in FIG. 9. Finally, a chemical cleaning and drying (d r y i n g) process is performed to completely remove

第16頁 進暨◦半^程 50磨0磨^製 片研晶研洗^ 日日以體以清 ί導程學於1° 導裝半裝A3由述 半洗對磨i。贅 對清再研行Q行 先邊,光it片另 以晶匕拋#'晶不 可該50該t體此 亦與面與i導在 ,程表程#半故 , 中製邊製3燥, 例磨晶磨50乾述 施研之研面暨所 實械50械表洗前 一機片機上清如 另學晶學之以皆 之化體化50程式 明邊導面片製方 發晶半表晶燥行 本該洗該體乾進 在行清行導該之 1228770 五、發明說明(11) 研磨液並乾燥半導體晶片5 0,而完成本發明研磨暨清洗 半導體晶片5 0之方法。 相較於習知技術,本發明係利用該表面化學機械研磨製 程與該晶邊化學機械研磨製程,分別研磨上表面5 〇 a上之 第一材料層52至該第一厚度與完全去除晶邊表面50b上之 第二材料層5 4,且所採用之晶邊化學機械研磨機構6 0又 包含有至少一拋光研磨墊6 4而得以在不必增加額外設備 或製程站別等生產成本的前提下,使用同一機台進行該 表面清洗拋光製程與該晶邊研磨清洗製程,故本發明所 提供之此一包含可該表面化學機械研磨製程與該晶邊化 學機械研磨製程之技術,乃為一極為實用之全功能式 U 1 1 - i n - 〇 n e )之半導體晶片研磨技術。除此之外,由 於本發明係利用該晶邊化學機械研磨製程以全去除晶邊 表面50b上之第二材料層54,因此可降低晶邊表面50b之 粗經度,進而避免習知技術中,殘存之第二材料層丨4於P.16 ◦ Half-pass 50 mills 0 mill ^ Production of film research crystal research and washing ^ Day to day to learn to learn ί Leadership learn at 1 ° Guide assembly half-load A3 from the half-wash on grinding i. I ’m going to study Q in advance. I ’m going to use the crystal dart # '晶 不可 50 The body is also guided by the surface and i. For example, grinding crystal grinding 50 dry research and research of the research surface and the actual machine 50 mechanical table washing the previous machine, the supernatant of the machine as if you learned crystallography, the incarnation, 50 program bright edge guide sheet, square hair crystal half table The crystal drying line should wash the body and dry it in the clearing line. 1228770 V. Description of the invention (11) The polishing liquid and the semiconductor wafer 50 are dried, and the method for grinding and cleaning the semiconductor wafer 50 according to the present invention is completed. Compared with the conventional technology, the present invention uses the surface chemical mechanical polishing process and the crystal edge chemical mechanical polishing process to respectively grind the first material layer 52 on the upper surface 50a to the first thickness and completely remove the crystal edges. The second material layer 54 on the surface 50b, and the used crystal edge chemical mechanical polishing mechanism 60 includes at least one polishing pad 64, so that it can be produced without adding additional equipment or process stations. The same machine is used for the surface cleaning and polishing process and the crystal edge grinding and cleaning process. Therefore, the technology provided by the present invention including the surface chemical mechanical polishing process and the crystal edge chemical mechanical polishing process is an extreme Practical full-featured U 1 1 -in-One) semiconductor wafer polishing technology. In addition, since the present invention uses the crystal edge chemical mechanical polishing process to completely remove the second material layer 54 on the crystal edge surface 50b, the rough longitude of the crystal edge surface 50b can be reduced, thereby avoiding conventional techniques. The remaining second material layer

第17頁 1228770 五、發明說明(12) 後續製中因為受到熱應力(t h e r m a 1 s t r e s s )而剝落 (pealing )產生碎屑(flake),所導致污染產品並影 響產品的功能(performance)的問題。 以上所述僅本發明之較佳實施例,凡依本發明申請專利 範圍所做之均等變化與修飾,皆應屬本發明專利之涵蓋 範圍。Page 17 1228770 V. Description of the invention (12) In the subsequent system, due to thermal stress (t h e r m a 1 s t r e s s) peeling (pealing) generates flakes, which causes the problem of contaminating the product and affecting the performance of the product. The above are only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

1228770 圖式簡單說明 圖式之簡單說明 圖一為習知研磨暨清洗一半導體晶片之方法中,待研磨 暨清洗之該半導體晶片之上視示意圖。 圖二為習知研磨暨清洗該半導體晶片之方法中,待研磨 暨清洗之該半導體晶片之剖面示意圖。 圖三為習知用以研磨暨清洗該半導體晶片之化學機械研 磨機構之示意圖。 圖四為完成習知研磨暨清洗該半導體晶片之方法後之該 半導體晶片之剖面示意圖。 圖五為本發明研磨暨清洗一半導體晶片之方法中,待研 磨暨清洗之該半導體晶片之上視示意圖。 圖六為本發明研磨暨清洗該半導體晶片之方法中,待研 磨暨清洗之該半導體晶片之剖面示意圖。 圖七為在進行完該表面化學機械研磨製程與該表面清洗 製程後,半導體晶片5 0之剖面示意圖。 圖八為用於本發明全功能式之半導體晶片研磨製程中之 晶邊化學機械研磨機構之示意圖。 圖九為本發明全功能式之半導體晶片研磨製程中所包含 之晶邊化學機械研磨製程之方法示意圖。 圖式之符號說明 10 半導體晶片 10a 上表面1228770 Brief description of the drawings Brief description of the drawings Figure 1 is a schematic top view of the semiconductor wafer to be ground and cleaned in the conventional method for grinding and cleaning a semiconductor wafer. FIG. 2 is a schematic cross-sectional view of the semiconductor wafer to be ground and cleaned in the conventional method for grinding and cleaning the semiconductor wafer. FIG. 3 is a schematic diagram of a conventional chemical mechanical grinding mechanism for grinding and cleaning the semiconductor wafer. FIG. 4 is a schematic cross-sectional view of the semiconductor wafer after the conventional method of grinding and cleaning the semiconductor wafer is completed. FIG. 5 is a schematic top view of the semiconductor wafer to be ground and cleaned in the method for grinding and cleaning a semiconductor wafer according to the present invention. FIG. 6 is a schematic cross-sectional view of the semiconductor wafer to be ground and cleaned in the method for grinding and cleaning the semiconductor wafer according to the present invention. FIG. 7 is a schematic cross-sectional view of a semiconductor wafer 50 after the surface chemical mechanical polishing process and the surface cleaning process are performed. FIG. 8 is a schematic diagram of a crystal edge chemical mechanical polishing mechanism used in the full-function semiconductor wafer polishing process of the present invention. FIG. 9 is a schematic diagram of a method of chemical-mechanical polishing of crystal edges included in the full-function semiconductor wafer polishing process of the present invention. Description of Symbols for Drawings 10 Upper Surface of Semiconductor Wafer 10a

第19頁 1228770 圖式簡單說明 10b 晶 邊 表 面 10c 下 表 面 1 Obi 上 斜 角 1 0b2 下 斜 角 1 0b3 侧 邊 12 第 一 材 料 層 14 第 二 材 料 層 16 定 位 缺 σ 20 化 學 機 械 研 磨機 構22 研 磨 平 台 24 研 磨 墊 26 清 洗 液 供 應 管 28 晶 圓 載 具 30 研 磨 漿 供 應 管 32 調 ΛΛ* 即 器 50 半 導 體 晶 片 50a 上 表 面 50b 晶 邊 表 面 50c 下 表 面 50bl 上 斜 角 50b2 下 斜 角 50b3 側 邊 52 第 一 材 料 層 54 第 二 材 料 層 56 定 位 缺 a 60 邊 緣 化 學 機 械研磨機構 62 晶 圓 載 具 64 拋 光 研 磨 墊 66 定 位 桿 68 滾 軸 70 上 斜 角 研 磨 墊 72 下 斜 角 研 磨 墊 74 側 邊 研 磨 墊 76 研 磨 漿 供 應 管 78 清 洗 液 供 應 管Page 19 1228770 Brief description of the diagram 10b Crystal edge surface 10c Lower surface 1 Obi Upper bevel 1 0b2 Lower bevel 1 0b3 Side edge 12 First material layer 14 Second material layer 16 Positioning gap σ 20 Chemical mechanical polishing mechanism 22 Grinding Platform 24 Polishing pad 26 Cleaning liquid supply tube 28 Wafer carrier 30 Polishing slurry supply tube 32 Adjusting ΛΛ * ie 50 Semiconductor wafer 50a Upper surface 50b Crystal edge surface 50c Lower surface 50bl Upper bevel 50b2 Lower bevel 50b3 Side edge 52 One material layer 54 Second material layer 56 Positioning defect a 60 Edge chemical mechanical polishing mechanism 62 Wafer carrier 64 Polishing polishing pad 66 Positioning rod 68 Roller 70 Upper bevel polishing pad 72 Lower bevel polishing pad 74 Side polishing pad 76 Slurry supply pipe 78 Cleaning liquid supply pipe

第20頁Page 20

Claims (1)

1228770 六、申請專利範圍 1· 一種全功能式(al 1- in-one )之半導體晶片研磨製 程,該半導體晶片係置於一化學機械研磨機構 (chemical mechanical polishing device ,CMP device)之一研磨平台(polishing platen)上,該半 導體晶片包含有一上表面(top surface)、一下表面 (bottom surface)與一晶邊表面(edge bevel surface ),該晶邊表面包含有一上斜角(frontside bevel )、一 下斜角(backside bevel )與一側邊 (edge ),該半導體晶片另包含有至少一第一材料層 (first material layer)形成於該上表面上以及一第 二材料層(second material layer)形成於該晶邊表面 上,該研磨製程包含有下列步驟: 利用一研磨墊(polishing Pad),進行一表面化學機械 研磨(surface CMP)製程,·以去除該上表面上之該第一 材料層至一第一厚度; 進行一晶邊化學機械研磨(rim CMP )製程,以完全去除 該上斜角、該下斜角與該側邊上之該第二材料層; 進行一第一清洗(f i r s t c 1 e a n i n g )製程,以清洗該半 導體晶片之該上表面、該上斜角、該下斜角與該側邊及 晶面;以及 乾燥該半導體晶片。 2 ·如申請專利範圍第1項之研磨製程,其中該第一與第二 材料層各係包含有一介電層或一金屬層。1228770 6. Scope of patent application 1. A full-function (al 1-in-one) semiconductor wafer polishing process, the semiconductor wafer is placed on a polishing platform of a chemical mechanical polishing device (CMP device) (Polishing platen), the semiconductor wafer includes a top surface, a bottom surface, and an edge bevel surface, and the crystal edge surface includes a front side bevel, a A bevel and an edge, the semiconductor wafer further includes at least a first material layer formed on the upper surface and a second material layer formed on the upper surface On the surface of the crystal edge, the polishing process includes the following steps: A polishing pad is used to perform a surface CMP process to remove the first material layer on the upper surface to a First thickness; performing a rim CMP process to completely remove the upper bevel, the lower bevel and the side The second material layer on the substrate; performing a first cleaning process to clean the upper surface, the upper bevel, the lower bevel, and the side and crystal plane of the semiconductor wafer; and drying the Semiconductor wafer. 2. The grinding process according to item 1 of the patent application, wherein each of the first and second material layers comprises a dielectric layer or a metal layer. 1228770 六、申請專利範圍 3.如申請專利範圍第1項之研磨製程,其中形成該第一與 第二材料層之方法係包含有一化學氣相沉積(c h e m i c a 1 vapor deposition ,CVD)製程或一銅電鑛(electric copper plating ,ECP)製程 。 4 .如申請專利範圍第1項之研磨製程,其中該表面化學機 械研磨製程與該晶邊化學機械研磨製程皆係於加入一研 磨漿(s 1 u r r y )至該半導體晶片上後,利用該化學機械 研磨機構來進行。 5.如申請專利範圍第4項之研磨製程,其中該晶邊化學機 械研磨製程係分別以該化學機械研磨機構之至少一上斜 角研磨塾(front side bevel pad) 、至少一下斜角研 磨塾(backside bevel pad)與至少一側邊研磨塾 (edge pad )分別研磨該半導體晶片之該上斜角、該下 斜角與該側邊,以完全去除該第二材料層。 6 ·如申請專利範圍第4項之研磨製程,其中在進行完該表 面化學機械研磨製程後,另需進行一第二清洗(second c 1 e a n i n g )製程,以清洗該半導體晶片之該上表面。1228770 6. Scope of patent application 3. The grinding process of item 1 in the scope of patent application, wherein the method of forming the first and second material layers includes a chemical vapor deposition (CVD) process or a copper process. Electric copper plating (ECP) process. 4. The polishing process of item 1 in the patent application scope, wherein the surface chemical mechanical polishing process and the crystal edge chemical mechanical polishing process are both after adding a slurry (s 1 urry) to the semiconductor wafer, using the chemical This is done with a mechanical grinding mechanism. 5. The polishing process according to item 4 of the patent application scope, wherein the crystal edge chemical mechanical polishing process uses at least one front side bevel pad and at least one bevel polishing of the chemical mechanical polishing mechanism, respectively. The backside bevel pad and at least one side edge polishing pad (ground pad) grind the upper bevel, the lower bevel, and the side of the semiconductor wafer, respectively, to completely remove the second material layer. 6 · If the polishing process of item 4 of the patent scope is applied, after the surface chemical mechanical polishing process is performed, a second cleaning (second c 1 e a n i n g) process is required to clean the upper surface of the semiconductor wafer. 第22頁 1228770 六、申請專利範圍 water,DI water)來進行,以去除該半導體晶片之該上 表面與該晶邊表面上之該第一與第二材料層之殘潰 (flake )以及殘餘之該研磨漿。 8. 如申請專利範圍第7項之研磨製程,其中在完成該第二 清洗製程之後,另需藉由一拋光螯(buffing pad)對該 半導體晶片之該上表面進行一拋光研磨(buff ing polishing)製程。 9. 一種研磨一半導體晶片的全功能式研磨裝置,該半導 體晶片包含有一上表面、一下表面與一晶邊表面,該晶 邊表面包含有一上斜角、一下斜角與一側邊,該半導體 晶片另包含有至少一第一材料層形成於該上表面上以及 一第二材料層形成於該晶邊表面上,該裝置包含有: 一研磨平台; 一晶圓載具,用以承載該半導體晶片, 一研磨墊,用以研磨該半導體晶片之該上表面之該材料 層至一第一厚度; 一定位桿,用以定位該半導體晶片在該晶圓載座上之座 標; 複數個滾軸(ro 1 1 er ),用以加強固定該半導體晶片於 該晶圓載座上; 至少一上斜角研磨墊,用以完全去除該半導體晶片之該 上斜角上之該第二材料層;Page 22 1228770 VI. Patent application scope water, DI water) to remove the flakes and residuals of the first and second material layers on the upper surface and the edge surface of the semiconductor wafer The slurry. 8. If the polishing process of item 7 of the patent scope is applied, after the second cleaning process is completed, a buffing polishing of the upper surface of the semiconductor wafer by a buffing pad is required. )Process. 9. A full-function grinding device for grinding a semiconductor wafer, the semiconductor wafer including an upper surface, a lower surface, and a crystal edge surface, the crystal edge surface including an upper bevel, a lower bevel, and a side edge, the semiconductor The wafer further includes at least a first material layer formed on the upper surface and a second material layer formed on the crystal edge surface. The device includes: a polishing platform; and a wafer carrier for carrying the semiconductor wafer. A polishing pad for polishing the material layer on the upper surface of the semiconductor wafer to a first thickness; a positioning rod for positioning the coordinates of the semiconductor wafer on the wafer carrier; a plurality of rollers (ro 1 1 er) for strengthening and fixing the semiconductor wafer on the wafer carrier; at least one upper bevel polishing pad for completely removing the second material layer on the upper bevel of the semiconductor wafer; 第23頁 1228770 六、申請專利範圍 至少一下斜角研磨墊,用以完全去除該半導體晶片之該 下斜角上之該第二材料層; 至少一侧邊研磨墊,用以完全去除該半導體晶片之該側 邊上之該第二材料層;以及 至少一研磨漿供應管,用以提供一研磨漿於該半導體晶 片與該研磨墊、該上斜角研磨墊、該下斜角研磨墊以及 該側邊研磨墊之間;以及 至少一清洗液供應管,用以提供一清洗該半導體晶片用 之清洗液。 1 0.如申請專利範圍第9項之裝置,其中該半導體晶片之 該側邊包含有一定位缺口 ,用於與該定位桿相作用,以 定位該半導體晶片在該晶圓載座上之座標。 1 1 .如申請專利範圍第9項之裝置,其中該第一與第二材 料層各係包含有一介電層或一金屬層。 1 2.如申請專利範圍第9項之裝置,其中形成該第一與第 二材料層之方法係包含有一化學氣相沉積製程或一銅電 鍍製程。 1 3.如申請專利範圍第9項之裝置,其中該清洗液係為去 離子水,用以清洗該半導體晶片之該上表面、該上斜 角、該下斜角與該側邊,以去除該半導體晶片之該上表Page 23 1228770 6. The scope of the patent application is at least one bevel polishing pad to completely remove the second material layer on the lower bevel of the semiconductor wafer; at least one edge polishing pad to completely remove the semiconductor wafer The second material layer on the side; and at least one polishing slurry supply pipe for providing a polishing slurry on the semiconductor wafer and the polishing pad, the upper bevel polishing pad, the lower bevel polishing pad, and the Between the side polishing pads; and at least one cleaning liquid supply pipe for providing a cleaning liquid for cleaning the semiconductor wafer. 10. The device according to item 9 of the patent application scope, wherein the side of the semiconductor wafer includes a positioning notch for interacting with the positioning rod to position the coordinates of the semiconductor wafer on the wafer carrier. 11. The device according to item 9 of the scope of patent application, wherein each of the first and second material layers comprises a dielectric layer or a metal layer. 1 2. The device according to item 9 of the patent application, wherein the method of forming the first and second material layers comprises a chemical vapor deposition process or a copper electroplating process. 1 3. The device according to item 9 of the scope of patent application, wherein the cleaning liquid is deionized water for cleaning the upper surface, the upper bevel, the lower bevel, and the side of the semiconductor wafer to remove The above table of the semiconductor wafer 第24頁 1228770 六、申請專利範圍 面、該上斜角、該下斜角與該側邊上之該第一與第二材 料層之殘渣以及殘餘之該研磨漿。 1 4.如申請專利範圍第9項之裝置,其中該全功能式研磨 裝置包含有一拋光墊,用於對該半導體晶片之該上表面 進行一拋光研磨製程。 1 5. —種全功能式之半導體晶片研磨製程,該半導體晶片 係置於一化學機械研磨機構之一研磨平台上,該半導體 晶片包含有一上表面、一下表面與一晶邊表面,該晶邊 表面包含有一上斜角、一下斜角與一側邊,該側邊包含 有一定位缺口,用於與該化學機械研磨機構之一定位桿 相作用、,以定位該半導體晶片在該晶圓載座上之座標, 該半導體晶片另包含有至少一第一材料層形成於該上表 面以及一第二材料層形成於該晶邊表面上,該研磨製程 包含有下列步驟: ^ 進行一晶邊化學機械研磨製程,以完全去除該上斜角、 該下斜角與該側邊上之該第二材料層; 進行一第一清洗製程,以清洗該半導體晶片之該上表 面、該上斜角、該下斜角與該側邊;以及 乾燥該半導體晶片。 1 6.如申請專利範圍第1 5項之研磨製程,其中該第一與第 二材料層各係包含有一介電層或一金屬層。Page 24 1228770 VI. Scope of patent application The residue of the surface, the upper bevel, the lower bevel and the first and second material layers on the side and the residual slurry. 14. The device according to item 9 of the scope of patent application, wherein the full-function polishing device includes a polishing pad for performing a polishing process on the upper surface of the semiconductor wafer. 1 5. A full-function semiconductor wafer polishing process. The semiconductor wafer is placed on a polishing platform of a chemical mechanical polishing mechanism. The semiconductor wafer includes an upper surface, a lower surface, and a crystal edge surface. The crystal edge The surface includes an upper bevel, a lower bevel, and a side, and the side includes a positioning gap for interacting with a positioning rod of the chemical mechanical polishing mechanism to position the semiconductor wafer on the wafer carrier. Coordinate, the semiconductor wafer further includes at least a first material layer formed on the upper surface and a second material layer formed on the crystal edge surface. The grinding process includes the following steps: ^ performing a chemical edge mechanical polishing of the crystal edge Process to completely remove the upper bevel, the lower bevel, and the second material layer on the side; perform a first cleaning process to clean the upper surface, the upper bevel, and the bottom of the semiconductor wafer The bevel and the side; and drying the semiconductor wafer. 16. The grinding process according to item 15 of the scope of patent application, wherein each of the first and second material layers includes a dielectric layer or a metal layer. 第25頁 1228770 六、申請專利範圍 1 7.如申請專利範圍第1 5項之研磨製程,其中形成該第一 與第二材料層之方法係包含有一化學氣相沉積製程或一 銅電鍍製程。 1 8 ·如申請專利範圍第1 5項之研磨製程,其中該方法在進 行該晶邊化學機械研磨製程之前,係包含有一利用一研 磨墊所進行,用以去除該上表面上之該第一材料層至一 第一厚度之表面化學機械研磨製程,且該表面化學機械 研磨製程係於加入一研磨漿至該半導體晶片上後,利用 該化學機械研磨機構來進行,而在進行完該表面化學機 械研磨製程後,另需進行一第二清洗製程,以利用一去 離子水清洗該半導體晶片之該上表面。 1 9.如申請專利範圍第1 8項之研磨製程,其中在完成該第 二清洗製程之後,另需藉由一拋光墊對該半導體晶片之 該上表面進行一拋光研磨製程。 2 0 .如申請專利範圍第1 5項之研磨製程,其中該方法在進 行該晶邊化學機械研磨製程之後,係包含有一利用一研 磨塾所進行,用以去除該上表面上之該第一材料層至一 第一厚度之表面化學機械研磨製程,且該表面化學機械 研磨製程係於加入一研磨漿至該半導體晶片上後,利用 該化學機械研磨機構來進行,而在進行完該表面化學機Page 25 1228770 6. Scope of patent application 1 7. The grinding process according to item 15 of the scope of patent application, wherein the method of forming the first and second material layers includes a chemical vapor deposition process or a copper electroplating process. 18 · According to the polishing process of claim 15 in the scope of patent application, wherein the method includes a polishing pad to remove the first surface on the upper surface before the crystal edge chemical mechanical polishing process is performed. The surface chemical mechanical polishing process from the material layer to a first thickness, and the surface chemical mechanical polishing process is performed by adding a polishing slurry to the semiconductor wafer, using the chemical mechanical polishing mechanism, and after performing the surface chemical After the mechanical polishing process, a second cleaning process is required to clean the upper surface of the semiconductor wafer with deionized water. 19. The polishing process according to item 18 of the scope of patent application, wherein after the second cleaning process is completed, a polishing polishing process is further performed on the upper surface of the semiconductor wafer with a polishing pad. 20. The grinding process according to item 15 of the scope of patent application, wherein the method after performing the crystal edge chemical mechanical grinding process comprises a grinding process to remove the first surface on the upper surface. The surface chemical mechanical polishing process from the material layer to a first thickness, and the surface chemical mechanical polishing process is performed by adding a polishing slurry to the semiconductor wafer, using the chemical mechanical polishing mechanism, and after performing the surface chemical machine 第26頁 1228770 六、申請專利範圍 械研磨製程後,另需進行一第二清洗製程,以利用一去 離子水清洗該半導體晶片之該上表面。 2 1 .如申請專利範圍第2 0項之研磨製程,其中在完成該第 二清洗製程之後,另需藉由一拋光墊對該半導體晶片之 該上表面進行一拋光研磨製程。 2 2.如申請專利範圍第1 5項之研磨製程,其中該晶邊化學 機械研磨製程係分別以該化學機械研磨機構之至少一上 斜角研磨塾、至少一下斜角研磨墊與至少一側邊研磨塾 分別研磨該半導體晶片之該上斜角、該下斜角與該側 邊,以完全去除該第二材料層。 2 3.如申請專利範圍第2 2項之研磨製程,其中該晶邊化學 機械研磨製程係於加入一研磨漿至該半導體晶片上後, 利用該化學機械研磨機構來進行。 2 4.如申請專利範圍第2 3項之方法,其中該晶邊清洗製程 係利用一去離子水來進行,以去除該半導體晶片之該晶 邊表面上之該第二材料層之殘渣以及殘餘之該研磨漿。Page 26 1228770 6. Scope of patent application After the mechanical grinding process, a second cleaning process is required to clean the upper surface of the semiconductor wafer with deionized water. 2 1. If the polishing process of item 20 of the scope of patent application is applied, after the second cleaning process is completed, a polishing process is further performed on the upper surface of the semiconductor wafer by a polishing pad. 2 2. The polishing process according to item 15 of the scope of patent application, wherein the crystal edge chemical mechanical polishing process uses at least one upper-angle bevel grind of the chemical mechanical polishing mechanism, at least one lower-angle bevel polishing pad, and at least one side. Edge grinding: grinding the upper bevel, the lower bevel, and the side of the semiconductor wafer respectively to completely remove the second material layer. 2 3. The polishing process according to item 22 of the patent application scope, wherein the crystal edge chemical mechanical polishing process is performed by adding a polishing slurry to the semiconductor wafer and then using the chemical mechanical polishing mechanism. 2 4. The method according to item 23 of the scope of patent application, wherein the crystal edge cleaning process is performed using a deionized water to remove residues and residues of the second material layer on the surface of the crystal edge of the semiconductor wafer. The slurry. 第27頁Page 27
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