TWI224428B - Loop filter capacitor leakage current control - Google Patents

Abstract

A locked loop circuit (470, 900, 1000, 1200) uses a control circuit (488, 514, (952, 954, and 904), (1052, 954, and 904), (1252, 1254, and 1204)) to adjust a leakage current through a loop filter capacitor (206, 306) of the locked loop circuit (470, 900, 1000, 1200). The control circuit (488, 514, (952, 954, and 904), (1052, 954, and 904), (1252, 1254, and 1204)) is responsive to any combination of a phase detector (202, 302), a switch (500, 516, 904), a combinational logic circuit (952, 1052), a test processor unit (1252), and an adjustment circuit (954, 1254).

Description

说明, Description of the invention: [Technical field to which the invention belongs] The present invention relates to # $, Ί 万, lock loop circuits, and in particular, to the leakage of capacitors used to control loop filters in locked loop circuits. Method and device for electric current. [Prior art] As shown in Figure 1, among other components, a typical computer system has a microprocessor (12), multiple types of memory (14), and / or special functions. A's integrated circuit (16b and peripheral computer resources (not shown: output), such as monitors, keyboards, software programs, etc .. These components are, for example, communication such as wire, bus, etc. Path. 9) communicate with each other to accomplish various tasks of the computer system (10). In order to achieve this kind of work properly, the computer system (10) coordinates its various actions on the basis of the nursery. Generate the system clock signal for this ... crystal oscillator J series (known in the art as "Reference 昉 昉 Asian and shown in $ 1 heading &amp; SYS-Clk) to a computer system (various Components. ^ Modern microprocessors and other integrated circuits can operate at frequencies much higher than the clock signal of the system. Therefore, microprocessors (12) are involved in computer systems (10). As with other guarantees, τ <gravity becomes important to use an appropriate and accurate time reference. B is used in the computer system (10) to ensure that the system clock 俨 n and the microprocessor clock One component θ — s, the phase-locked loop (p LL) (2 0) clock generator type between signals (ie, "chip clock signal Z number = chip_clk) at an appropriate time reference. Plq 2 : ζ, ο Kinds of oscillators to control the #% 炎 门 — Chen Ying, quasi holding a phase of the electric Qidou / ° Yingling test brother 1 relative to the system clock t 谠, PLL ( 2〇) The clock signal of this system is A and the input is expected to be (, the clock signal of the n system is its parameter suppression) A chip clock "WT1D Otp, 4 Dudi 1 is shown as-) in the chip is output to the microprocessor (12). The system clock signal and the chip clock signal are controlled by the PLL (2G) The relationship between the phase and frequency of the shirt. This relationship between the phase of the system clock signal and the clock signal of the chip and the frequency car ensures that the various components in the microprocessor 02) can be used-a controlled and Reliable time reference. However, when this relationship is not maintained by the PLL (20), the actions in the computer system will become uncertain. Figure 2 shows a block diagram of a typical PLL.) The The PLL (200) system includes a PLL core (250), a buffer (212, 214, 216, 218), and a feedback loop (221) on the feedback loop path. The buffer (212, 2 14) It is to increase the driving strength of the input pulse (215) to provide a chip clock signal (217) for the other circuits of the microprocessor (12 in the i). The buffers (216, 218) buffer the The chip clock signal (217) is another circuit to the microprocessor (12 in Fig. 1). By the buffer (212 , 214, 216, 2 18) The time delay generated is reflected in the feedback signal (221) supplied to the PLL core (250). The PLL core (250) is designed to output the chip clock signal (2 17), the chip clock signal (217) is a multiple of the system clock signal (201). When the PLL is in "lock", the chip clock signal (217) and the system clock signal (201) are Maintain a specific phase relationship. To allow for different multiplication ratios, 1224428

The loop signal (221) uses a circuit (224) divided by B. A phase-frequency detector (202) aligns the transition edges and frequencies of the clock and% Γ pulse B 仏 (22 3). The word "(202)" adjusts its output frequency so that the clock and pulse A signals (221) are given by. The phase-frequency detection pulse A signal (221) is reduced to zero with any phase and frequency difference between the clock B ^ (223). The phase-frequency detector (202) generates a signal for controlling the charge pump (204, '234) :. The phase-frequency detector (202) uses the control signals up (203) and DOWN (205) to control the charge pump (204, 234) to increase or decrease the output of the charge pump. The charge pump (204) adds or removes charge from a capacitor C1 (206), which changes the potential at the input of the bias generator (208). The 60% Guzhai (206) is connected between the power source Vdd and the control voltage VCTRL (207). The charge pump (234) adds or removes charge to or from a bias voltage VBP (209) of a bias generator (208). The bias generator (208) is responsive to the control voltage (207) to generate bias voltages VBP (209) and Vbn (211). The PLL core (25) can be self-biased by adding a bias voltage Vbp (209) of the charge pump (234) to the bias generator (208). The addition of a second charge pump (234) allows a resistor in series with the capacitor (206) to be removed. The voltage-controlled oscillator (21〇) generates an output # (2 13) with a frequency related to the bias voltage vBp (209) and 1224428 vbn (21 1). ‘Divide, the circuit (220, 222, 224) determines the multiplication factor provided by the PLL core (250). "Division, the addition of the circuit (22, 222, 224) enables the PLL core (250) to multiply the system clock signal (201). When the chip clock signal (2 17) must be higher than the system It is useful to multiply the system clock signal (201) at the frequency of the pulse signal (201).

For example, during normal operation, the variables A and c can be respectively set as the working number B in the circuit (220) of division = A and the circuit (222) divided by c (224 in the circuit divided by b) (224 ) Is set to 0. The phase-frequency detector (202) is aligned with the rotation, crossing edges and frequencies of the clock A signal (221) and the clock B signal (223). The phase-frequency detector (moving) adjusts the frequency of the output clock signal (215) of the PLL core (250), so that any phase between the clock A signal and the clock B signal (223) and The frequency difference drops to zero. Since the clock B signal (223) has a circuit (224) that reduces its input frequency by 0 times, it is divided by B, so the phase and frequency detector (202) adjusts the voltage-controlled oscillator (21〇). The output signal (2ι3) has a frequency of 10 times that of the south and the Japanese pulse A ^ (22 1). Therefore, the chip clock signal (217) is 1 () times higher than the system clock signal ⑽) in frequency. T. The power consumption of the microprocessor is critical. Reducing the frequency of the chip's clock signal (21 7) reduces the switching rate of the other circuits in the microprocessor (I] in the figure). When there is no activity in the microprocessor for a long period of time ', a low power mode can be entered. The slower heart rate typically reduces the power consumption of the microprocessor (12 in Figure i) 1224428. The change in the frequency of the chip clock signal (217) is by changing the frequency in the division circuit (220, 222 , 224). For example, during the action of reducing = rate, the variable A may be set to 16 in the circuit divided by a (㈣; the variable B may be set to ^ in the circuit divided by B (224) and the variable c In the circuit (222) divided by c, it can be: set to 32. In this example, the frequency of the chip clock signal (217) is doubled. At the same time, compared with the above example without reducing power In addition, the frequency updated by the phase-frequency detector (202) is reduced by a factor of M. The appropriate action of the microprocessor (shown in Figure 丨: PT Τ) is dependent on the pulse (20). The relationship between the signal (plus) and the clock of the chip "Waist-shaped Temple" has a fixed phase and frequency relationship. As the frequency of modern computers continues to increase, the need to quickly transfer data between crystals is also ΛΛ. Receiving data, usually when the material should be crying or shaking by receiving. The stalk signal determines whether the asset field receiving circuit is sampled or locked. The /: = sign can be at the beginning of the period when the data is valid. Transition, however, the receiver circuit is in the middle of the valid period "The f signal is when the data can be opened from its transmission point ::,:. At the same time, the transmission of the clock signal can be delayed by a delay lock ... In both cases, a delay lock loop (Or 'Clock signal-a fixed phase relative to the original Figure 3 shows :, the pulse "Tiger. Eight. K # _ ~ a part of Dian Tan's computer system components (100) ... see The information (1M) is from), 叩 34) (also known as "receiver Aon" is transmitted to the pen) In order to assist the transmission of resources, a clock signal (116) is also associated with the information (114) Teleported together. Some circuits may also have a path to transfer data from circuit B (1 34) and the extra-maxillary clock (not shown) to circuit A (i 12). The clock signal 〇1 6) can be changed from one state to another at the beginning of data transmission. Route B (134) requires a clock signal between some &amp; k after the start of valid data in time. . Moreover, the clock signal ⑴6) may have degraded quality during transmission. The DLL has a function to regenerate the clock signal 5 (16) to a valid state and generate a private version of the clock signal (116) for use by other circuits. For example, the receiver circuit = 34) can use the phase-shifted version of the clock signal (116) as the receiver = the sample of the channel. The sampling signal of the receiver circuit determines when the input of the receiver circuit should be sampled. The performance of the DLL is important, so the DLL must maintain an appropriate time reference on the CPU or the integrated circuit in general. Figure 4 is a block diagram showing a typical DLL (300). The clock signal (301) is input to the DLL (300) to produce a phased (ie, delayed ^). The clock signal (301) is turned into a voltage-controlled delay line (3丨 〇) and a phase detector (302). The phase detector (302) measures the output signal of the clock signal (301) and the voltage-controlled delay line (31〇)-0ut ( Whether the phase difference between 3i7) has the desired delay amount. The phase detector (30) generates a signal to control the charge pump (304). The phase detector (30) uses the upper and lower # Fool, U (303) and D (305) to control the charge pump (30 sentences to increase or decrease its output current. To ensure that the charge pump (304) maintains a nominal current output, The charge pump (304) is internally biased. The internal bias of the charge pump 12 1224428 (304) is based on the bias signals vBp (309) and vBN (311). Generated by the bias generator (308) (discussed below). The up and down signals (303, 305) are adjusted relative to the nominal current set by the bias signals (09, 31 1). Charge pump (304) Current output. The charging system (304) adds or removes charge from a capacitor &lt; ^ (3 06), which then changes the potential at the input of the bias generator (308). The capacitor (306 ) Is connected between the power supply VOD and the control signal Vctrj307). The bias generator (308) generates a bias bias (309, 311) in response to the control signal (307), and then controls and maintains the delay of the voltage-controlled delay line (310). A nominal current output from the charge pump (304). In Figure 4, the voltage-controlled delay line 10) can be made using a starved το current-deficient component. This means that the delay is controlled by changing the amount of current available for charging and discharging valleys. The knowledge of a voltage-controlled delay line depends on the stable range of frequencies that the DLL (300) can operate. The output signal (317) of the voltage-controlled delay line (31) represents a phase-delayed replica of the clock signal (301), which is then used by other circuits. Please still refer to Figure 4 to adjust the delay through the voltage-controlled delay line (31) in the DLL (300) through the negative feedback generated by the output signal (3 17). The phase detector (302) integrates a phase error generated between the clock signal (301) and the output signal (317). The voltage-controlled delay line ⑽) delays the output signal ㈣ for a fixed time ^, so that the required delay between the clock signal ⑽) and the output signal (3 17) is maintained. Therefore, the proper operation of the receiver circuit (134 in Figure 3) is determined by maintaining a fixed phase delay between the DLL (300) in the clock signal ⑽) and the output signal 13. [Summary of the Invention] According to one feature of one or more examples of the yak thunder / yoke of the present invention, an integrated circuit system includes ... (1) a locked loop mine circuit 'which includes a circuit for detecting The device for the phase difference between the 10th clock signal and a dream fan 1 Gule-1 pulse signal, a device for generating a control signal for the little water seat according to the phase difference, and the control according to the control Signal to store a power k &amp; power and power valley state, and used to generate the second clock based on the W signal ^ ^ the intention of the foxtail, and (2) a missing packet The control circuit is operatively connected to the three electric valley states, and the leakage electric machine circuit is configured to adjust the stored electric charge. According to a feature of one or more embodiments of the present invention, a method for the action of a locked loop circuit includes: comparing a phase difference between a clock signal and a second clock signal ; Generate a control signal according to / ratio k; According to the control signal, use a capacitor connected to the control signal to store electricity #; control the capacitor's leakage current; and generate the second clock according to the control signal signal. Other features and advantages of the present invention will be apparent from the following description and the scope of the appended claims. [Embodiment] As the component features (such as transistor characteristics) used to implement integrated circuit components like PLL / DLL continue to become smaller, they may have larger leakage currents (ie, larger gates) Pole tunneling current). This is because the thickness of the oxide layer of the transistor (located between the gate of the transistor and the semi-body substrate) is reduced when the transistor is specifically &lt; rushed. When the oxide layer is reduced to 14 1224428 angstroms, the gate terminal of the transistor begins to leak charge to the other terminals of the transistor. In the case of a capacitor of a loop filter, the capacitor typically requires a large capacitance from the perspective of capacitance, and can be made with a transistor ', and this reduction in the size characteristics of the transistor and the accompanying The increase in the leakage current may adversely affect the performance of the PLL / DLL. In some cases, a certain amount of leakage current may even cause the PLL / DLL to fail when passing through the capacitor of the loop filter. Therefore, there is a need for a PLL / DLL design that can protect against or compensate for the leakage current of the capacitor and the leakage of the loop wave transformer. Fig. 5 shows an example of a lock loop circuit according to an embodiment of the present invention. Those skilled in the art will appreciate that although the particular type of lock loop circuit in Figure 5 is a PLL (470), the principles of the present invention can be similarly applied to DLLs. In Figure 5, the PLL (470) uses a phase frequency detector (472) that detects the phase difference between the input clock signal elk-in (474) and the feedback clock signal fbk-clk (476). . Based on the phase difference detected by the phase frequency detector (472), the phase frequency detector (472) outputs pulses to a charge pump (482) on the UP (478) and DOWN (480) signals. The charge pump (482) generates a voltage control signal Vctrl (484) based on the pulses on the UP (478) and DOWN (480) signals. For the sake of convenience, the PLL (47〇) uses a loop filter composed of a loop filter capacitor (486) and a loop filter resistor (487), which is operatively connected to the voltage control. Signal (484). The capacitor (486) of the loop filter is based on the voltage control signal (484) to store / 1224428 to dissipate the charge. Those skilled in the art will understand that the capacitor (486) of the loop filter can be made using the gate capacitance of a metal oxide semiconductor field effect transistor (MOSFET). The 1 ^ (478) and DOWN (480) signals are only provided for one pulse per clock cycle. Therefore, the voltage control signal (484) may not be detected due to the leakage current of the capacitor (486) of the loop filter. maintain. To protect against the increased leakage current associated with the characteristics of the smaller transistor, a leakage current control circuit (488) is placed between the capacitor (486) of the loop filter and the potential Vdd (49). Those skilled in the art will notice that in one or more other embodiments, 'the leakage current control circuit (488) may be connected to a potential Vss' or ground (as shown in FIG. 7), and This potential is not Vdd (490). As shown in Figure 5, the leakage current control circuit (488) is operatively connected to the UP (478) and DOWN (480) signals, so that the leakage current control circuit (488) can (1) allow a loop filter The capacitor (486) leaks current when the charge pump (482) is 'on' (the charge pump (482) is said to be 'on' when the charge pump (482) actively provides or draws current to and from the voltage control Signal (484)), and (2) when the charge pump (482) is 'off', the leakage current of the capacitor (486) of the loop filter is limited. Those skilled in the art will understand that whenever one or both of the UP (478) and DOWN (480) signals are pulsed, the charging millet (482) is turned on during the pulse. A more detailed description of the leakage current control circuit is provided below with reference to FIGS. 6 and 7. Please refer to FIG. 5, the voltage control signal (484) is used as an input to the bias generator (492), and the bias generator (492) generates at least one bias 16 1224428 voltage signal (494) to the voltage controlled oscillation (Vco) (496). The voltage controlled oscillator (496) is based on at least one bias signal (494) from the bias generator (492) to generate an output clock signal clk_out (498). In addition to being an output of the PLL (470), the output clock signal (498) is fed back to the phase frequency detector (472) through the clock distribution network (400) and the feedback divider (402). An input. Those skilled in the art will note that in one or more other embodiments, the PLL (470) may not use the bias generator (492), but may be operatively connected to the voltage controlled oscillator (496). And voltage control signal (484). Fig. 6 shows a method of the leakage current control circuit (488) shown in Fig. 5 according to an embodiment of the present invention. In Figure 6, the leakage current control circuit (488) includes a p-channel transistor switch (500). And a NOR gate circuit (508), which is responsive to the UP (478) and DOWN (480) signals ( As shown in Figure 5, from the phase frequency detector (472)). More specifically, the p-channel transistor switch (500) has a first terminal (502) operatively connected to a potential vdd (490), and a second terminal (504) operatively connected to a capacitor of a loop filter ( 486). The gate terminal (506) of the p_ channel transistor switch (500) is operatively connected to the output of the NOR gate circuit (508). When one or both of the UP (478) and DOWN (480) signals are 'high', the No. gate circuit (508) outputs 'low', and when the UP (478) and DOWN (480) 480) When both signals are 'low', their output is high. Therefore, when one or both of the UP (478) and DOWN (480) signals are 'high', (that is, the charge pump ((482) in Fig. 5 ·) is 'on', ), The NO gate circuit (508) outputs 'low' to p 17 1224428 through the transistor switch (500), which then causes the p-channel transistor switch (500) to switch to 'on' and allows the circuit Filter capacitor (486) leakage current. Conversely, when both UP (478) and DOWN (480) signals are 'low' (ie, the charge pump ((482) in Figure 5)) Yes (off), the NO gate circuit (508) outputs' high 'to the p-channel transistor switch (500), which then causes the p-pass transistor switch (500) to switch to' Turn off and limit the leakage current of the capacitor (486) of the loop filter. Due to this configuration, the leakage current of the capacitor (486) of the loop filter is forked because it cannot become larger than the p-channel transistor switch (5 〇〇) source-to-drain current. Furthermore, because of the charge. The pump ((482) in Figure 5) is 'off' most of the time, so The cumulative reduction of the leakage current of the capacitor (486) of the circuit filter is helpful to improve the integrity of the voltage control signal (484), so that it brings a reliable and stable pLL operation. The leakage current control circuit (514) of another embodiment. In Figure 7, the capacitor (5 10) of a PLL loop filter is referenced to the potential Vss or ground (5 12), instead of the potential vdd (at 罘(490) in Figures 5 and 6. In this embodiment, the leakage current control circuit (5 1 4) includes § an n-channel transistor switch (5 1 6), an OR gate circuit (524) , Which is in response to the up (478) and DOWN (480) signals (from the phase frequency detector (472) as shown in FIG. 5). More specifically, the n-pass transistor switch (516) It has a first terminal (52) operatively connected to the ground potential (512) and a second terminal (518) operatively connected to a 4-loop filter capacitor (5 丨 〇). The n-channel transistor switch ( 5 丨 6) is connected operatively to the output of the 0-foot gate circuit (524) 18 1224428. When the UP ( 478) and one or both of the DOWN (480) signals are 'high', the OR gate circuit (524) outputs 'high', and when the UP (478) and DOWN (480) signals are both Both are 'low, when its output' is low. Therefore, when one or both of the UP (478) and DOWN (480) signals are 'high', (ie, the charging The pump ((482) in Figure 5 is' on ')' The OR gate circuit (524) outputs' high 'to the n-channel transistor switch (5 1 6), so it makes the n-channel transistor Switch 1 6) is switched to 'on,' and allows the capacitor (5 丨) leakage current of the loop filter. Conversely, when both the UP (478) and DOWN (480) signals are 'low' (that is, the charge pump ((482 "in Fig. 5 is 'off')), the The R-gate circuit (52 sentences outputs 'low' to the n-channel transistor switch (516), which then causes the n-channel transistor switch (516) to switch to 'off' and limits the capacitor of the loop filter (5 1 6) Leakage current. Due to this configuration, the leakage current of the capacitor (then) of the loop filter and the wave filter is controlled because it cannot become larger than the n-channel transistor.

To make. ^ The n-channel transistor switch (5 1 6) is because the charge pump (the capacitor of the "loop filter in Figure 5") helps to improve the reliable and stable PLL operation of the voltage control signal. In other embodiments, components other than the drain (488) and (514) in FIG. 7) n-channel transistor are added.

The discussion above with reference to Figures 19 1224428 to 7 is similarly applicable to DLLs. The embodiment of the present invention also relates to an adjustment and correction system for adjustment after locking the loop band. Please refer to Figure 2 for the manufacture of capacitor (206) and drain, which then changes the capacitor (206) 2 to 7 to be able to withstand the potential. So the frequency of the 'voltage controlled oscillator (21G) may drift. Stored for the dll as shown in Figure 4. It is also suitable here for the adjustment system, system multiplication, and combination logic of the present invention. The combination logic is controlled by an adjustment circuit that compensates for such a leakage current—the cardiac current ”circuit. Therefore, with respect to PL1 shown in FIG. 2, the missing pen ^ of ^. ^ ^ (206) can be compensated, and thus the capacitor (206) maintains a fixed potential. This is also possible for DLLs. Figure 8 is a block diagram showing a phase-frequency detector (600). The phase-frequency detector (600) represents the phase-frequency detector shown in Fig. 2 as (202). Those skilled in the art will understand that the phase-frequency detector (600) is a phase detector similar to the DLL shown in Figure 4. In Fig. 8, the phase-frequency detector (600) is integrated to generate a phase error between the clock A signal (221) and the clock B signal (223). The clock A signal (221) provides a clock to a flip-flop (606), and the clock B signal (223) provides a clock to a flip-flop (608). § When the h pulse A # (22 1) changes from low to high state, the flip-flop (606) is the 鬲 state generated by the power supply vDD (651) on the input of the flip-flop (606). The transition is made to this UP signal (203). When the clock B signal (223) changes from low-level evil to high-level resentment, the flip-flop (Mg) is a high state transition generated by the power source Vdd (651) on the input of the flip-flop (608) To the 20 1224428 DOWN signal (205). When both the UP and DOWN signals (203, 205) are in the high state, the AND gate (603) outputs a high state on the signal line (607). A high state on the signal line (607) resets the two flip-flops (606) and the flip-flops (608). When the flip-flop (606) and the flip-flop (608) are reset respectively, the UP and DOWN signals (203, 205) transition to the low state. Figure 9 is a block diagram showing the charge pump (700). The charge pump (700) represents the charge pumps (204, 234) shown in Fig. 2. Those skilled in the art will understand that the charge pump (700) is similar to the DLL charge pump shown in Figure 4. In Figure 9, the charge pump (700) has two current sources (702, 708). The current source (702) is connected between a power source VDD (701) and a signal line (703). The current source (708) is connected between the power source Vss (707) and the signal line (705). In Figure 9, the UP and DOWN signals (203, 205) from the phase-frequency detector (600) shown in Figure 8 determine whether the switches (704, 706) are closed, respectively. When the UP signal (203) is in the high state, the switch (704) is closed. The switch (704) is connected between the signal (703) and the control voltage (207). When closed, the switch (704) allows the control voltage (207) to use the current generated by the current source (702) to add charge to the capacitor (e.g., 206 shown in Figure 2). When the DOWN signal (205) is in the high state, the switch (706) is closed. The switch (706) is connected between a signal (705) and a control voltage (207). When closed, the switch (706) allows the control voltage (207) to be used to move the charge from the capacitor (e.g., 206 shown in Figure 2) by the current generated by the current source (708). except. 21 1224428 There is a short period of time when both the UP and DOWN signals (203, 205) are in the high state. In Figure 8, when both the UP and DOWN signals (203, 205) transition to the high state, the AND gate (603) resets the flip-flop by generating a high state on the signal line (607) ( 606, 608). The AND gate (603) and the flip-flops (606, 608) require a limited time to respond to such a change in state. In Figure 9, when both the UP and DOWN signals (203, 205) are high, the switches (704, 706) are both closed. During this period, a nominal charge is added to the capacitor (for example, 206 shown in Figure 2). Part or all of the current generated by the current source (702) is transferred to the Vss power source (707) through the current source (708). Fig. 10 is a timing chart (800) showing the phase-frequency detector (600) shown in Fig. 8. The timing chart (800) shows two clock cycles. The first clock cycle shows that the clock B signal (223) lags behind the clock A signal (221) (i.e., they have a phase difference). The second cycle shows that the clock B signal (223) is properly aligned with the clock A signal (221). In the first cycle, when the clock A signal (22 1) changes from a low state to a high state, the UP signal (203) changes from a low state to a high state. When the clock B signal (223) changes from a low state to a high state, the DOWN signal (205) changes from a low state to a high state. Because both the UP and DOWN signals (203, 205) are high, the AND gate (603 shown in Figure 8) resets the two flip-flops (606, 608 shown in Figure 8). . When the flip-flops (606, 608 shown in Fig. 8) are reset respectively, the UP and DOWN signals (203, 205) output a low state. 22 1224428 In the first period, the period of the UP signal (203) in the high state is longer than that of the DOWN signal (205). Thus, the current source (702 shown in Fig. 9) adds a charge to the capacitor (for example, 206 shown in Fig. 2). If the D0WN signal (205) requires the signal (203) to be long during the high state, the current source (（shown in Figure 9 will be removed from the capacitor (2 shown in Figure 2). 6) Remove the charge. The change in potential maintained by the emperor container (for example, 206 shown in Figure 2) affects the voltage-controlled oscillator (for example, shown in Figure 2). The frequency of 2⑼. | In Fig. 10, in the second period, the clock A signal (22 丨) and the clock B signal (223) both transition from the low state to the high state. In other words, the pulse A signal (201) and the clock B signal (223) are in phase. Therefore, both the up and D0WN signals (203, 205) transition from the low state to the high at the same time. The 606 and 608 shown in Fig. 8 are reset as the same because the AND gate (60 ° shown in Fig. 8 and the pros and cons (60 ° and 6 ° shown in Fig. 8) are reset. 8) It takes a limited time (ie, tMIN) to respond to changes in state, so both up and down # # (203, 205) have a limited time that is high. A nominal It is added to the capacitor in the system (e.g., display 206 in FIG. 2) to maintain the voltage on the control current potential (2〇7 shown in FIG. 2).

In Fig. 10, the charge pump (700 shown in Fig. 9) can be maintained in the capacitor (for example, 206 shown in Fig. 2) during the period of the charge. . The clock A signal (22 1) and clock B 23 1224428 "When the tiger (223) is aligned 'the charging pump (70% shown in the f 9 graph) is active compared to the charging pump being inactive The period of time is quite small (that is, 丄 W.) In this charge pump (700 shown in Figure 9) is inactive. That is, 'Although the switches (704, 706) are open, the period is The capacitance = two! The potential of 2, shown in the figure 2 may be due to being used;: two ... For example, the leakage current of the components shown in Figure 2 is 20%, and ## and". In addition, during the period of the power reduction mode, the period in which the charge (704, 706, 7000 shown in ^) is inactive (that is, when the L channel is switched) is increased. As in, in the power reduction mode, during the interval of the charging) action, the actions of Quan Wan and Zhi Wu in Q are increased by 1 times. During this power reduction mode, the potential at 20 μM valley (for example, in FIG. 2) may drift a large amount and store the liver. A device is needed to compensate for this drift. The semiconductor capacitor industry in Yixian County, the vertical electrode is from the source of ^ / transistor and draw it to produce a terminal of the capacitor. This capacitor is made up of a parallel plate capacitor. The other terminal of the transmission line is the path of the leakage current originally stored in the transistor by the interpolar connection of the transistor. Leakage PLL lock: The potential on the change. In a locked-loop circuit like ^, 206 Η 右 a a a σσ (Columns such as shown in Figure 2 maintained by the dust control oscillator (for example, 210 shown in Figure 2) The amount of frequency generated. In the second figure, in the second figure, the charge pump (204) is more belted. The stored electric charge (that is, the stored two electric valley (206)) &lt;) A relatively long interval period 24 1224428 may produce a drift in the frequency amount expected by the PLL (200). Although the designer may want a integrated circuit to have a specific value for the leakage current of the capacitor (206), But the actual values of these parameters are usually not known until the integrated circuit has been manufactured (that is, in the post-manufacturing stage). For example, 'the designer may want the frequency drift of the PLL (2 0 0) to be within a Within a specific range. The leakage current of the capacitor (206) may be affected unintentionally because of many factors in the manufacturing process. Because the leakage current cannot be manufactured without considerable time and money Was redesigned in later stages, so These manufacturing factors may cause the PLL (200) to have a frequency drift range that is different from the originally designed range of the PLL (200). Therefore, the PLL (200) may have poor performance. Therefore, for a type that helps to improve manufacturing There is a need for a subsequent technique and design for controlling the leakage current in the capacitor (206) of the PLL (200). Figure 11 shows an example of an adjustable lock loop circuit according to an embodiment of the present invention. Familiarity Those skilled in the art will understand that although Figure 11 shows a specific lock loop circuit as a PLL (900), the principles of the present invention can be similarly applied to a DLL. The phase of the adjustable PLL (900) is- The frequency detector (202), the capacitor (206), the bias generator (208), and the voltage-controlled oscillator (2 10) operate similarly to the corresponding components described above with reference to Fig. 2. In Fig. 11, A leakage current control circuit (904) is connected between the control voltage (207) and the power supply Vss. Since the capacitor (206) is a leakage current, the potential on the control voltage (207) tends to drift to the power supply VDD. The leakage The flow control circuit (904) is configured to pull the potential on the control voltage (207) 25 1224428 to the power source Vss. For example, an n-channel transistor system is used as the leakage current control circuit (904). In this field Those with ordinary knowledge will understand that in other embodiments, the capacitor (206) can be connected between the control voltage (207) and the power supply Vss. In this example, the leakage current control circuit (9⑽) is Connected between the control package voltage (207) and the power supply VDD. The leakage current control circuit (904) in this configuration can be a p-channel transistor. In Fig. 11, an adjustment circuit (954) is used to adjust the leakage current control circuit (904) to compensate the leakage current of the capacitor (206). A bias pen position VBIAS (961) is used to control the compensation1 which is added to compensate for this leakage current. The bias potential (961) can be adjusted to increase, decrease, turn off, or maintain a compensation amount (i.e., leakage current compensation) of the leakage current generated by the leakage current control circuit (904). In Fig. 11, a combinational logic circuit (952) uses a plurality of adjustment signals N (953) to control the adjustment circuit (954). The values of the plurality of adjustment signals N (953) are determined by the combinational logic circuit (952). The combinational logic circuit (952) can communicate through an interface (not shown) using M communication lines (95 1). Those having ordinary knowledge in this field will understand that this interface and communication lines (951) can have a wide variety of forms. The communication can be defined by an industry standard. The edge combination logic circuit (952) generates the plurality of adjustment signals v (953) in response to the deduction value on the M communication lines (951). The combinational logic circuit (9 5 2) can have 2M input combinations. For example, μ may be equal to 4 and ν may be equal to 6. Therefore, there are 6 combinations of 26 1 ^ 24428 1 for the values of the six adjustment signals N (953). … Those skilled in the art will understand that the adjustable pll (9㈣ can be analog, digital, or a combination of the two types of circuits. Figure u shows the _ 个 实 _Other-fans according to the invention ㈣ Locked loop circuit. Those skilled in the art will understand that although Figure 12 shows a specific locked loop circuit as ... (deleted), the principle of the present invention can be similarly applied to ... LL. The adjustable pll ( i〇〇〇) phase-frequency detector (202), capacitor ⑽), bias generator (208), | vibration control in (2H)), leakage current control circuit (9G4) and adjustment circuit (954 ) Operates similarly to the corresponding components of the above-referenced figure u. In Fig. 12, a combination logic circuit (1052) uses a plurality of adjustment signals N (953) to control the adjustment circuit (954). The values of the plurality of adjustment signals N (953) are determined by the combinational logic circuit (1 () 62). The up and down signals (203, 205) from the phase-frequency detector (202) control the combinational logic circuit (1062). . The first and second signals (1062) are generated in response to the up and down signals (203, 205) to generate the plurality of adjustment signals N (953). In one or more embodiments, the combinational logic circuit (1062) may utilize a state machine to generate multiple adjustment signals f # u N (953). In other embodiments, the combinational logic circuit (1062) may include an analog circuit having an analog-to-digital converter to generate the plurality of adjustment signals N (953). In other embodiments, the combinational logic circuit (1062) and the adjustment circuit (954) can be combined to perform a function similar to the charge pump (204), wherein the additional charge pump controls the leakage current control Circuit (904). 27 Hot white technicians will understand that the adjustable PLL (1000) can be analog, digital or a combination of two types of circuits. · Figure 13 shows a programmable motor source (1 1 00) according to an embodiment of the present invention.程式 The programmable current source can represent the adjustment circuit (954) shown in Figures 1 and 12. The programmable current source (110) includes a plurality of p-channel transistors (1102, 1106, 111) connected to a plurality of current sources (U22, &quot; 24, 1126), which are connected to each other. Arranged side by side. These packet current sources (1 122, 1 124, 1126) are connected to the power supply Vdd and p-channel transistors (1102, 1106, 1110), respectively. These p-channel transistors (1102 φ, 1106, mo) have a common node, and the bias potential Vbm (961) is supplied to the leakage current control circuit (in the second figure and the twelfth figure). 904). The programmable current source (1100) also contains a plurality of n-channel transistors (1 1 04, Π 08, 111 2) connected to multiple current sources (Π 2 8, 1, 1 3 0, 1 1 32), respectively. , Which are arranged side by side with each other. These current source current sources (1 128, 1 130, 1132) are connected to the power source vss and the η-channel transistors (1 104, 1 108, 1 1 12), respectively. The n-channel transistors (1104, 1108, 112) are connected to a bias potential vBIAS (961). _ Each of the transistors has a corresponding individual control signal, the control signal is “on” or “off”, the individual p-channel transistors (1 102;! 106, 1110) and individual n-channel transistors U 104, 1 108, 1 1 12). The p-channel transistors (1 102, 1 106, 1 1 10) have control signals ENE-PO (1101), ENE_P, (1105), and ENE-Pν (1109) connected to their gates, respectively. The n-channel transistors (1ΐ04, 1108, 1 112) have control signals EN-NO (1103), EN_N] (1107), and 28 1224428 en-Nn ( 1 1 1 1). The `` low '' potential on any EN-PX control signal (丨 101, 丨 105, 1 1 09) is to “turn on” the individual p-channel transistor (11 02, 1 1 06 , 1 1 1 〇) 'Where "X" represents any subscript 0 to N. "High" on any EN-N ^ s signal (1103, 1107, 1111), the potential is "on" individually Η-channel transistors (1104, 1108, 1112), where "x," represents any subscript 0 to N. A "conducting" p-channel transistor (1102, 1106, mo) is oriented The power supply VDD ground changes the bias potential (961). The change in the bias potential (961) is due to one or more of the current sources (1 122, 1 124, 1 126) _ provided Caused by the current flowing above the bias potential (96 1). A "conducting" n-channel transistor (1104, 1108, 1112) is oriented toward the power source v

The bias potential is changed by 0 S (961). The change in the bias potential (961) is caused by-the current provided by one or more of the current sources (1128, 1130, 1132) flowing out of the bias potential VBIAS (961). By selecting which ρ-channel transistor (1102, 1106, 1110) and / or ^ -channel transistor (1104, 1108, 1112) "conduct", one selected at the bias potential vBIAS (661) Change can be achieved. The person with general knowledge in this field will understand that these current sources (1122, 1124, 1126, 1128, 1130, 1132) can be designed with transistors operating in the saturation region. Furthermore, the ρ-channel transistor (1 102, 1 106, 1 1 10) and the η-channel transistor (1 104, 1 1 () 8, 1 1 12) are operated as switches to connect a current source (丨 丨 22, 1124, 1126, Π 28, 1130, 1132) to the bias potential vbias (961). '' Those with general knowledge in this field will understand that p-channel transistors 29 1224428 (1 102, 1 106, 1 1 l10) and n-channel transistors (1 104, 1 108, 1 112) can be individual or The entire group is “on”. Each current source (1 1 22, 1 124, 1 126, 1 128, 1 130, 1 132) can provide a fixed amount of current; although, with each current source (1122, 1124, 1 126, 1 128) , 1 130, 1 132) may provide different currents than other current sources u 122, 1 124, 1126, 1128, 1130, 1132). These current sources (1122, 1124, I 126, 1 128, 1 130, 1 132) can be designed when the current source (1 122, 1124, 1126, 1128, 1130, 1132) is connected to the bias potential vbias (901) provides a linear, exponential, or other function when disconnected from the bias potential vB1AS (961). The p-channel transistors (1102, 1106, 1110) and ^ -channel transistors (1104, 1108, 1112) can be used to add a fixed amount of current to the bias potential VBIAS (961). Current, or subtract a fixed amount of current from the current above the bias potential 乂 8 ^ 5 (961). The electric channels (1 102, 1106, 1 110) and the n-channel transistors (1 104, 11), 8 and II 12) are programmable current sources (11〇〇). Actions. The programmable motor source includes a plurality of current sources, each of which is operatively connected to a switch. The open relationship controls the flow of current from the current source. In Fig. 11 'the combinational logic circuit (952) generates a binary "k-sub-tuple", which determines which n-channel transistors in the adjustment circuit (954) (shown in n 1104, 1108, 1112) and p-channel transistors (1102, 1106, πm0 shown in Fig. 13) are "on," and those are "off". According to this The signal value of the M communication lines (951) received by the combinational logic circuit (952) represents the EN-NX signal (1103, 1107, and 1111 in Fig. 13 30) and the EN-Px signal (in Fig. 13 (101, 1105, 1109) can be “on” or “off” the p-channel transistor (shown in FIG. 13) of the adjustment circuit (954). 1 104, 1108, 1 112) and n-channel transistors (1104, 1108, 1112 shown in Figure 13). The bias potential vbias (961) of the adjustment circuit (954) adjusts the leakage current control circuit (904) to compensate the leakage current of the capacitor (206). In FIG. 12, the combinational logic circuit (1052) generates a binary control word group, which determines which n-channel transistors (1104, 11 shown in FIG. 13) in the adjustment circuit (954). 〇8, Ul2) and ρ-channel transistors (1 102, 1 106, u 1〇 shown in Figure 13) are "on" and which are "off," which represent the EN_NX signal (in The multiple adjustment signals N (653) of 1103, 1071, and 1111 in FIG. 13 and EN_PX # (11101, 1105, and 1109 in FIG. 13) may be “on, or“ “OFF” The p-channel transistor (1102, U06, 111) shown in FIG. 13 and the n-channel transistor (in u〇8, 1112 shown in FIG. 13) in the adjustment circuit (954). ). The bias potential VBIAS (961) of the adjustment circuit (954) adjusts the leakage current control circuit (904) to compensate the leakage current of the capacitor (206). The adjustable PLL (900 in Figure 11 and 700 in Figure 12) may exhibit unwanted operating characteristics after manufacturing, and these unwanted operating characteristics may not Zhongming Yi-Bu d ♦ ,,, Shi Bei. In one or more embodiments, the adjustment circuit (954 shown in Figure M and Figure 12) can modify the adjustable pLL (900 in Figure 11 and Figure 31). f / 2 (700 in the figure), so the adjustable PLL (900 in figure ▲ and the figure in Figure 12 can be adjusted. Those skilled in the art will understand the previous reference The principle of the fans of Figures 8 through 8 can be similarly applied to DLLs. Figure 14 shows a locking circuit along an example of another embodiment of the present invention. Those skilled in the art will understand that although The M diagram shows a specific locked loop circuit of the individual PLL (1200). The phase-frequency detector (202), the capacitor (206) of the pll (i200), which should be similarly adjustable in the present invention, ), The bias generator (208) and the day-controlled vibrator (i) operate similar to the corresponding components of the above-mentioned reference to FIG. 2. In Fig. 14, a leakage current control circuit (12G4) is connected between the control block (207) and Xunyuan Vss. Since the potential of the capacitor (20 magic leakage current 'on the control signal (207) has a tendency to drift toward the power source I. The leakage current control circuit (12G4) is configured to set the potential on the control signal (207) Pull to the power supply Vss. For example, in Figure 14, an n-channel transistor system is used as the leakage current control circuit (2204). Those with ordinary knowledge in this field will understand that in other implementations In the example, 'the capacitor (206) can be connected between the control signal (2G7) and the power supply vs. In this example, the leakage current control circuit (1204) is connected to the pestle signal (207) and the power supply. Between VDD. The leakage current control circuit (1204) in this configuration can be a p-channel transistor. In Figure 14, an adjustment circuit (1254) is used to adjust the leakage current control circuit (1204). ) To compensate the leakage current of the capacitor (206). A bias voltage of 321224428 C VBIAS (1261) is used to control the amount of compensation applied to compensate for the leakage current. The bias potential (1261) can be adjusted To increase, decrease, shut down or maintain Compensation for leakage current generated by the current control circuit (丨 204);! (Ie, leakage current compensation). The adjustment circuit (丨 254) can be similar to that described and shown in Figure 13 In FIG. 14, a test processor unit (1252) uses a plurality of adjustment signals N (1253) to control the adjustment circuit (254). The values of the plurality of adjustment signals N (1253) are determined by the test processor unit (1252). The test processor unit (1252) generates the plurality of adjustment signals N (1253) or binary control characters from a register that determines the settings of the adjustment circuit (1254). The test processor unit (1252) can change the contents of its registers through a host interface. In one or more embodiments of the invention, the test processor unit (1252) may be responsive to instructions. These instructions can be interpreted by the test processor unit (1 252) and can cause changes in the contents of the registers stored in the test processor unit 025 2). A change in the register contents may cause a change in the plurality of adjustment signals N (1253). The test processor unit (1252) can communicate through a host interface and a flash line (丨 25 丨). Those with ordinary knowledge in this field will understand that the host interface and the M communication lines (1251) can have a wide variety of forms. In one or more embodiments, the host interface may be operatively connected to another computer system. Furthermore, the host interface may be defined by an industry standard in one or more embodiments. The host interface described above can be used to operationally connect to a 33 1224428 other computer system. For example, a tester (not shown) can test the processor unit (1252) for communication. In some embodiments, the tester (not '", page not shown) may refer to the test unit (1252) without testing to adjust the adjustment circuit (= 4) to modify the leakage current of the adjustable pLL (12⑼) In some examples, the tester (not shown) can measure one of the operating characteristics of the adjustable PLLG200 or a representative operating characteristic of an integrated circuit. The adjustable The PIX (12 (^ is the compensation of the operation and the adjustment. Various adjustments can be made in order to confirm the adjustment setting of the desired operating characteristics of the adjustable pLL (l200). For example, 'The tester ( (Not shown) can be used to adjust the adjustable PLL (12GG) until the delay drift in the voltage controlled oscillator (21 ()) is minimized. The tester (not shown) can also be used to adjust The adjustable PLLO200) until the adjustable pll02⑽) operating characteristics reach a desired degree of performance. Such operating characteristics can include delay drift, maximum operating frequency, minimum operating frequency, lock time, etc. Has general knowledge in this field It will be appreciated by (Class 7 may be connected to the bias potential of the plant Kennedy leakage current control circuit (iv) the ...) Cloth ㉟ entire circuit G254) can still be "off ,,. In other words,… Zhou Zheng's $ Road (1254) can be controlled without affecting the adjustable holes ()). The test processor unit (1252) operatively controls the adjustment circuit: (1254). Adjust the bias potential of the circuit (1254). (Add) is to adjust the leakage current control circuit (1204). The technical staff will know that the adjustable PLL (1200) can be a circuit with a ratio, a digital or a combination of the two types. 34 1224428 Those skilled in the art will understand that the principles previously discussed with reference to Figure 14 can be similarly applied to DLLs. Advantages of the present invention may include one or more of the following advantages. In one or more embodiments, since the leakage current of the capacitor of a PLL / DLL loop filter can be controlled, it can contribute to more stable and reliable operation of the PLL / DLL. Thus, the phase shift of the PLL / DLL may not drift, or it may not drift as much as the PLL / DLL design of a capacitor that does not use a switch to resistively isolate the loop filter. In one or more embodiments, since an open relationship provided in series with the capacitor of the PLL / DLL loop filter is helpful to control the leakage current of the capacitor of the PLL / DLL loop filter, the PLL / DLL loop is filtered. The chip area occupied by the capacitor of the device can be reduced because the capacitor of the PLL / DLL loop filter does not need to be large to maintain the potential on the voltage control signal.

The adjustable PLL / DLL may exhibit unwanted operating characteristics after manufacturing, and the unwanted operating characteristics may not be apparent from simulation. In one or more embodiments, because the adjustment circuit can modify the operating characteristics of the adjustable PLL / DLL, the adjustable PLL / DLL can be adjusted. In one or more embodiments, because the adjustable PLL / DLL can be manufactured with a device for compensating for the leakage current of the capacitor, there is less iterative design and operation at the adjustable PLL / DLL Higher credibility in characteristics can be provided. In one or more embodiments, the 35 1224428 can be modified because of an adjustment circuit. The operational characteristics of Zhou Zheng's PLL / DLL, and the response of the offender during the operating situation can be entered / in one or more embodiments of Week 1, a limited number of adjustable: may need to be tested In order to determine the necessary adjustments for a 1-bit T to be used for future non-decent PLL / DLL. Instead, in one or more embodiments, the current source in the programmable electric source can be provided with a fixed current supply. It may be easier to fix it ^ ^ 0 'claws / original, and e ten and maintain a fixed current supply ~ 4 The privateized current source can use the digital control of the switch to increase the current from the current level, Reduce the current and / or change the direction of the current. % In one or more embodiments, 'because the adjustment circuit can modify the choice of adjustable PLL / DLL as a special feature, it is known as a characteristic, so the investigation of the response of the adjustable PLL / DLL during the operating situation may be Was carried out. The actual results help determine the appropriate values for the circuit components in the adjustable PLL / DLL and help reduce costly repetitive designs. In one or more embodiments, a tester and test processor unit π can be used to make known performance characteristics can be analyzed and / or the adjustable PLL / DLL can be adjusted. The present invention has been described in relation to a limited number of embodiments, but those skilled in the art, with the help of this disclosure, will realize the imagination and others without departing from the principles disclosed herein. Examples of the scope of the invention. Therefore, the scope of the present invention should be limited only by the scope of the attached patent application. [Schematic description] 36 1224428 (I) Schematic part The first figure shows typical computer system components. Brother 2 is a block diagram showing the phase-locked loop back of conventional techniques. Figure 3 shows typical computer system components. Fig. 4 is a block diagram showing the delay lock of the conventional technique. Fig. 5 shows a circuit according to an embodiment of the present invention. Fig. 6 shows a portion of the circuit according to the present invention shown in Fig. 5 as shown in Fig. 5; Fig. 7 is a diagram showing a circuit according to an embodiment of the present invention-Fig. 8 is a schematic diagram showing a phase-frequency detector. Figure 9 is a schematic diagram showing a charge pump. Figure 10 is a timing diagram showing _-4 / shown in Figure 8. The phase-frequency detector described in 3 is a block diagram showing a circuit having a gangster a /, and a leakage current control circuit according to an embodiment of the present invention.弟 12 图 系 # A member is not present; (p since 4 · 八 ^^ ΛΛ ώ There is a block diagram of a circuit of an adjustable positive leakage current control circuit according to an embodiment of the present invention.: 13 Figure shows the An embodiment of the present invention

/ And source schematic. I 苐 Κ picture shows one and right

Adjusted Leakage # Block Invention of a V-shaped circuit of an embodiment of the invention. (1) Computer system for representative symbols 37 10 1224428 12 14 16 18 19 20 100 112 114 116 134 200 201 202 204 206 207 208 209 210 211 212, 214, 216, 218 213 215 Microprocessor memory volume circuit crystal oscillation Communication Circuit Phase Locked Loop (PLL) Computer System Component Circuit A Information

Clock signal circuit B Phase lock loop (PLL) System clock signal phase-frequency detection charge pump capacitor control voltage bias generator bias voltage voltage controlled oscillator bias voltage buffer output signal output clock signal 38 1224428 217 chip Clock signal 220 divided by A circuit 221 Clock A signal 222 divided by C circuit 223 Clock B signal 224 divided by B circuit 234 Charge pump 250 PLL core 300 DLL 301 Clock signal 302 Phase detector 304 Charge pump 306 Capacitor 307 Control signal 308 Bias generator 309 Bias signal 310 Voltage controlled delay line 311 Bias signal 317 Output signal 402 Feedback divider 470 PLL 472 Phase frequency detector 474 Input clock signal 476 Feedback clock signal 39 1224428 482 Charge pump 484 Voltage control signal 486 Capacitor of the loop filter 487 Resistor of the loop filter 488 Leakage current control circuit 492 Bias generator 494 Bias signal 496 Voltage controlled oscillator 498 Output clock signal 500 p channel transistor switch 502 First terminal 504 Second terminal 506 Gate terminal 508 NOR Gate circuit 510 Capacitor of PLL loop filter 514 Leakage current control circuit 516 η channel transistor switch 518 Second terminal 520 First terminal 522 Gate terminal 524 OR Gate circuit 600 Phase-frequency detector 606, 608 Flip-flop 607 Signal Line 1224428 700 charge pump 702 current source 703 signal line 704 switch 705 signal line 706 switch 708 current source 900 PLL 904 leakage current control circuit 951 communication line 952 combination logic circuit 953 adjustment signal 954 adjustment circuit 961 bias potential 1000 PLL 1052 combination Logic circuit 1100 programmable current sources 1101, 1103, 1105, 1107, 1109, 1111 control signals 1102, 1106, 1110 P-channel transistors 1104, 1108, 1112 n-channel transistors 1122, 1124, 1126, 1128, 1130, 1132 Current source 1200 PLL 1204 Leakage current control circuit 1251 Communication line

41 1224428 1252 Test processor unit 1253 Adjustment signal 1254 Adjustment circuit 1261 Bias potential

42

Claims (1)

1224428% of the year, the factory said that the scope of corrections and corrections: 1 · An integrated circuit, which includes: A locked loop circuit, the locked loop circuit includes: used to detect the signal in a first clock And a phase difference device between the second clock signal, a device for generating a control signal based on the phase difference, a capacitor for storing a charge based on the control signal, and a device for generating based on the control signal The device of the second clock signal, and a leakage current control circuit operatively connected to the capacitor, wherein the leakage current control circuit is configured to adjust the stored charge. 2. The integrated circuit of item 丨 in the scope of patent application, wherein the leakage current control circuit is connected between the capacitor and a potential, wherein the leakage current control circuit includes a switch in response to the device for detection And wherein the open relationship is set in series with the capacitor. 3. If the integrated circuit of item 1 or 2 of the scope of patent application, it further includes Φ a programmable current source connected to the leakage current control circuit, wherein 4 privatizable current source includes a first current source And a first switch configured to control the leakage current control circuit; and a combinational logic circuit operatively connected to the programmable current source, wherein the combinational logic circuit is configured to selectively adjust the programmable current source. 43 1224428 4. If the integrated circuit of item 1 of the scope of patent application, it further includes an adjustment circuit operatively connected to the leakage current control circuit, the adjustment circuit in the basin is configured to control the leakage current control. " And eight test processor units operatively connected to the adjustment circuit, wherein the test processor unit is configured to selectively adjust the adjustment circuit. For example, the integrated circuit of the scope of application for a patent! The lock loop circuit is one of the phase lock loop and the delay lock loop. [6] For example, the integrated circuit of item 3 of the scope of patent application, wherein the first current source and the first open relationship are configured to control according to a control At the first potential and one of the programmable current source: = 1 electric motor 'and wherein the output is operatively connected to the leakage current control circuit. 7. If a patent application covers a 6-item integrated circuit, The programmable current source further includes: a first current source and a second switch, the second open relationship is configured to be controlled at a second potential according to a second control signal and X can privatize the current flow between the outputs of the current source. 8. If the patent application is for a three-item integrated circuit, the combinational logic circuit is configured to respond to the -clock signal and the -th clock signal. The phase difference between the two clock signals is used to adjust the programmable current source. 9 · For example, the integrated circuit of item 4 in the patent application scope, wherein the adjustment circuit system includes: the electric units are configured to be controlled at a first Potential and the adjustment circuit 44 1224428 current flow between one turn out! The first switch; and a second switch configured to control the current flow between a second potential and the output of the adjustment circuit, The wheel output system is operatively connected to the leakage current control circuit. Ϊ́〇 · The integrated circuit of item 4 of the patent application scope, wherein the adjustment circuit includes a first p-channel transistor and a 筮 ^ ^ ^ r The Le-n-channel transistor, wherein the first p-channel transistor and the -n-channel transistor system are connected in series. Π. If the integrated circuit of item 10 of the patent application scope, the adjustment circuit It further includes: a second p-channel transistor connected in parallel with the first p-channel transistor; and the -p-channel transistor in a second n-channel transistor connected in parallel with the first n-channel transistor The crystal and the second p-channel transistor system are connected in series with the -n-channel transistor and the second n-channel f crystal. 12. For example, the integrated circuit circuit of item (i) of the patent application scope further includes: A device for outputting at least one bias signal 'wherein the device for the Yanfeng priest is enough to be the first clock signal is based on the at least one bias signal. 13. A type of circuit for performing a lock loop The method of action includes: comparing a phase difference between a ^^ clock signal and a second clock signal; 45 1224428 generating a control signal based on the comparison; and using a connection to The capacitor of the control signal is used to store charge; the leakage current of the capacitor is controlled; and the second clock signal is generated according to the control signal. 14. The method of claim 13, wherein controlling the leakage current of the capacitor includes using a switch provided in series with the capacitor, wherein the open relationship is responsive to the comparison. 15. The method of claim 13 or 14, wherein controlling the leakage current of the capacitor includes: using a leakage current control circuit in response to a programmable current source, wherein the programmable current source is Including a first current source and a first switch configured to control the leakage current control circuit; and a combinational logic circuit operatively connected to the programmable current source to selectively adjust the programmable current source. 16. The method of claim 13 in the scope of patent application, wherein controlling the leakage current of the capacitor comprises: using a test processor unit to generate and generate a binary control word f to be applied to the binary control word circuit. Tuple to selectively adjust an adjustment 17. The method according to item 15 of the scope of the patent application, further comprising: B 依据 using a first current source and the first switch according to a first control signal to control A current flows between a first electrical potential and a 46 1224428 output of the programmable current source, wherein the output is operatively connected to the leakage current control circuit. 18. The method of claim 15 in the patent application range, wherein the selective adjustment comprises: citing a combination of a logic circuit to adjust one of the possible settings of the programmable current source to a fixed number, and wherein The selective adjustment is responsive to the comparison. The selectivity β 19 · If the method of the 16th scope of the patent application, Adjusting the adjustment circuit includes: controlling at a first potential and a first current flow of the adjustment circuit; and controlling it at a second potential and the second current flow of the adjustment circuit. / Between rounds Pick up, schema: as the next page 47