TWI223744B - Method of storage device read phase auto-calibration and related mechanism - Google Patents

Method of storage device read phase auto-calibration and related mechanism Download PDF

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Publication number
TWI223744B
TWI223744B TW092134816A TW92134816A TWI223744B TW I223744 B TWI223744 B TW I223744B TW 092134816 A TW092134816 A TW 092134816A TW 92134816 A TW92134816 A TW 92134816A TW I223744 B TWI223744 B TW I223744B
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Taiwan
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scope
item
patent application
phase
storage device
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TW092134816A
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English (en)
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TW200519577A (en
Inventor
Yi-Shu Chang
Seng-Huang Tang
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Realtek Semiconductor Corp
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Priority to TW092134816A priority Critical patent/TWI223744B/zh
Priority to US10/711,442 priority patent/US7257036B2/en
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Publication of TWI223744B publication Critical patent/TWI223744B/zh
Publication of TW200519577A publication Critical patent/TW200519577A/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10481—Improvement or modification of read or write signals optimisation methods

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Dram (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Description

1223744 圖式簡單說明 圖式之簡單說明 圖一為本發明儲存裝置讀取相位自動校正方法之流 程不意圖。 圖二為圖一之方法之相關元件之示意圖。 圖式之符號說明 101,102，……，115標準延遲單元 2 1 0控制單元 2 2 0延遲鏈 2 3 0多工器 DQS，VREF，TDO，TD1，……，TD15，SEL，TRIG 訊號
第13頁

Claims (1)

1223744 六、申請專利範圍 1. 一種對一儲存裝置進行讀取相位校正之方法，該方法 包含有： 對該儲存裝置寫入至少一預定樣式（predetermined pattern)之資料' 以複數個相位當中之一相位，讀取該儲存裝置之資 料； 比較所讀取之資料與該預定樣式之資料；以及 根據該比較結果，於該複數個相位當中決定一讀取 相位。
2 .如申請專利範圍第1項所述之方法，其中該複數個相位 係為相對於一參考訊號（reference signal)。 3.如申請專利範圍第2項所述之方法，其中該參考訊號 係為一頻閃訊號（s t r 〇 b e s i g n a 1)或一時脈訊號。 4 .如申請專利範圍第2項所述之方法，其中該儲存裝置 係為一動態隨機存取記憶體（DRAM)，並且該參考訊 號係為一 DQS訊號。
5 .如申請專利範圍第1項所述之方法，其中該儲存裝置係 為一記憶體。 6.如申請專利範圍第5項所述之方法，其中該儲存裝置
第14頁 1223744 六、申請專利範圍 係為一DDR( Double Data Rate)記憶體 7.如申請專利範圍第1項所述之方法，其 之 至少—預定樣式係為一個十六進位數、Μ寫入歩领 進位數0101或1010。 歎5或a’即一個二 8.;ΠίΠί7項所述之方法，其中該寫人步驟 個一 i # I S Μ Υ係為一個十六進位數5滅a5，即一 個一進位數 01011〇1〇或 loiooioi。 9 ·如申請專利範圍第1工百％、+、>古、、上 ^ m ^ 1負所述之方法，並Φ古女靖取步驟係 讀取被寫入該儲存萝罢夕5小益— Ll 阳什忒置之至少一預定樣式之資料。 1 0 ·如申，^利巧圍第i項所述之方法，其中該比較步驟 係比較该所項取之資料是否與該預定樣式之資料相 同。 7 1 1 ·如申請專利範圍第1項所述之方法，其中該決定步驟 係於該複數個相位當中讀取正確之相位中決定一相位 作為該讀取相位。
1 2 ·如申請專利範圍第1 1項所述之方法，其中該決定步驟 係於該複數個讀取相位當中讀取正確之連續相位中位 於正中央或近似正中央之相位作為該讀取相位。
第15頁 1223744 六、申請專利範圍 1 3. —種電路用以對一儲存裝置進行讀取相位校正，該電 路包含有： 一控制單元，耦合至該儲存裝置，用來於複數個相 位當中決定一讀取相位，並根據該讀取相位輸出 一選擇訊號；
一延遲鏈，用來產生複數個相位信號；以及 一多工器，耦合至該控制單元與該延遲鏈，用來根 據該選擇訊號，於複數個相位當中選擇輸出一讀 取相位。 1 4.如申請專利範圍第1 3項所述之電路，其中該控制單元 係為一數位訊號處理器。 1 5 .如申請專利範圍第1 3項所述之電路，其中該控制單元 包括一韋刃體。
第16頁
TW092134816A 2003-12-10 2003-12-10 Method of storage device read phase auto-calibration and related mechanism TWI223744B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW092134816A TWI223744B (en) 2003-12-10 2003-12-10 Method of storage device read phase auto-calibration and related mechanism
US10/711,442 US7257036B2 (en) 2003-12-10 2004-09-19 Method and apparatus for storage device read phase auto-calibration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092134816A TWI223744B (en) 2003-12-10 2003-12-10 Method of storage device read phase auto-calibration and related mechanism

Publications (2)

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TWI223744B true TWI223744B (en) 2004-11-11
TW200519577A TW200519577A (en) 2005-06-16

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US (1) US7257036B2 (zh)
TW (1) TWI223744B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7685456B1 (en) 2003-07-30 2010-03-23 Marvell Israel (Misl) Ltd. DDR interface bus control
US7345933B1 (en) * 2005-01-13 2008-03-18 Marvell Semiconductor Israel Ltd. Qualified data strobe signal for double data rate memory controller module
JP4414974B2 (ja) * 2006-02-28 2010-02-17 パナソニック株式会社 データ受信装置
KR101027689B1 (ko) * 2009-09-30 2011-04-12 주식회사 하이닉스반도체 데이터 드라이빙 임피던스 자동 조정 회로 및 이를 이용한 반도체 집적회로
TWI404339B (zh) * 2009-11-25 2013-08-01 Mstar Semiconductor Inc 記憶體信號相位調整方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4600895A (en) * 1985-04-26 1986-07-15 Minnesota Mining And Manufacturing Company Precision phase synchronization of free-running oscillator output signal to reference signal
US5093841A (en) * 1990-01-30 1992-03-03 Nynex Corporation Clock acquisition in a spread spectrum system
US5066868A (en) * 1990-08-13 1991-11-19 Thomson Consumer Electronics, Inc. Apparatus for generating phase shifted clock signals
US5126691A (en) * 1991-06-17 1992-06-30 Motorola, Inc. Variable clock delay circuit
US5245637A (en) * 1991-12-30 1993-09-14 International Business Machines Corporation Phase and frequency adjustable digital phase lock logic system
US5561692A (en) * 1993-12-09 1996-10-01 Northern Telecom Limited Clock phase shifting method and apparatus
US6760856B1 (en) * 2000-07-17 2004-07-06 International Business Machines Corporation Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration
US7103110B2 (en) * 2003-10-10 2006-09-05 Atmel Corporation Dual phase pulse modulation encoder circuit

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TW200519577A (en) 2005-06-16
US7257036B2 (en) 2007-08-14
US20060080564A1 (en) 2006-04-13

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