TWI222195B - Method for fabricating heat sink of semiconductor packaging substrate - Google Patents
Method for fabricating heat sink of semiconductor packaging substrate Download PDFInfo
- Publication number
- TWI222195B TWI222195B TW092109195A TW92109195A TWI222195B TW I222195 B TWI222195 B TW I222195B TW 092109195 A TW092109195 A TW 092109195A TW 92109195 A TW92109195 A TW 92109195A TW I222195 B TWI222195 B TW I222195B
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- Prior art keywords
- heat
- heat sink
- layer
- heat dissipation
- photoresist layer
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於丰墓 尤指利用電鍍方式在散熱片上::f板,散熱片製作方法, 該散埶片内後於半I鱗、、 ;成凸部之製作方法,係必 狀…乃η甘入孓牛導體封裝基 俾將 【先前技術】 隨著積體電路製造技術的進步, 越來越多的半導體元件。 日日片上可沉積 過护士 七夕田於母一個丰導體元件在運从耳 過麁中,Α夕或少都會耗散出 :?作的 ί件積集度的增力…吏得單-晶片所耗散;導體 2越多。若不能提供一有 :、:也越 導致該晶片無*正常運2 f w #作溫度以上’進而 的情形下,半導運作,甚至影響晶片之壽命。在 之封裝基板中,掣;片〗3:耗散係藉由在半導體晶片 達成。 “…導熱材料所構成的散熱結構來 凊參閱第1圖,其係顯示習知 J結t半導體封裝基板。該半 中以導熱= 乍為散 ί —上表面100及-下表面101之散孰片t基板1包括一具 :、片10上表面1〇〇之上樹脂層n、一壓厶10、一壓合於該散 表面101之下樹脂層12、一形成於該上二於該散熱片10下 =3、-形成於該下樹㈣12< 11之上電路 導電检15與導熱拾16。為保護上下層=14、以及複數個 路層,該下電路層14上分別塗覆有— 故於該上電 。亥政熱片10係内嵌於該半導體封裴基中17、18。 1222195 五、發明說明(2) --- 該半導體封裝基板1之散熱結構。此外,並於該散熱片i 〇 上鑽鑿有複數個導通孔11 〇,用以裝設該複數個導電栓i 5 及複數個導熱栓1 6。當該上樹脂層丨丨及該下樹脂層丨2之絕 緣樹脂壓合於該散熱片1 0後,該絕緣樹脂得填滿該散埶 之導通孔11 0。 ” 该上電路層1 3係佈置於該上樹脂層丨丨之表面,並於i 上設置有複數個打線墊131,俾於該上電路層13覆蓋一声、 拒銲層17之後,該打線墊131得露出該拒銲層17之開口 : 以供金線161得以電性連接該晶片ι6〇與該基板卜 該下電路層1 4係佈置於該下樹脂層丨2之表面,並於其 上设置有複數個銲球墊1 4 1,俾於該下電路層丨4覆蓋一層 拒銲層1 8之後,該複數個銲球墊丨4丨得露出該拒銲層丨8之 開口,以供該複數個銲球墊1 4 1與銲球1 9相連接。 該複數個導電栓1 5係貫穿該上樹脂層1卜該散熱片i 〇 之導通孔11 0及該下樹脂層1 2使上電路層丨3與下電路層j 4 得以相互電性連接。其中,該導電栓丨5之口徑係小於該導 通孔1 1 0之口徑,且於該導電栓丨5與該導通孔!丨〇之間隙填 充有絕緣樹脂以防止短路發生。 該複數個導熱栓1 6亦係貫穿該上樹脂層11、該散熱片 1 0之導通孔1 1 0及該下樹脂層1 2使該晶片1 6 0上所產生之熱 量得以傳導至該散熱片1 〇,以達到散熱的功能。 在實施封裝時,將至少一個半導體晶片1 6 〇以絕緣傳 熱膠(未圖示)黏著於該基板具有導熱栓1 6之表面置晶區 域,使晶片上所產生的熱量得以藉由該晶片1 6 0底部之絕V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a tomb, especially an electroplating method on a heat sink: an f-plate, a method for manufacturing a heat sink, and the loose sheet is placed in a semi-I scale, The method of making the convex part is necessary ... It is η to enter the yak conductor packaging base. [Previous technology] With the advancement of integrated circuit manufacturing technology, more and more semiconductor components. It can be deposited on the Japanese film. The nurse, Tanabata Yuma, and a female conductor are transported from ear to ear, and Axi will at least dissipate:? The increase of the accumulation degree of the made pieces ... It is dissipated by the single-chip; the more the conductor 2 is. If you ca n’t provide a:,: the more the chip will fail to operate normally at 2 f w # above the temperature, and the semiconducting operation will even affect the life of the chip. In the package substrate, the chip; chip [3]: Dissipation is achieved by the semiconductor wafer. "... Refer to Figure 1 for the heat dissipation structure made of a thermally conductive material, which shows the conventional J-junction semiconductor package substrate. In this half, the thermal conductivity = first is scattered—the upper surface 100 and the lower surface 101 are scattered. The chip t substrate 1 includes: a resin layer n above the upper surface of the chip 10, a pressure roller 10, a resin layer 12 laminated on the lower surface 101, and a heat dissipation layer formed on the upper surface and the heat dissipation layer. The bottom of the sheet 10 = 3,-is formed on the lower tree ridge 12 < 11 and the circuit conductance test 15 and the thermal pick-up 16. In order to protect the upper and lower layers = 14, and a plurality of road layers, the lower circuit layer 14 is coated with- Therefore, the power is turned on. The Haizheng heat sink 10 is embedded in the semiconductor package 17 and 18. 1222195 V. Description of the invention (2) --- The heat dissipation structure of the semiconductor package substrate 1. In addition, the heat sink A plurality of through holes 11 〇 are drilled on i 〇 for mounting the plurality of conductive bolts i 5 and the plurality of thermally conductive bolts 16. When the insulating resin of the upper resin layer 丨 and the lower resin layer 丨 2 is pressed, After being combined with the heat sink 10, the insulating resin has to fill the scattered vias 110. "The upper circuit layer 13 is arranged on the On the surface of the upper resin layer 丨, a plurality of wire bonding pads 131 are provided on i. After the upper circuit layer 13 is covered with a sound and solder resist layer 17, the wire bonding pad 131 is exposed to the opening of the solder resist layer 17: The gold wire 161 can be used to electrically connect the wafer ι60 and the substrate and the lower circuit layer 14 is arranged on the surface of the lower resin layer 丨 2, and a plurality of solder ball pads 1 4 1 are provided thereon.之后 After the lower circuit layer 丨 4 is covered with a solder resist layer 18, the plurality of solder ball pads 丨 4 丨 the opening of the solder resist layer 丨 8 must be exposed for the plurality of solder ball pads 141 and the solder The balls 1 to 9 are connected. The plurality of conductive bolts 15 are penetrating through the upper resin layer 1b, the via hole 110 of the heat sink i 0 and the lower resin layer 12 to electrically connect the upper circuit layer 3 and the lower circuit layer j 4 to each other. Among them, the diameter of the conductive pin 5 is smaller than the diameter of the through hole 110, and the conductive pin 5 and the through hole!丨 〇 The gap is filled with insulating resin to prevent short circuit. The plurality of thermally conductive bolts 16 also penetrate the upper resin layer 11, the through holes 1 10 of the heat sink 10, and the lower resin layer 12 so that the heat generated on the wafer 160 can be conducted to the heat dissipation. Slice 1 〇 to achieve the function of heat dissipation. When the package is implemented, at least one semiconductor wafer 160 is adhered to the surface of the substrate with a thermally conductive plug 16 by an insulating heat transfer adhesive (not shown), so that the heat generated on the wafer can pass through the wafer. 1 6 0 bottom of the
17172 全懋.ptd 第9頁 1222195 五、發明說明(3) ' ' ------- 緣傳熱膠(未圖不)傳導道# ,ln Μ# # 亥導熱栓16,再傳導至該散熱 “、:丄Ϊ : Ϊ f的㈣。該上電路層13之打線墊131係 而與晶片160上之銲墊相連接。為保護 呑亥晶片1 6 0不受外界雷性+搞 1 pg , , „ t!丨^^ 干擾可用一封膠1 62包覆於該晶 ί ϋΛ其Λ °最&,將複數個料19連接於該 ϋϊ; 銲球墊141上,以完成具散熱結構之半 ^而上述以導熱栓作為散熱結構之半導體封裝件 功妒之篓赦扒甘#產生之熱1傳送至散熱片以完成散熱 ^ 導…、裎,/、與晶片之接觸截面積極小,且因1係穿 熱片之中故為其製作過程增加了許多不必要步 必要的製作成本。个&理心,亦同時增加了許多不 有鑑於上述習知半導體 專利公報第457836號公告中板之缺點,於中華民國 封裝基板結構及其製作方法5路::⑧「具高散熱半導體 該項專利公告中所揭露之且ϋ f芩閱第2圖,其中顯示 拓。兮主遗抽u # 具w散熱結構之半導體封萝美 板。该丰導體封裝基板2包括—苒千 T裝基 面201之散熱片20、一壓人於ς = 一上表面20 0及—下表 脂層2卜一壓合於該散埶片欠熱片20上表面2 0 0之上樹 一形成於該上樹脂層21Ζ 下表面20 1之下樹脂層22、 層22之下電路層24、以 -形成於該下樹脂 該散熱片20亦内嵌於兮=導電检25。 攝,其具有〆上凸部202、17172 Quan 懋 .ptd Page 9 1222195 V. Description of the invention (3) '' ------- Edge heat transfer glue (not shown) Conduction channel #, ln Μ # # HAI conductive plug 16 and then conductive to The heat sink ",: 丄 Ϊ: Ϊ f㈣. The wire bonding pad 131 of the upper circuit layer 13 is connected to the solder pad on the chip 160. To protect the chip 16 from external thunder ++ 1 pg,, „t! 丨 ^^ Interference can be covered with a piece of glue 1 62 该 其 Λ 其 Λ ° the most &, a plurality of materials 19 are connected to the ϋϊ; solder ball pad 141 to complete the heat dissipation Half of the structure ^ And the above-mentioned semiconductor package using the thermal conductive plug as a heat dissipation structure, the heat generated from the basket # 1 is transferred to the heat sink to complete the heat dissipation ^ guide, 裎, /, the contact cross section with the chip is very small , And because of the 1 series of heat-through films, it adds many unnecessary steps and necessary production costs to its production process. A & rationality, and at the same time added a lot of the structure of the package substrate and its manufacturing method in the Republic of China without considering the shortcomings of the board in the above-mentioned conventional semiconductor patent publication No. 457836. It is disclosed in a patent announcement and is shown in Figure 2. It shows the extension. Xi main legacy pumping u # semiconductor package with a heat dissipation structure. The semiconductor package substrate 2 includes-苒 千 T 装 基The heat sink 20 on the surface 201 is pressed on the upper surface = a top surface 20 0 and the lower surface fat layer 2 is pressed onto the upper surface 2 0 0 of the diffuser sheet underheat sheet 20 and a tree is formed on the surface. Upper resin layer 21Z lower surface 20 1 resin layer 22 below layer 22, circuit layer 24 below layer 22, and-formed on the lower resin. The heat sink 20 is also embedded in the conductive film 25. It has a convex projection. Ministry 202,
1222195 五、發明說明(4) 一中心部2 0 3及一下凸部2 0 4。此外,並於該散熱>i 2 0上鑽 鑿有複數個導通孔2 1 0,用以裝設該複數個導電栓2 5。當 該上樹脂層2 1及該下樹脂層2 2之絕緣樹脂壓合於該散熱片 2 0後,該絕緣樹脂得填滿該散熱片之導通孔2 1 0。 該上電路層2 3係佈置於該上樹脂層2 1之表面,並於其 上設置有複數個打線墊2 3 1,俾於該上電路層2 3覆蓋一層 拒銲層2 7之後,該打線墊2 3 1得露出該拒銲層2 7之開口’ 以供金線2 6 1電性連接該晶片2 6 0與該基板2。 該下電路層2 4係佈置於該下樹脂層2 2之表面,並於其 上設置有複數個銲球墊2 4 1,俾於該下電路層2 4覆蓋一層 拒銲層2 8之後,該複數個銲球墊2 4 1得露出該拒銲層2 8之 開口’以供該複數個銲球墊2 4 1與銲球2 9相連接。 該複數個導電栓2 5係貫穿該上樹脂層2卜該散熱片2 0 之導通孔2 1 0及該下樹脂層2 2使上電路層2 3與下電路層2 4 得以相互電性連接。其中,該導電栓2 5之口徑係小於該通 孔2 1 0之口徑,且於該導電拴2 5與該導通孔2丨〇之間隙填充 有絕緣樹導脂以防止短路發生。 在實施封裝時,將至少一個半導體晶片2 6 〇以絕緣傳 熱膠(未圖示)黏著於該散熱片2 〇之凸部2 〇 2上,使該晶 片2 6 0所產生的熱量得以藉由該晶片2 6 〇底部之絕緣傳熱膠 (未圖示)直接傳導至該散熱片2 〇,以達到散熱的目的, 並利用複數條金線2 6 1以電性連接該上電路層2 3之打線墊 2 3 1與晶片2 6 0上之電極,而為保護該晶片2 6 〇不受外界電 性干擾’可用一封膠2 6 2包覆於該晶片2 6 0及該金線2 6 1之1222195 V. Description of the invention (4) A central portion 203 and a lower convex portion 204. In addition, a plurality of through holes 2 1 0 are drilled on the heat dissipation > i 2 0 for mounting the plurality of conductive pins 25. After the insulating resins of the upper resin layer 21 and the lower resin layer 22 are pressed on the heat sink 20, the insulating resin must fill the through holes 21 of the heat sink. The upper circuit layer 2 3 is disposed on the surface of the upper resin layer 21, and a plurality of wire bonding pads 2 3 1 are provided thereon. After the upper circuit layer 2 3 is covered with a solder resist layer 2 7, the The bonding pad 2 3 1 has to expose the openings of the solder resist layer 2 7 for the gold wire 2 6 1 to electrically connect the chip 2 60 and the substrate 2. The lower circuit layer 24 is disposed on the surface of the lower resin layer 22, and a plurality of solder ball pads 2 41 are provided thereon. After the lower circuit layer 24 is covered with a solder resist layer 28, The plurality of solder ball pads 2 4 1 can expose the openings of the solder resist layer 28 to allow the plurality of solder ball pads 2 4 1 to be connected to the solder balls 2 9. The plurality of conductive bolts 25 pass through the upper resin layer 2 and the through holes 2 1 0 of the heat sink 20 and the lower resin layer 22 to electrically connect the upper circuit layer 2 3 and the lower circuit layer 2 4 to each other. . The diameter of the conductive bolt 25 is smaller than the diameter of the through hole 210, and the gap between the conductive bolt 25 and the through hole 2 is filled with a conductive resin to prevent short circuit. When the package is implemented, at least one semiconductor wafer 2 60 is adhered to the convex portion 2 02 of the heat sink 2 0 with an insulating heat transfer adhesive (not shown), so that the heat generated by the wafer 2 60 can be borrowed. An insulating heat transfer adhesive (not shown) at the bottom of the chip 26 is directly conducted to the heat sink 20 to achieve the purpose of heat dissipation, and a plurality of gold wires 2 6 1 are used to electrically connect the upper circuit layer 2 3 of the wire bonding pad 2 3 1 and the electrode on the wafer 2 60, and in order to protect the wafer 2 6 0 from external electrical interference 'the wafer 2 6 2 and the gold wire can be covered with a glue 2 6 2 2 6 1 of
17172 全慰.ptd 第11頁 1222195 五、發明說明(5) 之後,將複數個銲球2g連接於該半 銲球墊24 1上,以—忐且古私也^ ♦霞封裝基板2之 雖缺,>南散熱結構之半導體封裝。 μ 述之具咼散熱結構之半導體封梦其4 ^ 直接將半導體晶片透過-絕緣傳熱膠以安置ί 土 =藉由 徒i、較好的散熱效果及較低的製作 樽 ,上製作如第2圖戶斤示之具有凸部之散熱片乍係成本姓, 式完成的。而使用姓刻的製作方法會產手括透過?方 不良、浪費散熱材料及姑刻不均勾等缺點。=片形狀17172 Total comfort. Ptd Page 11 1222195 V. Description of the invention (5) After connecting a plurality of solder balls 2g to the semi-solder ball pad 24 1, so that the ancient and private also ^ ♦ Xia package substrate 2 Although , ≫ A semiconductor package with a south heat dissipation structure. μ The semiconductor sealing dream with a heat dissipation structure described above 4 ^ Directly pass the semiconductor wafer through-insulating heat transfer adhesive to place ί Soil = by i, better heat dissipation effect and lower manufacturing bottle, the above production as the first Figure 2 shows the heat sink with convex parts at first, which is the last name. And the production method using the last name engraving will produce hand through? Disadvantages such as poor quality, wasting heat-dissipating materials, and unevenness. = Sheet shape
示,其中說明傳統上之具高散埶结構 I 之耑埶创从士上 …口稱之牛導體封裝基板中 月文…、片IL作方法之各步驟,且其内容 τ 論。 ,、門谷將於下文中進行討 請參閱第3Α圖,其中顯示一尚未進行加工 斤構成八中以鋼為較佳之選擇。該散熱材料3 〇 〇且有— —下表面3〇2a。進行敍刻製程之前/可先行 對4上表面及下表面進行表面平面化處理。 請參閱第3B圖。分別於該散熱材料3〇〇之上表面3〇1 上及下表面3 0 2a上以一層光阻層310及光阻層32〇覆蓋其1 形^有凸部之部份。因此,該散熱材料3 〇 〇於未被光阻層 覆蓋之部分形成上外緣表面303 a及下外緣表面3〇4a,而為 該光阻層所覆蓋欲形成有凸部之部分則形成上凸部表面… 30 lb及下凸部表面3 0 2b。由於蝕刻製程並不會侵蝕由光阻 層覆蓋的部份,故蝕刻製程係從該上外緣表面3 〇 3 a及該下 外緣表面3 0 4 a開始進行。It shows the steps of the traditional method of making a high-dissipation structure I from the original… nicknamed bull conductor package substrate, and the process of IL, and its content τ. , Mengu will be discussed below. Please refer to Figure 3A, which shows that one has not been processed. The heat dissipation material is 300 and has a lower surface 300a. Before and after the engraving process, the surface of the upper and lower surfaces of the 4 can be planarized. See Figure 3B. A photoresist layer 310 and a photoresist layer 32o are respectively covered on the upper surface 3001 and the lower surface 3002a of the heat-dissipating material 300 to cover the portion of the shape 1 having convex portions. Therefore, the heat-dissipating material 300 forms the upper outer edge surface 303 a and the lower outer edge surface 304 a on the portion not covered by the photoresist layer, and the portion covered by the photoresist layer to be formed with a convex portion is formed. Surface of the convex part ... 30 lb and surface of the convex part 30 2b. Since the etching process does not erode the portion covered by the photoresist layer, the etching process starts from the upper outer edge surface 3 0 a and the lower outer edge surface 3 0 4 a.
17172 全懋.ptd 1222195 五、發明說明(6) 請參閱第3C圖’其中顯示對散熱材料3 0 0進行適當之 蝕刻後所形成之散熱材料3 〇 〇。如圖所示,其中以虛線包 覆的區域為該散熱材料3 〇 〇被蝕刻去除之部分3 〇 5,使得該 散熱材料3 0 0之上下表面上形成新的上外緣表面3 〇 3b及新 白勺下外緣表面304b。此外,蝕刻製程完成後在該散熱材料 30 0上形成一上凸部3〇1及一下凸部3〇2。 請/閱第3D圖,其中顯示移除覆蓋於該散熱材 β Μ β + _ 先層32〇後所完成之用於具高 散熱結構之丰導體封裝基板之散熱片3〇。 根據上述之散埶片制祚古、土 π t 土 表面的平面性盔法達到^ & μ此外,由於蝕刻製程對於 ”无違到較佳的控制,使得所制、土 +私勒ϋ /、有新的上外緣表面3 〇 3 b及新的 ^仏月… 不佳的缺點。再者,以姓刻的方式所卜=,匕之平, 易在新的蝕刻表面間形成蝕刻不二來之散熱片今 散熱片具有形狀不佳的缺點。-勾專問喊,使所製造之 T内容】 有鑑於上述之習知缺點,本 :種半導體封裝基板之散熱;G主要目的在於提供 製作半導體封裝基板之散熱片,以羽係利用電鑛方式 刻方ίί:散熱片時所造成散熱材料藝中利用# 本《月之另一目的在於提供篇之問題。 熱片製作方法,係藉由電鍍方 ::體封裝基板之散 乂牛導體封裝基板之散17172 Quan 懋 .ptd 1222195 V. Description of the invention (6) Please refer to FIG. 3C ′, which shows the heat dissipation material 300 formed by performing appropriate etching on the heat dissipation material 300. As shown in the figure, the area enclosed by the dashed line is the portion 305 of the heat dissipation material 300 that has been etched away, so that the upper and lower surfaces of the heat dissipation material 300 form a new upper outer edge surface 300b and Lower outer edge surface 304b. In addition, after the etching process is completed, an upper convex portion 301 and a lower convex portion 302 are formed on the heat dissipation material 300. Please read / read the 3D picture, which shows the heat sink 3 for the high-conductor package substrate with high heat dissipation structure, which is removed after covering the heat sink β Μ β + _ first layer 32. The planar helmet method of making ancient and soil π t soil surfaces according to the above-mentioned scattered tablets achieves ^ & μ In addition, because the etching process does not violate the better control, the produced, soil + private ϋ / There is a new upper outer edge surface 3 〇3 b and a new ^ 仏 month ... Poor shortcomings. In addition, according to the method of the last name engraved =, Ding Zhiping, it is easy to form etching between the new etched surface The heat sink of Erlai has the shortcomings of its poor shape.-Asking to make the content of the T produced] In view of the above-mentioned conventional shortcomings, this: a type of semiconductor package substrate heat dissipation; G is mainly for the purpose of providing The heat sink of the semiconductor package substrate is made using the electricity ore method. The heat sink material is used in the heat sink. Another purpose of this month is to provide a question. The method of making the heat sink is borrowed. From the plating side :: Bulk of bulk package substrate
17172全懋.ptd 第13頁 1222195 五、發明說明(7) 熱片,以避免習知技藝中利用蝕刻方式製作散熱片時,造 成之散熱片之平面性與蝕刻不均勻等缺點。 為了達到上述及其他目的,本發明之半導體封裝基板 之散熱片製作方法係包括下列步驟:首先,提供一散熱材 料,其中該散熱材料可為具有熱的良導性質之任何金屬或 非金屬材料,若所提供之散熱材料為非金屬或未具導電性 時,可在其表面先行形成一導電金屬層以利後續電鍍製程 之執行;接著,在該散熱材料之表面覆蓋一光阻層,並於 該光阻層上形成有至少一開口,以使該散熱材料之表面欲 形成有凸部之部份外露出該光阻層開口;然後,以電鍍的 方式在該散熱材料上外露出光阻層開口之表面,形成具適 當厚度之凸部;最後,將該光阻層移除即完成用於内嵌至 一半導體封裝基板之散熱片結構。 相較於習知技藝中利用蝕刻方式製作散熱片,本發明 以電鍍方法所製作之散熱片毋須移除任何散熱材料,以避 免造成散熱材料之浪費,進一步節省生產成本。再者,以 電鍍的方式所形成之凸部之外形可輕易地依照所覆蓋之光 阻層形狀來決定,故所製造之散熱片具有良好之外形;此 外,亦可避免習知利用蝕刻製程所造成之形狀不佳與蝕刻 不均勻等問題。 【實施方式】 請參閱第4圖,其中顯示本發明之半導體封裝基板之 散熱片製作方法之實施例各步驟示意圖。 請參閱第4A圖,首先提供一散熱材料4 0 0,其具有一17172 全懋 .ptd Page 13 1222195 V. Description of the invention (7) Hot fins to avoid the disadvantages of flatness and uneven etching of the fins when the fins are made by etching in the conventional art. In order to achieve the above and other objectives, the method for manufacturing a heat sink of a semiconductor package substrate of the present invention includes the following steps: First, a heat sink material is provided, wherein the heat sink material can be any metal or non-metallic material with good thermal conductivity properties. If the heat-dissipating material provided is non-metal or non-conductive, a conductive metal layer may be formed on the surface first to facilitate the subsequent electroplating process; then, a photoresist layer is covered on the surface of the heat-dissipating material, and At least one opening is formed on the photoresist layer so that a portion of the surface of the heat dissipation material where a convex portion is to be formed exposes the photoresist layer opening; and then, the photoresist layer is exposed on the heat dissipation material by plating. A convex portion having an appropriate thickness is formed on the surface of the opening; finally, the photoresist layer is removed to complete a heat sink structure for embedding in a semiconductor package substrate. Compared with using conventional etching techniques to produce heat sinks, the heat sinks produced by the electroplating method of the present invention do not need to remove any heat sink materials, so as to avoid waste of heat sink materials and further save production costs. In addition, the outer shape of the convex portion formed by electroplating can be easily determined according to the shape of the covered photoresist layer, so the manufactured heat sink has a good outer shape; in addition, it is also possible to avoid the conventional use of an etching process. The resulting problems include poor shape and uneven etching. [Embodiment] Please refer to FIG. 4, which shows each step of a method for manufacturing a heat sink of a semiconductor package substrate according to the present invention. Referring to FIG. 4A, a heat-dissipating material 4 0 0 is first provided, which has a
17172全懋.ptd 第14頁 1222195 五、發明說明(8) "' 上表面40la及一下表面4〇2a。該散熱材料4〇 〇可由金屬或 非金屬等任何熱的良導體所構成。然而,若該散熱材料 4 0 0為非金屬或未具導電性時,則需於其上表面40 la及下 ^面4 0 2a上預先形成一導電金屬層(未圖示),俾作為後 續電鍍所需之電流傳導路徑,其可由金屬、合金或堆疊數 層金屬層所構成,可選自銅、錫、鎳、鉻、鈦、銅/路&合 金或錫/$σ 3金所構成之組群之金屬所形成,惟依實際操 作的經驗,該導電膜較佳係由銅或鈀粒子(特別是無^鑛, 所構成,可藉由物理氣相沈積(PVD)、化學氣相沈積 又 (c V D )、無電錢或化學沈澱,例如濺鍍(s P u 11 e r i n g )、蒸 鍍(evaporation)、電弧蒸氣沈積(arc vapor deposition)、離子束濺鍍(i〇ri beam sputtering)、雷射 溶散沈積(laser ablation deposition)、電衆促進之化 學氣相沈積或有機金屬之化學氣相沈積等方法,形成於該 非金屬之散熱材料表面。 請參閱第4B圖,接著於該散熱材料4 0 0之上表面4〇la 及下表面4 0 2 a上利用印刷、旋塗或貼合等方式形成有一層 光阻層4 1 0及光阻層4 2 0,該光阻層可例如為乾膜或液態光 阻專光阻層(Photoresist),並於該光阻層41 〇及4 2 0上形 成有至少一開口 40 lb及40 2b以外露出該散熱材料4〇0中欲 形成有凸部之表面,另該散熱材料4 〇 〇中為該光阻層覆蓋 之部分則為上外緣表面403a及下外緣表面4〇4a。 請麥閱第4 C圖,然後對散熱材料4 〇 〇進行電鍍製程, 俾於該散熱材料40 0上沿著開口 40 lb形成一上凸^ 401,且17172 全懋 .ptd Page 14 1222195 V. Description of the invention (8) " 'The upper surface 40la and the lower surface 402a. The heat-dissipating material 400 may be made of any heat good conductor such as metal or non-metal. However, if the heat-dissipating material 400 is non-metal or non-conductive, a conductive metal layer (not shown) needs to be formed on the upper surface 40 a and the lower surface 4 2 a in advance. The current conducting path required for electroplating can be composed of metal, alloy or stacked metal layers, which can be selected from copper, tin, nickel, chromium, titanium, copper / circuit & alloy or tin / $ σ 3 gold The group of metals is formed, but according to practical experience, the conductive film is preferably composed of copper or palladium particles (especially no ore), which can be formed by physical vapor deposition (PVD), chemical vapor phase Deposition (c VD), no electricity or chemical precipitation, such as sputtering (s Pu 11 ering), evaporation, arc vapor deposition, ion beam sputtering , Laser ablation deposition, laser-assisted chemical vapor deposition or organic metal chemical vapor deposition, etc., are formed on the surface of the non-metallic heat-dissipating material. Please refer to FIG. 4B, followed by the heat dissipation Material 4 0la on the top surface of 4 0 0 and the following table A photoresist layer 4 1 0 and a photoresist layer 4 2 0 are formed on the surface 4 0 2 a by printing, spin coating, or lamination. The photoresist layer may be, for example, a dry film or a liquid photoresist special photoresist layer. (Photoresist), and at least one opening 40 lb and 40 2b is formed on the photoresist layer 41 〇 and 4 2 0 to expose the surface of the heat dissipation material 400 where a convex portion is to be formed, and the heat dissipation material 4 〇 〇 The part covered by the photoresist layer is the upper outer edge surface 403a and the lower outer edge surface 404a. Please read Figure 4C, and then perform the electroplating process on the heat dissipation material 400. The heat dissipation material 401 is formed along the opening 40 lb along the opening ^ 401, and
17172 全懋.Ptd 第15頁 1222195 五 沿 下 熱 、發明說明(9) 一__ = 成:下凸部40 2,使得該散熱材料4°〇之上 ». /成上凸部表面401 c及下凸部表面t 材料戶斤你4、士 n a zc。而該散 y成之凸邛厚度係可依據先前覆蓋於該4為 之光1¾ r〇 τΛ- 月文熱材制》 所Θ 4:層厗度以選擇。有關電鍍技術繁多,惟t 2 所周=製程技術,故未再予資述。 &乃業界 今二芩閱第4 D圖’最後移除覆蓋於該上外緣表 ;::卜緣表面4〇4a上之光阻廣41。及光阻層42象〇表:,及 於内嵌至丰慕辦料壯 即元成用 ^ * V體封波基板之散熱片4 0,俾使該散埶 ^ 有上凸部4〇1及下凸部4〇2,且該上凸部表面、電 4表面4 0 2 c位置係高於該散執片4 〇中先前 1吸 所覆蓋部分之外❹& 了⑤%月 :甲“為該光P且, 基板於後續ϋΐί 14〇3a及下外緣表面4〇4a,俾於嵌二 傻縯封裝製程時,以供至少一半導砍入 凸部表面。 日a接置於該 很據以上 製作方法,係 -凸部,因此 之外緣部分以 散熱材料與成 蓋至該散熱材 度,使得所製 性,藉以避免 性不佳等問題 之後,可 體封裝基板中 之說明,本發明 以電鍍方式在該 相較習知技藝中 形成一具相對凸 本。而且,透過 料表面,將可較 作出之散熱片具 習知利用蝕刻製 〇 之半導體 散熱材料 藉由蝕刻 部之散熱 適當形狀 佳地控制 有較佳之 程時,造 凸部之散 熱片未形 表面上形成 方法去除散 件’將可節 與厚度之光 該凸部之形 形狀與良好 成材料浪費 省 將該電鍍完成有 ’係藉由在該散 熱片内嵌於 成有凸部之 一半導 表面形17172 Quan 懋 .Ptd Page 15 1222195 Fifth edge heat, description of the invention (9) a __ = Cheng: the lower convex part 40 2, making the heat-dissipating material above 4 ° 〇 ». / The surface of the upper convex part 401 c And the surface of the lower convex part t material households you 4, Shi na zc. The thickness of the convex ridge formed by the dispersion can be selected according to the previous coverage of the light of the 4 wei 1¾ r0 τΛ- Yuewen Hot Material Co., Ltd. Θ 4: the degree of layer thickness to choose. There are many electroplating technologies, but t 2 is equal to process technology, so it will not be described again. & It is the industry today to read the 4D figure 'and finally remove the photoresist 41 covering the upper outer edge table 40: a of the edge surface 404a. And the photoresist layer 42. Table 0: and the heat sink 40 embedded in the V-body wave-sealing substrate ^ * for V-type wave-sealing substrates, so that the scattered ^ has a convex portion 401 And the lower convex part 402, and the position of the upper convex part surface and the electric 4 surface 4 0 2 c is higher than the part covered by the previous 1 suction in the loose film 4 0 ❹ & It is the light P, and the substrate is subsequently 1440a and the lower outer surface 40a, which is used in the encapsulation process for at least half of the guide to cut into the surface of the convex portion. According to the above manufacturing method, the system is a convex part, so the outer edge part is covered with a heat-dissipating material and the heat-dissipating material, so that it can be manufactured to avoid problems such as poor performance. The invention formed a relatively convex pattern in the comparatively conventional technique by electroplating. Moreover, through the surface of the material, the semiconductor heat sink material that can be made by etching compared with the conventional heat sink can be appropriately dissipated by the etched part. When the shape is controlled well, the convex part of the heat sink is formed on the unshaped surface. Removal of scattered member 'may be the light-shaped section and the thickness of the projecting portion of the waste material into a shape with good electroplating is the province have' lines by half of the guide surface of the convex portions formed in the heat sink is embedded in to
第16頁 1222195 五、發明說明(ίο) 成至少一絕緣層與至少一電路層,以形成一半導體封裝基 板,俾可提供至少一半導體晶片得以接置於該散熱片之凸 部上(如第2圖所示),以透該散熱片之凸部將晶片產生之 熱量傳導至外界。 本發明之半導體封裝基板之散熱片製作方法中係可在 一金屬或非金屬等良好散熱材料上利用電鍍方式於該散熱 材料上形成有至少一凸部,先前圖式中雖於該散熱材料之 上下表面皆形成有一凸部,而實際上該凸部亦可單獨形成 於該散熱材料一表面上,以供安置有一半導體晶片,亦或 於該散熱材料之一表面上電鍍形成有多數之凸部,以供接 置有多數之半導體晶片,惟以上所揭示之内容僅為本發明 之較佳實施例,並非用於侷限本發明之技術範圍。本發明 之實質技術内容係廣義地定義於以下之申請專利範圍中, 任何他人所完成之技術實體或方法若與下列申請專利範圍 完全相同或僅為等同之變更或修改,均得視為涵蓋於本發 明之精神及範疇之内。Page 16 1222195 V. Description of the Invention (ίο) At least one insulating layer and at least one circuit layer are formed to form a semiconductor package substrate, and at least one semiconductor wafer can be provided on the convex portion of the heat sink (such as the first (Shown in Figure 2), the heat generated by the chip is conducted to the outside through the convex portion of the heat sink. In the manufacturing method of the heat sink of the semiconductor package substrate of the present invention, at least one convex portion can be formed on the heat sink by electroplating on a good heat sink material such as metal or nonmetal. A convex portion is formed on both the upper and lower surfaces. In fact, the convex portion may be separately formed on one surface of the heat-dissipating material for mounting a semiconductor wafer, or a plurality of convex portions may be formed by electroplating on one surface of the heat-dissipating material. In order to connect and install a large number of semiconductor wafers, the content disclosed above is only a preferred embodiment of the present invention, and is not intended to limit the technical scope of the present invention. The substantial technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by another person that is completely the same as the scope of the patent application below or is only equivalent changes or modifications can be deemed to be covered by Within the spirit and scope of the present invention.
17172 全懋.ptd 第17頁 1222195 圖式簡單說明 【圖示簡單說明】 第1圖係習知技藝之半導體基板剖面示意圖,其中顯 示以導熱栓作為散熱結構之半導體封裝基板; 第2圖係習知技藝之半導體封裝基板剖面示意圖,其 中顯示具有高散熱結構散熱片之半導體封裝基板; 第3A圖至第3D圖係習知技藝之半導體封裝基板高散熱 結構散熱片製作方法流程步驟之剖面示意圖;以及 第4A圖至第4D圖係本發明之半導體封裝基板之散熱片 製作方法流程步驟之剖面示意圖。 1 半導體封裝基板 10 散熱片 100 上表面 101 下表面 11 上樹脂層 110 導通孔 12 下樹脂層 13 上電路層 131 打線墊 14 下電路層 141 鲜球塾 15 導電栓 16 導熱栓 160 晶片 161 金線 162 封膠 17 拒銲層 18 拒銲層 19 輝球 2 半導體封裝基板 20 散熱片 200 上表面 201 下表面 202 上凸部 203 中心部 204 下凸部 21 上樹脂層 210 導通孔17172 Quan 懋 .ptd Page 17 1222195 Brief description of the diagram [Simplified illustration of the diagram] Figure 1 is a schematic cross-sectional view of a semiconductor substrate of a conventional technology, which shows a semiconductor package substrate using a thermal conductive plug as a heat dissipation structure; A cross-sectional schematic diagram of a semiconductor packaging substrate of a known technology, which shows a semiconductor packaging substrate with a high heat dissipation structure heat sink; Figures 3A to 3D are cross-sectional schematic diagrams of the process steps of a method for manufacturing a high heat dissipation structure of a semiconductor package substrate of a conventional technology; And FIGS. 4A to 4D are schematic cross-sectional views of the steps of a method for manufacturing a heat sink of a semiconductor package substrate of the present invention. 1 semiconductor package substrate 10 heat sink 100 upper surface 101 lower surface 11 upper resin layer 110 via hole 12 lower resin layer 13 upper circuit layer 131 wire bonding pad 14 lower circuit layer 141 fresh ball 塾 15 conductive pin 16 thermal pin 160 chip 161 gold wire 162 Sealant 17 Solder resist layer 18 Solder resist layer 19 Glow ball 2 Semiconductor package substrate 20 Heat sink 200 Upper surface 201 Lower surface 202 Upper convex portion 203 Center portion 204 Lower convex portion 21 Upper resin layer 210 Via hole
17172 全懋.ptd 第18頁 1222195 圖式簡單說明 22 下 樹 脂 層 23 上 電 路 層 231 打 線 墊 24 下 電 路 層 241 銲 球 墊 25 導 電 栓 260 晶 片 261 金 線 262 封 膠 27 拒 銲 層 28 拒 辉 層 29 銲 球 30 散 熱 片 300 散 熱 材 料 301 上 凸 部 301a 上 表 面 301b 上 凸 部 表 面 302 下 凸 部 3 0 2a 下 表 面 3 0 2b 下 凸 部 表 面 3 0 3a 上 外 緣 表 面 3 0 3b 新 的 上 外 緣 表 面 3 0 4a 下 外 緣 表 面 3 0 4b 新 的 下 外 緣 表 面 305 去 除 部 310 光 阻 層 320 光 阻 層 40 散 熱 片 400 散 孰 材 料 401 上 凸 部 401a 上 表 面 401b 開 D 401c 上 凸 部 表 面 402 下 凸 部 4 0 2a 下 表 面 40 2b 開 σ 4 0 2c 下 凸 部 表 面 4 0 3a 上 外 緣 表 面 4 0 4a 下 外 緣 表 面 410 光 阻 層 420 光 阻 層17172 Full 懋 .ptd Page 18 1222195 Brief description of the diagram 22 Lower resin layer 23 Upper circuit layer 231 Wire bonding pad 24 Lower circuit layer 241 Solder ball pad 25 Conductive plug 260 Chip 261 Gold wire 262 Sealant 27 Solder resist layer 28 Resist glow Layer 29 Solder ball 30 Heat sink 300 Heat dissipating material 301 Upper protrusion 301a Upper surface 301b Upper protrusion surface 302 Lower protrusion 3 0 2a Lower surface 3 0 2b Lower protrusion surface 3 0 3a Upper outer edge surface 3 0 3b New Upper outer edge surface 3 0 4a Lower outer edge surface 3 0 4b New lower outer edge surface 305 Removed portion 310 Photoresist layer 320 Photoresist layer 40 Heat sink 400 Bulk material 401 Upper convex portion 401a Upper surface 401b Open D 401c On Convex surface 402 lower convex portion 4 0 2a lower surface 40 2b opening σ 4 0 2c lower convex surface 4 0 3a upper outer edge surface 4 0 4a lower outer edge surface 410 photoresist layer 420 photoresist layer
17172 全想.ptd 第19頁17172 Think All.ptd Page 19
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