TW200423347A - Method for fabricating heat sink of semiconductor packaging substrate - Google Patents
Method for fabricating heat sink of semiconductor packaging substrate Download PDFInfo
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- TW200423347A TW200423347A TW092109195A TW92109195A TW200423347A TW 200423347 A TW200423347 A TW 200423347A TW 092109195 A TW092109195 A TW 092109195A TW 92109195 A TW92109195 A TW 92109195A TW 200423347 A TW200423347 A TW 200423347A
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- heat sink
- heat
- heat dissipation
- photoresist layer
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
200423347 五、發明說明（1) -ί發明所屬之技術領域】 本發明係有關於半導體封裝基板之散熱片製作方法， 尤指利用電鍍方式在散熱片上形成凸部之製作方法，俾將 該散熱片内嵌於半導體封裝基板中。 【先前技術】 隨著積體電路製造技術的進步，在單一晶片上可沉積 越來越多的半導體元件。由於每一個半導體元件在運作的 過程中，或多或少都會耗散出熱量，因此之故隨著半導體 元件積集度的增加，使得單一晶片所耗散出來的熱量也越 多。若不莾提供一有效的散熱機制，則在晶片上所累1 積的熱量可導致晶片上之溫度升高到操作溫度以上，進而 導致該晶片無法正常運作，甚至影響晶片之壽命。在一般 的情形下，半導體晶片中的熱量耗散係藉由在半導體晶片 之封裝基板中，製作一種由導熱材料所構成的散熱結構來 達成。 請參閱第1圖，其係顯示習知技藝中以導熱栓作為散 熱結構之半導體封裝基板。該半導體封裝基板1包括一具 有一上表面10 0及一下表面10 1之散熱片10、一壓合於該散 熱片1 0上表面1 0 0之上樹脂層1 1、一壓合於該散熱片1 0下 #面1 0 1之下樹脂層1 2、一形成於該上樹脂層1 1之上電路 層1 3、一形成於該下樹脂層1 2之下電路層1 4、以及複數個 導電栓1 5與導熱栓16。為保護上下層之電路，故於該上電 路層1 3與該下電路層1 4上分別塗覆有一拒銲層1 7、1 8。 " 該散熱片1 0係内嵌於該半導體封裝基板1中，以作為200423347 V. Description of the invention (1)-The technical field to which the invention belongs] The present invention relates to a method for manufacturing a heat sink for a semiconductor package substrate, and more particularly to a method for forming a convex portion on a heat sink by electroplating. Embedded in a semiconductor package substrate. [Previous technology] With the development of integrated circuit manufacturing technology, more and more semiconductor elements can be deposited on a single wafer. Since each semiconductor element dissipates heat to a greater or lesser degree during its operation, as the accumulation of semiconductor elements increases, the more heat is dissipated from a single chip. If you do not provide an effective heat dissipation mechanism, the accumulated heat on the wafer can cause the temperature on the wafer to rise above the operating temperature, which will cause the wafer to malfunction and even affect the life of the wafer. In general, the heat dissipation in a semiconductor wafer is achieved by making a heat dissipation structure made of a thermally conductive material in the packaging substrate of the semiconductor wafer. Please refer to FIG. 1, which shows a semiconductor package substrate using a thermally conductive plug as a heat dissipation structure in the conventional art. The semiconductor package substrate 1 includes a heat sink 10 having an upper surface 100 and a lower surface 101, a resin layer 11 laminated on the upper surface 100 of the heat sink 10, and a heat sink laminated on the heat sink 10. Sheet 10 lower #surface 1 0 1 resin layer 1 below 2, a circuit layer 1 formed on the upper resin layer 1 1 a circuit layer 1 4 formed on the lower resin layer 1 2 and a plurality of Various conductive bolts 15 and 16. In order to protect the upper and lower circuits, solder resist layers 17 and 18 are respectively coated on the upper circuit layer 13 and the lower circuit layer 14. " The heat sink 10 is embedded in the semiconductor package substrate 1 as
17172全懋.ptd. 第8頁 200423347 五、發明說明（2) 該半導體封裝基板丨之散熱結構。此外，並於該散熱片i 〇 上鑽馨有複數個導通孔1 1 〇，用以裝設該複數個導電栓i 5 及複數1固導熱栓1 6。當該上樹脂層1 1及該下樹脂層1 2之絕 緣樹脂壓合於該散熱片i 〇後，該絕緣樹脂得填滿該散熱片 之導通孔1 1 0。 ' 該上電路層1 3係佈置於該上樹脂層1 1之表面，並於其 上設置有複數個打線墊1 3丨，俾於該上電路層丨3覆蓋一層 拒鲜層1 7之後’該打線墊1 3 1得露出該拒銲層1 7之開口， 以供金線1 6 1得以電性連接該晶片1 6 〇與該基板卜 )该下，路廣1 4係佈置於該下樹脂層1 2之表面，並於g 上=置有複數個銲球墊丨4丨，俾於該下電路層丨4覆蓋一芦〃、 拒紅層1 8之後，該複數個銲球墊丨4丨得露出該拒銲層1 8 開口，以供該複數個銲球墊141與銲球19相連接。 =复數個導電栓15係貫穿該上樹脂層u、該 及該下樹脂層12使上電路層13與下電路層14 ;;二？接… =古π祕β 口位，且於忒導電栓1 5與該導通孔1 1 0之間隙填 充有、纟巴緣樹脂以防止短路發生。 ’、真 ιη =數個導熱栓16亦係' 貫穿該上樹脂ΙΗ、肖散熱片-旦ί V L孔1 1 0及該下樹脂層1 2使該晶片1 6 0上所產生^埶 里付以，v至邊散熱片i 0 ’以達到散熱的功能。 …、 =施封裝時，將至少一個半導體晶片16〇以絕緣 ^ (未圖示）黏著於該基板具有導熱栓16之表面 區 域，使晶片上所產生的熱量得以藉由該晶片16〇底 /17172 全懋 .ptd. Page 8 200423347 V. Description of the Invention (2) The heat dissipation structure of the semiconductor package substrate. In addition, a plurality of through holes 1 1 0 are drilled on the heat sink i 0 for installing the plurality of conductive bolts i 5 and the plurality of solid heat conducting bolts 16. After the insulating resins of the upper resin layer 11 and the lower resin layer 12 are pressed on the heat sink i 0, the insulating resin must fill the through holes 1 1 0 of the heat sink. 'The upper circuit layer 1 3 is arranged on the surface of the upper resin layer 1 1, and a plurality of wire bonding pads 1 3 丨 are arranged thereon, after the upper circuit layer 丨 3 is covered with a freshness prevention layer 17' The wire bonding pad 1 3 1 has to expose the opening of the solder resist layer 17 so that the gold wire 1 6 1 can be electrically connected to the wafer 16 and the substrate. B) The Lu Guang 1 4 series is arranged under the The surface of the resin layer 12 is provided with a plurality of solder ball pads on g = 4, and the lower circuit layer is covered with a reed, and the red-rejecting layer is 18, and the plurality of solder ball pads are provided. The opening of the solder resist layer 18 may be exposed for the plurality of solder ball pads 141 to be connected to the solder balls 19. = A plurality of conductive plugs 15 penetrate the upper resin layer u, the lower resin layer 12 and the upper circuit layer 13 and the lower circuit layer 14; Connect ... = ancient π secret β mouth, and fill the gap between the conductive pin 15 and the via hole 1 10 with a resin, to prevent short circuit. ', True ιη = several thermally conductive bolts 16 are also through' penetrating the upper resin 1Η, Xiao heat sink-dan VL hole 1 1 0 and the lower resin layer 12 2 so that the wafer 1 6 0 is generated Therefore, v to the side heat sink i 0 ′ is used to achieve the function of heat dissipation. …, = At least one semiconductor wafer 16 is adhered to the surface area of the substrate having the thermally conductive plug 16 with insulation ^ (not shown) during packaging, so that the heat generated on the wafer can pass through the wafer 160 /
200423347 五、發明說明（3) -緣傳熱勝（未圖示）傳導至該導熱栓1 6，再傳導至該散熱 片1 0，以達到散熱的目的。該上電路層丨3之打線墊丄3 i係 通過複數條金線1 6 1而與晶片1 β 〇上之銲墊相連接。 > 該晶片160不受外界電性干擾，可用一封膠16 片16〇及該金線m之上。最後，將複數個銲球丨接^ = -半導體封裝基板丨之鲜球塾141上，以完成具散 導體封裝。 、。偁之+ 然而，上述以導熱栓作為 中’用於將晶片上所產生之熱 工^*之導熱栓，，其與晶片之接 設於該散熱片之中故為其製作 驟。如此，不但散熱效果不盡 必要的製作成本。 月文熱結構之半導體封裝件 量傳送至散熱片以完成:散熱 觸截面積極小，且因並 ： 過程增加了許多不必要；牙 理想，亦同時增加了許多不 有鑑於上遠習知半導體封裝基板之缺點，於 專利公報第4 5 7 8 3 6號公告中揭露了一種「呈古 3 ^ 异呵散熱丰莫興 封裝基板結構及其製作方法」。請參閱第2圖，其中顯厂、豆 該項專利公告中所揭露之具高散熱結構之半導體封^其1" 板。該半導體封裝基板2包括一具有一上表面2^〇及二土 ^2 0 1之散熱片20、一壓合於該散熱片2〇上表面2〇〇之If 月P層2卜一壓合於該散熱片2 0下表面2 〇 1之下樹脂層 Μ 一形成於該上樹脂層21之上電路層23、一形成於下' 層2 2之下電路層24、以及複數個導電栓25。 s曰 該散熱片2 〇亦内嵌於該半導體封裝基板2之中，σ 為該半導體封裝基板2之散熱結構，里呈右_ μ ， 上凸部2〇2、200423347 V. Description of the invention (3)-Edge heat transfer (not shown) is conducted to the thermal pin 16 and then to the heat sink 10 to achieve the purpose of heat dissipation. The bonding pads 3 i of the upper circuit layer 3 are connected to the bonding pads on the wafer 1 β 0 through a plurality of gold wires 16 1. > The chip 160 is free from external electrical interference, and a piece of glue 16 and 16 can be used above the gold wire m. Finally, a plurality of solder balls are connected to the fresh balls 141 of ^ =-semiconductor package substrate to complete a bulk conductor package. .偁 之 + However, the above-mentioned heat-conducting bolt is used as the medium 'for the heat-conducting bolt generated on the wafer, and its connection with the wafer is placed in the heat sink, so it is made. In this way, not only the heat dissipation effect is not necessary, but also the manufacturing cost is not necessary. The amount of the semiconductor package of the thermal structure of the moon is transferred to the heat sink for completion: the thermal contact cross section is very small, and due to: the process adds a lot of unnecessary; the tooth is ideal, and at the same time it adds a lot of semiconductor packages that are not known in the past The shortcomings of the substrate are disclosed in Patent Publication No. 4 5 7 8 3 6 which is a "Chenggu 3 ^ Dihe heat dissipation Feng Moxing package substrate structure and its manufacturing method." Please refer to FIG. 2, which shows a semiconductor package with a high heat dissipation structure disclosed in the patent notice of the factory and bean ^ its 1 " board. The semiconductor package substrate 2 includes a heat sink 20 having an upper surface 2 ^ 〇 and two earth ^ 2 01, and an If-P layer 2 laminated on the upper surface 200 of the heat sink 2 and laminated. A resin layer M is formed below the lower surface of the heat sink 20, a circuit layer 23 is formed on the upper resin layer 21, a circuit layer 24 is formed below the lower layer 2, and a plurality of conductive plugs 25 are formed. . s: The heat sink 20 is also embedded in the semiconductor package substrate 2. σ is the heat dissipation structure of the semiconductor package substrate 2. It has a right-side μ_2 and an upper convex portion 202.
17172全懋.ptd .17172 Full 懋 .ptd.
200423347 -— —^—__ 五、發明說明（4) ^------- 一中心4 2 0 3及—下凸部2 〇 4。此外， I右福數個暮、s 工於5亥散熱片2 0上鑽 鑿有祓^ V通孔210,用以裝設該複數個導 2 該上樹脂層2 1及該下樹脂層2 2之絕緣樹月t懕入歹田 2〇後’該絕緣樹脂得填滿該散熱片 上23係佈置於該上樹脂層21之表面，並於其 ί ^ Ϊ 線塾231，俾於該上電路層23覆蓋一層 拒銲層27之後’該打線墊231得露出該拒銲層27之開口， 以供金線2 6 1電性連接該晶片2 6 〇與該基板2。 該下電路層24係佈置於該下樹脂層22之表面，並 上設置有複數、個銲球墊2 4 1，俾於該下電路層2 4覆蓋—層， 拒銲層28之後、，該複數個銲球墊241得露出該拒銲層28^ 開口，以供該複數個銲球墊2 4丨與銲球2 9相連接。 。玄複數個‘电栓2 5係貫穿該上樹脂層2丨、該散熱片2 ( 之導通孔21〇及該下樹脂層22使上電路層23與下電路層24 得以相互電性連接。其中’言亥導電栓25之口徑係小於該通 孔210之口徑，且於該導電栓25與該導通孔2ι〇之間隙填充 有絕緣树導脂以防止短路發生。 、 在二知封裝蛉，將至少一個半導體晶片2 6 〇以絕 熱膠（未圖示）黏著於該散熱片2〇之凸部2〇2上，使該： 片所產生的熱量得以藉由該晶片26〇底部之絕緣傳敎膜 、Ϊ J : : Ϊ Ϊ Ϊ導至該散熱片20，以達到散熱的目的， 亚利用曰複數條金線261以電性連接該上電路層㈡之打線塾 2 3 m曰曰片2 6 0上之電極，而為保護該晶片2 6 〇不受 性干擾，可用一封膠2 6 2包覆於該晶片26〇及該金線261之200423347-— — ^ — __ 5. Description of the invention (4) ^ ------- a center 4 2 0 3 and-a lower convex portion 2 04. In addition, a few V and V through holes 210 were drilled on the heat sink 2 0 of the right side and the right side to install the plurality of guides 2, the upper resin layer 2 1 and the lower resin layer 2. After the insulation tree t of 2 enters Putian 20, the insulation resin must fill the heat sink 23, which is arranged on the surface of the upper resin layer 21, and 于 塾 塾 塾 231 on the upper circuit. After the layer 23 covers a solder resist layer 27, the wire bonding pad 231 must expose the opening of the solder resist layer 27 for the gold wire 2 61 to electrically connect the wafer 2 6 to the substrate 2. The lower circuit layer 24 is arranged on the surface of the lower resin layer 22, and a plurality of solder ball pads 2 4 1 are arranged on the lower circuit layer 24 to cover the layer. After the solder resist layer 28, the The plurality of solder ball pads 241 have to expose the openings of the solder resist layer 28 ^ for the plurality of solder ball pads 2 4 丨 to be connected to the solder balls 29. . A plurality of “electric bolts 2 5” penetrate the upper resin layer 2 丨, the through holes 21 of the heat sink 2 (and the lower resin layer 22, so that the upper circuit layer 23 and the lower circuit layer 24 can be electrically connected to each other. 'The diameter of the conductive plug 25 is smaller than the diameter of the through hole 210, and a gap between the conductive plug 25 and the through hole 2m is filled with an insulating tree conductive grease to prevent a short circuit. At least one semiconductor wafer 26 is adhered to the convex portion 202 of the heat sink 20 with a heat-insulating adhesive (not shown), so that the heat generated by the wafer can be transmitted through the insulation at the bottom of the wafer 26. The film, Ϊ J:: Ϊ Ϊ Ϊ is led to the heat sink 20 to achieve the purpose of heat dissipation. A plurality of gold wires 261 are used to electrically connect the upper circuit layer of the wire 塾 2 3 m 曰 2 2 Electrode on 0, and in order to protect the wafer 2 6 0 from sexual interference, a piece of glue 2 6 2 can be used to cover the wafer 26 0 and the gold wire 261.
200423347 五、發明說明（5) -上，之後，將複數個銲球2 9連接於該半導體封裝基板2之 銲球墊2 4 1上，以完成具高散熱結構之半導體封裝。 雖然’上述之具南散熱結構之半導體封裝基板係藉由 直接將半導體晶片透過一絕緣傳熱膠以安置在一散熱結構 -上，俾能提供較好的散熱效杲及較低的製作成本，但是傳 -統上製作如第2圖所示之具有凸部之散熱片係透過蝕刻方 式完成的。而使用蝕刻的製作方法會產生包括散熱片形狀 不良、浪費散熱材料及蝕刻不均勻等缺點。如第3圖所 示，其中說明傳統上之具高散熱結構之半導體封裝基板中 之·(：熱片製作芕法之各步驟，且其内容將於下文中進行討1 論。 請參閱第3 Α圖，其中顯示一尚未進行加工之散熱材料 3 0 0。該散熱材料3 0 0可由金屬或非金屬等任何熱的良導體 所構成，，其中以銅為較佳之選擇。該散熱材料3 0 0具有一 上表面301a及一下表面302a。進行蝕刻製程之前，可先行 對該上表面及下表面進行表面平面化處理。 " 請參閱第3 B圖。分別於該散熱材料3 0 0之上表面3 0 1 a 上及下表面3 0 2 a上以一層光阻層3 1 0及光阻層3 2 0覆蓋其欲 形成有凸部之部份。因此，該散熱材料3 0 0於未被光阻層 之部分形成上外緣表面3 0 3 a及下外緣表面3 0 4 a，而為 該光阻層所覆蓋欲形成有凸部之部分則形成上凸部表面 3 0 1 b及下ib部表面3 0 2 b。由於姓刻製程並不會侵I虫由光阻 層覆蓋的部份，故蝕刻製程係從該上外緣表面3 0 3 a及該下 外緣表面3 0 4 a開始進行。200423347 V. Description of the invention (5)-After that, a plurality of solder balls 29 are connected to the solder ball pads 2 41 of the semiconductor package substrate 2 to complete a semiconductor package with a high heat dissipation structure. Although the above-mentioned semiconductor package substrate with a south heat dissipation structure is disposed on a heat dissipation structure by directly passing the semiconductor wafer through an insulating heat transfer adhesive, it can provide better heat dissipation efficiency and lower manufacturing costs. However, conventionally, the production of a heat sink with convex portions as shown in FIG. 2 is completed by etching. However, the manufacturing method using etching has disadvantages including bad shape of the heat sink, waste of heat dissipation material, and uneven etching. As shown in Figure 3, which explains the various steps in the traditional semiconductor package substrate with a high heat dissipation structure (: hot-film fabrication method), and its content will be discussed below. Please refer to Section 3 A, which shows a heat-dissipating material 300 that has not been processed. The heat-dissipating material 300 can be composed of any good heat conductor such as metal or non-metal, and copper is the better choice. The heat-dissipating material 3 0 0 has an upper surface 301a and a lower surface 302a. Before the etching process, the surface of the upper surface and the lower surface can be planarized. &Quot; Please refer to FIG. 3B. Above the heat dissipation material 300 respectively The surface 3 0 1 a is covered by a photoresist layer 3 1 0 and a photoresist layer 3 2 0 on the upper and lower surfaces 3 0 2 a. Therefore, the heat dissipation material 3 0 0 The portion covered by the photoresist layer forms the upper outer edge surface 3 0 3 a and the lower outer edge surface 3 0 4 a, and the portion covered by the photoresist layer to form the convex portion forms the upper convex surface 3 0 1 b And the lower surface of the ib part 3 0 2 b. Because the surname engraving process will not invade the I covered by the photoresist layer Parts, so the etching process from the upper lines 3 0 3 a peripheral surface and the lower surface of the outer edge 3 0 4 a started.
17172全懋.ptd . 第12頁 200423347 五、發明說明（6) 請參閱第3 C圖，其中顯示對散熱材料3 0 0進行適當之 Ί虫刻後所形成之散熱材料3 0 0。如圖所示，其中以虛線包 覆的區域為該散熱材料3 0 0被蝕刻去除之部分3 0 5，使得該 散熱材料3 0 0之上下表面上形成新的上外緣表面3 0 3 b及新 的下外緣表面3 0 4b。此外，蝕刻製程完成後在該散熱材料 3 0 0上形成一上凸部3 0 1及一下凸部3 0 2。 最後，請參閱第3 D圖，其中顯示移除覆蓋於該散熱材 料3 0 0表面之光阻層3 1 0及光阻層3 2 0後所完成之用於具高 散熱結構之半導體封裝基板之散熱片3 0。 根據上述、之散熱片製作方法可知，透過蝕刻的方式β 去除部分3 0 5移除所製造出來之散熱片浪費了許多散熱材 料，因此不具有成本上的效益。此外，由於蝕刻製程對於 表面的平面性無法達到較佳的控制，使得所製造之散熱片 具有新的上外緣表面3 0 3 b及新的下外緣表面3 0 4 b之平面性 不佳的缺點。再者，以蝕刻的方式所製造出來之散熱片容 易在新的蝕刻表面間形成蝕刻不均勻等問題，使所製造之 散熱片具有形狀不佳的缺點。 【内容】 有鑑於上述之習知缺點，本發明之主要目的在於提供 一種半導體封裝基板之散熱片製作方法，係利用電鍍方式 製作半導體封裝基板之散熱片，以避免習知技藝中利用蝕 刻方式製作散熱片時所造成散熱材料浪費之問題。 本發明之另一目的在於提供一種半導體封裝基板之散 熱片製作方法，係藉由電鍍方式製作半導體封裝基板之散17172 全懋 .ptd. Page 12 200423347 V. Description of the invention (6) Please refer to Figure 3C, which shows the heat dissipation material 3 0 0 formed after the appropriate heat engraving of the heat dissipation material 3 0 0. As shown in the figure, the area enclosed by the dashed line is the part 305 of the heat dissipation material 300 that has been removed by etching, so that a new upper outer edge surface 3 0 3 b is formed on the upper and lower surfaces of the heat dissipation material 300. And the new lower outer edge surface 3 0 4b. In addition, after the etching process is completed, an upper convex portion 301 and a lower convex portion 302 are formed on the heat dissipation material 300. Finally, please refer to FIG. 3D, which shows a semiconductor package substrate with a high heat dissipation structure completed after removing the photoresist layer 3 110 and the photoresist layer 3 2 0 covering the surface of the heat dissipation material 300. Of heat sink 3 0. According to the above-mentioned method for manufacturing a heat sink, it can be known that removing the manufactured heat sink through the β-removing portion 3 05 through the etching method wastes a lot of heat-dissipating materials, so it is not cost effective. In addition, because the etching process cannot achieve better control over the planarity of the surface, the manufactured heat sink has a new upper outer edge surface 3 0 3 b and a new lower outer edge surface 3 0 4 b. Shortcomings. In addition, the heat sink manufactured by etching is easy to form problems such as uneven etching between the new etched surfaces, so that the manufactured heat sink has the disadvantage of poor shape. [Content] In view of the conventional shortcomings described above, the main purpose of the present invention is to provide a method for manufacturing a heat sink for a semiconductor package substrate. The problem of wasting heat dissipation material caused by the heat sink. Another object of the present invention is to provide a method for manufacturing a heat dissipating sheet for a semiconductor package substrate.
17172全懋.ptd. 第13頁 200423347 五、發明說明（7) -熱片，以避免習知技藝中利用蝕刻方式製作散熱片時，造 成之散熱片之平面性與钱刻不均勻等缺點。 " 為了達到上述及其他目的，本發明之半導體封裝基板 之散熱片製作方法係包括下列步驟：首先，提供一散熱材 -料，其中該散熱材料可為具有熱的良導性質之任何金屬或 -非金屬材料，若所提供之散熱材料為非·金屬或未具導電性 時，可在其表面先行形成一導電金屬層以利後續電鍍製程 之執行；接著，在該散熱材料之表面覆蓋一光阻層，並於 該光阻層上形成有至少一開口 ，以使該散熱材料之表面欲 形φί有凸部之f卩份外露出該光阻層開口；然後，以電鍍的^ 方式在該散熱材料上外露出光阻層開口之表面，形成具適 當厚度之凸部；最後，將該光阻層移除即完成用於内嵌至 一半導體封裝基板之散熱片結構。 相較於習知技藝中利用蝕刻方式製作散熱片，本發明 以電鍍方法所製作之散熱片毋須移除任何散熱材料，以避 免造成散熱材料之浪費，進一步節省生產成本。再者，以 龠鍍的方式所形成之凸部之外形可輕易地依照所覆蓋之光 阻層形狀來決定，故所製造之散熱片具有良好之外形；此 外，亦可避免習知利用蝕刻製程所造成之形狀不佳與蝕刻 肩句勻等問題。 【實施方式】 請參閱第4圖，其中顯示本發明之半導體封裝基板之 散熱片製作方法之實施例各步驟示意圖。 請參閱第4 A圖，首先提供一散熱材料4 0 0，其具有一17172 全懋 .ptd. Page 13 200423347 V. Description of the invention (7)-Heat fins to avoid the disadvantages of flatness and unevenness of the fins when the heat sink is made by etching in the conventional art. " In order to achieve the above and other objectives, the method for manufacturing a heat sink of a semiconductor package substrate of the present invention includes the following steps: First, a heat sink material is provided, wherein the heat sink material can be any metal having good thermal conductivity or -Non-metallic materials. If the heat-dissipating material provided is non-metallic or non-conductive, a conductive metal layer can be formed on the surface to facilitate the subsequent plating process. Then, the surface of the heat-dissipating material is covered with a A photoresist layer, and at least one opening is formed on the photoresist layer, so that the surface of the heat-dissipating material is shaped like a convex portion, and the opening of the photoresist layer is exposed; A surface of the photoresist layer opening is exposed on the heat dissipation material to form a convex portion with an appropriate thickness. Finally, the photoresist layer is removed to complete a heat sink structure for embedding in a semiconductor package substrate. Compared with using conventional etching techniques to produce heat sinks, the heat sinks produced by the electroplating method of the present invention do not need to remove any heat sink materials, so as to avoid waste of heat sink materials and further save production costs. In addition, the outer shape of the convex portion formed by the hafnium plating method can be easily determined according to the shape of the covered photoresist layer, so the manufactured heat sink has a good outer shape; in addition, the conventional etching process can be avoided. The resulting shape is poor and the etching is uniform. [Embodiment] Please refer to FIG. 4, which shows each step of a method for manufacturing a heat sink of a semiconductor package substrate according to the present invention. Referring to FIG. 4A, a heat dissipating material 4 0 0 is first provided, which has a
17172 全懋.ptd 第14頁 20042334717172 懋 .ptd p. 14 200423347
上表面401 a及一下表面4〇2a。* 非金屬等任何埶的良導m _该散熱材料400可由金屬或 竭非金屬或未Λ構成。然而，若該散熱材料 ^, 4〇2a. Ta"τ, 續電鍍所需之電流傳導路二(未圖不）’俾作為後 層金屬層所構成，；=，其可由金屬、合金或堆疊數 a / 了遠自銅、錫、鎳、鉻、鈦、銅/鉻合 二^、备''所構成之組群之金屬所形成，惟依實際操 4的經驗，该導電膜較佳係由銅或鈀粒子（特別是無電鍍） 所構成，可藉由物理氣相沈積（PVD)、化學氣相沈積 (CVD)、無電錁或化學沈澱，例如濺鍍（sputtering)、蒸1 鍍（evaporation)、電弧蒸氣沈積（arc vap〇r deposition)、肖隹子束錢鍍（i〇n beam sputtering)、雷射 熔散沈積（laser ablation deposition)、電漿促進之化 學氣相，沈積或有機金屬之化學氣相沈積等方法，形成於該 非金屬之散熱材料表面。 請參閱第4 B圖，接著於該散熱材料4 〇 〇之上表面4 0 1 a 及下表面4 0 2 a上利用印刷、旋塗或貼合等方式形成有一層 光阻層4 1 0及光阻層4 2 0，該光阻層可例如為乾膜或液態光 阻等光阻層（Photoresist)，並於該光阻層41〇及42 0上形 成有至少一開口 401 b及4 0 2 b以外露出該散熱材料& 〇 〇中欲 形成有凸部之表面’另該散熱材料4 0 〇中為該光阻層覆蓋 之部分則為上外緣表面4 0 3 a及下外緣表面4 〇 4 a。 請參閱第4 C圖，然後對散熱材料4 0 〇進行電鍵製程， 俾於該散熱材料4 0 0上沿著開口 4 0 1 b形成〜上凸部4 〇 1，且The upper surface 401 a and the lower surface 402 a. * A good guide m for any metal such as non-metal _ The heat-dissipating material 400 may be made of metal or non-metal or non-Λ. However, if the heat-dissipating material ^, 4〇2a. Ta " τ, the current conducting path 2 (not shown in the figure) required for continued electroplating is constituted by the back metal layer; =, it may be made of metal, alloy or stack The number a / is far from the metal formed by the group consisting of copper, tin, nickel, chromium, titanium, copper / chromium ^, preparation, but according to the actual experience, the conductive film is preferably Consisting of copper or palladium particles (especially electroless plating), which can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless or chemical precipitation, such as sputtering, vapor deposition ( evaporation), arc vapor deposition, ino beam sputtering, laser ablation deposition, plasma-assisted chemical vapor phase, deposition or organic A method such as chemical vapor deposition of metal is formed on the surface of the non-metallic heat dissipation material. Referring to FIG. 4B, a photoresist layer 4 1 0 and a photoresist layer 4 1 0 are formed on the upper surface 4 0 1 a and the lower surface 4 2 a of the heat dissipation material 400 by printing, spin coating, or lamination. Photoresist layer 4 2 0. The photoresist layer may be, for example, a photoresist layer such as a dry film or a liquid photoresist, and at least one opening 401 b and 40 are formed in the photoresist layers 41 and 42. The surface of the heat-dissipating material & 〇2 where the convex portion is to be formed is exposed outside 2b. In addition, the portion covered by the photoresist layer in the heat-dissipating material 400 is the upper outer edge surface 4 0 3a and the lower outer edge. Surface 4 〇4 a. Please refer to FIG. 4C, and then perform a key bonding process on the heat dissipation material 400, and form an upper convex portion 4〇1 along the opening 4 0 1 b on the heat dissipation material 400, and
200423347 五、發明說明（9) …沿著開口 4 0 2 b形成一下凸部4 0 2，使得該散熱材料4 0 0之上 下表面上形成上凸部表面401c及下凸部表面402c。而該散 熱材料所形成之凸部厚度係可依據先前覆蓋於該散熱材料 上之光阻層厚度加以選擇。有關電鍍技術繁多，惟乃業界 -所周知之製程技術，故未再予贅述。 - 請參閱第4 D圖，最後移除覆蓋於該上外緣表面4 0 3 a及 該下外緣表面4 0 4 a上之光阻層4 1 0及光阻層4 2 0，即完成用 於内嵌至半導體封裝基板之散熱片4 0，俾使該散熱片4 0電 鍍完成有上凸部40 1及下凸部402，且該上凸部表面401c及 下^部表面4 0、2 c位置係高於該散熱片4 0中先前為該光阻層1 所覆蓋部分之外緣表面4 0 3 a及下外緣表面4 0 4 a，俾於嵌入 基板於後續封裝製程時，以供至少一半導體晶片接置於該 凸部表面。 根據以上之說明，本發明之半導體封裝基板之散熱片 製作方法，係以電鍵方式在該散熱材料表面上形成有至少 一凸部，因此相較習知技藝中藉由蝕刻方法去除散熱材料 之外緣部分以形成一具相對凸部之散熱件，將可節省較多 散熱材料與成本。而且，透過適當形狀與厚度之光阻層覆 蓋至該散熱材料表面，將可較佳地控制該凸部之形狀與厚 0，使得所製作出之散熱片具有較佳之形狀與良好之平整 性，藉以避免習知利用蝕刻製程時，造成材料浪費與平整 性不佳等問題。 r 之後，可將該電鍍完成有凸部之散熱片内嵌於一半導 體封裝基板中，係藉由在該散熱片未形成有凸部之表面形200423347 V. Description of the invention (9) ... A lower convex portion 4 2 is formed along the opening 4 2 b, so that the upper and lower surfaces of the heat dissipating material 4 0 0 form an upper convex surface 401 c and a lower convex surface 402 c. The thickness of the convex portion formed by the heat dissipation material can be selected according to the thickness of the photoresist layer previously covered on the heat dissipation material. There are many electroplating technologies, but they are well-known process technologies in the industry, so I will not repeat them. -Please refer to Figure 4D. Finally, remove the photoresist layer 4 1 0 and photoresist layer 4 2 0 covering the upper outer edge surface 4 0 3 a and the lower outer edge surface 4 0 4 a. The heat sink 40 embedded in the semiconductor package substrate is plated with an upper protrusion 401 and a lower protrusion 402, and the upper protrusion surface 401c and the lower surface 40, The position 2 c is higher than the outer edge surface 4 0 3 a and the lower outer edge surface 4 0 4 a of the heat sink 40 previously covered by the photoresist layer 1. When the substrate is embedded in the subsequent packaging process, For at least one semiconductor wafer to be placed on the surface of the convex portion. According to the above description, the manufacturing method of the heat sink of the semiconductor package substrate of the present invention is to form at least one convex portion on the surface of the heat dissipation material by means of an electric key. Therefore, compared with the conventional art, the heat dissipation material is removed by etching The edge part forms a heat dissipating member with a relatively convex portion, which can save more heat dissipating materials and costs. In addition, by covering the surface of the heat-dissipating material with a photoresist layer of an appropriate shape and thickness, the shape and thickness of the convex portion can be better controlled, so that the produced heat sink has better shape and good flatness. In order to avoid problems such as waste of materials and poor flatness when the conventional etching process is used. After r, the plated heat sink with convex parts can be embedded in half of the semiconductor package substrate by forming the surface shape of the heat sink without convex parts.
17172 全懋.ptd 第16頁 200423347 五、發明說明（ίο) 基凸 裝之 封片 體熱 導散 半該 一於 成置 形接 以以 ，得 層片 路晶 電體 一 導 少半 至一 與少 層至 緣供 絕提 一可 少俾 至， 成板 第 示。 所界 圖外 2 至 t導 (^傳 上量 部熱 之 生 產 片 晶 將 咅 凸 之 片 熱 散 亥 古口 透 以 在熱 可散 係該 中於 法式 方方 作鍍 製電 片用 熱利 散上 之料 板材 基熱 裝 散 封好 體良 導等 半屬 之金 ΠΙ3 Ltr 發或 本屬 金 之成 料形 材獨 熱單 散可 該亦 Λ; β— 妒立口 雖凸 中該 式上 圖際 前實 先而 β» β— 立口 咅 凸凸 1 1 少有 至成 有形 成皆 形面 上表 料下 材上 或1接 亦供 ，以 片， 晶部 體凸‘ 導之 半數 一 多 有有 置.成 安形 供鍍 以電 ，上 上面 面表 表一 1 之-料料 材材 熱熱 散散 該該 於於 明明 發發 本本 為。 僅圍 容範 内術 之技 示之 揭明 所發 上本 以限 惟侷 ，於 片用 晶非 體並 導， 半例 之施 數實 多佳 有較 置之 5 圍 中範 圍利 範專 利請 專申 請列 申下 之與 下若 以法 於方 義或 定體 地實 義術 廣技 係之 容成 内完 術所 技人 質他 實何 之任 發 本 於 蓋 涵 為 視 得 均 改 修 或 更 變 之。 同内 等之 為轉 僅範 或及 同神 相精 全之 完明17172 Quan 懋 .ptd Page 16 200423347 V. Description of the invention (ίο) The heat dissipation of the sealing body of the convex package is connected to the shape, and the conductivity of the layered crystal body is less than half to one. A few layers to the edge of the confession must be mentioned, which can be reduced to the first. Outside the boundary of the figure 2 to t guide (^ pass on the amount of heat produced by the production of crystals will spread the convex piece of heat radiated through the mouth, in order to dissipate the heat in the French method for plated electric sheet for heat dissipation The base material of the material is hot-packed and bulk-sealed. The semi-generous gold ΠΙ3 Ltr hair or the raw material shape of the metal is singularly hot and scattered. Β— Although the jealous stand is convex in the formula, Before the picture is shown, β »β— standing mouth convex convex 1 1 seldom or even formed on the surface of the material on the surface of the material or 1 connection is also available, with a piece, the crystal body convex 'half of the lead There is more than one. There is a form for electroplating. It is listed in Table 1 of Table 1 above. The materials and materials should be dissipated in the Ming Mingfa. Only the technique of enclosing the internal medicine is shown. Declared that the last issue is limited, and the crystal is not used in the film. The half number is better than the 5th range. The patent should be applied for. What is the hostage skill of Fangyi or fixed-field practice of wide-field technique? Han is made present in the cover are changed, as was the change or repair., Etc. within the same range as the only or transfected with the spirit and phase of all fine Ming End
17172全懋.ptd . 第17頁 200423347 圖式簡單說明 一 ·【圖示簡單說明】 第1圖係習知技藝之半導體基板剖面示意圖，其中顯 示以導熱栓作為散熱結構之半導體封裝基板； 第2圖係習知技藝之半導體封裝基板剖面示意圖，其 -中顯示具有高散熱結構散熱片之半導體封裝基板； - 第3A圖至第3D圖係習知技藝之半導體封裝基板高散熱 結構散熱片製作方法流程步驟之剖面示意圖；以及 第4A圖至第4D圖係本發明之半導體封裝基板之散熱片 製作方法流程步驟之剖面示意圖。 1 半導體封裝基板 10 散熱片 100 上表面 101 下表面 11 上樹脂層 110 導通孔 12 下樹脂層 13 上電路層 131 打線墊 14 下電路層 141 鲜球塾 15 導電栓 16 導熱栓 160 晶片 16 1 金線 162 封膠 17 脅 拒鋅層 18 拒鲜層 鲜球 2 半導體封裝基板 20 散熱片 200 上表面 201 下表面 202 上凸部 203 中心部 204 下凸告P 21 上樹脂層 210 導通孔17172 全懋 .ptd. Page 17 200423347 Schematic illustration one. [Simplified illustration] Figure 1 is a cross-sectional view of a conventional semiconductor substrate, which shows a semiconductor package substrate using a thermal conductive plug as a heat dissipation structure; Figure is a schematic cross-sectional view of a semiconductor package substrate of a conventional technology, in which a semiconductor package substrate with a high heat dissipation structure heat sink is shown;-Figures 3A to 3D are manufacturing methods of a semiconductor package substrate high heat dissipation structure heat sink of a conventional technology 4A to 4D are schematic cross-sectional views of the process steps of a method for manufacturing a heat sink of a semiconductor package substrate according to the present invention. 1 semiconductor package substrate 10 heat sink 100 upper surface 101 lower surface 11 upper resin layer 110 via hole 12 lower resin layer 13 upper circuit layer 131 wire bonding pad 14 lower circuit layer 141 fresh ball 塾 15 conductive pin 16 thermal pin 160 chip 16 1 gold Line 162 Sealant 17 Zinc-repellent layer 18 Fresh-repellent layer fresh ball 2 Semiconductor package substrate 20 Heat sink 200 Upper surface 201 Lower surface 202 Upper convex portion 203 Center portion 204 Lower convex P 21 Upper resin layer 210 Via hole
17172 全懋.ptd. 第18頁 i 200423347 圖式簡單說明 22 下 樹 脂 層 23 上 電 路 層 231 打 線 墊 24 下 電 路 層 241 銲 球 墊 25 導 電 栓 260 晶 片 261 金 線 262 封 膠 27 拒 鲜 層 28 拒 銲 層 29 銲 球 30 散 孰 片 300 散 数 材 料 301 上 凸 部 301a 上 表 面 301b 上 凸 部 表 面 302 下 凸 部 3 0 2 a 下 表 面 3 0 2b 下 凸 部 表 面 3 0 3a 上 外 緣 表 面 3 0 3 b 新 的 上 外 緣 表 面 3 0 4a 下 外 緣 表 面 3 0 4b 新 的 下 外 緣 表 面 305 去 除 部 310 光 阻 層 320 光 阻 層 40 散 熱 片 400 散 熱 材 料 401 上 凸 部 4 0 1a 上 表 面 401b 開 σ 4 0 1c 上 凸 部 表 面 402 下 凸 部 4 0 2a 下 表 面 4 0 2b 開 V 4 0 2 c 下 凸 部 表 面 4 0 3 a 上 外 緣 表 面 4 0 4a 下 外 緣 表 面 410 光 阻 層 4 2 0 光阻層17172 Full 懋 .ptd. Page 18 i 200423347 Brief description of the diagram 22 Lower resin layer 23 Upper circuit layer 231 Wire bonding pad 24 Lower circuit layer 241 Solder ball pad 25 Conductive plug 260 Chip 261 Gold wire 262 Sealant 27 Anti-frying layer 28 Solder resist layer 29 Solder ball 30 Scatter sheet 300 Scatter material 301 Upper convex part 301a Upper surface 301b Upper convex part surface 302 Lower convex part 3 0 2 a Lower surface 3 0 2b Lower convex part surface 3 0 3a Upper outer edge surface 3 0 3 b new upper outer edge surface 3 0 4a lower outer edge surface 3 0 4b new lower outer edge surface 305 removal portion 310 photoresist layer 320 photoresist layer 40 heat sink 400 heat dissipating material 401 upper convex portion 4 0 1a Upper surface 401b open σ 4 0 1c Upper convex surface 402 Lower convex portion 4 0 2a Lower surface 4 0 2b Open V 4 0 2 c Lower convex surface 4 0 3 a Upper outer edge surface 4 0 4a Lower outer edge surface 410 Photoresist layer 4 2 0 Photoresist layer
17172 全懋.ptd. 第19頁17172 懋 .ptd. P.19
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| US9153521B2 (en) | 2011-05-03 | 2015-10-06 | Subtron Technology Co., Ltd. | Method of manufacturing a package carrier |
| TWI763319B (en) * | 2021-02-22 | 2022-05-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9153521B2 (en) | 2011-05-03 | 2015-10-06 | Subtron Technology Co., Ltd. | Method of manufacturing a package carrier |
| TWI763319B (en) * | 2021-02-22 | 2022-05-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
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