1220273 五、發明說明（l) 曼明所屬之拮術 本發明是有關於一種半導體製程，且 種源極/汲極區的製造方法。 寺別疋有關於一 先前拮術 金屬氧化半導體（Metal 〇xide Semi⑶以此忧㈠電曰 量少且適合高積集度製作等優點，近； 已逐：：代傳統之雙載子電晶體。一個金屬氧 晶體間早地說，其係由基底、位與 _ 、 [氧=:r、位輸兩側之基广 此外金屬氣匕極區與沒極區之間的通道區所構成。、 泛，舉凡邏輯電路或是記情俨开杜初=可了况疋相當地廣 破，全屬氧化丰寡ί ϊ 或是材料應用的突 然而，隨著元件積集度逐漸提高，金 晶體的尺寸勢必要隨之縮小，❿ 體電 縮小’會使得源極區與没極區之 此外，金屬氧化半^體^^)問題發生。 源極/沒極的阻值升高。倘日日尺寸的縮小，還會使得 度（Junction Depth)來解決電阻值日之極=極=接面深 面，倘若為了解決因接面===問題。另-方 而利用高濃度之摻雜來製作擊穿漏電的問題， f久接面的源極/汲極區，則又 12168twf.ptd 第7頁 i 1220273 五、發明說明（2) 會因固態溶解度的限制而無法解決阻值升高之問題。因 ^，如何解決因提高元件積集度所衍生出來之問題是目 各界所關心的課題。 ⑺ 内容 區鑑於此，本發明的目的就是在提供一種源極/汲極 品的製造方法，以降低源極/汲極區的電阻值。 本發明的再-㈣是提供一種源極“及極區的 :題？避免相鄰的源極區以及沒極區之間產生擊穿漏電等 本發明提出一種源極/ &極區的製造方法， 先於基底上形成圖案化之第一鉍袓 击係 源極/汲極區之處的基底_面，I4//以暴露出預定形成 〜处旧悉履表面，其中此第一 餅 例如是對於基底具有蝕刻選擇性 s、貝 氣相沈積製程，以於基底與第一材化學 崎擇性的材質= = = = = = =具有 植入步驟，以於基底中形成深摻雜區 J離子 =驟然= ; = = :人罩幕，進行第：離 區與深摻雜區係共同作為一源極;:摻極雜區區。，其中此嶋 由於本發明之源極/汲極區 淺，因此可以避免相鄰的㈣^\\雜£接面可以作 漏電的問題，it而提升元件可靠及f極“間產生擊穿 仵了罪度。另外’本發明之源極 12168twf.ptd 第8頁 1220273 五、發明說明（3) / >及極區的深摻雜區接面 ^，、 體電阻值可以降低。 卞’木’以使源極/汲極區之整 為讓本發明之卜；+、 顯易懂，下文特兴=口，、他目的、特徵、和優點能更明 細說明如下1^圭實施例’並配合所附圖式，作詳 實施方i 本發明之源極/没極製 或記憶體元件等丰導髀_ I μ制 去可應用於邏輯電路 ^ yr m 半導體疋件的衣程當中，唯本發明之麻用 並不限於下述所揭露之内容。 ，尽^月之應用 你1沾f 1Α圖至第1 Ε圖所示，其繪示依照本發明-較佳杏施 種源極/汲極區之製造流程剖面示意圖。 只 是石夕照第1八圖，提供基底ι〇0，此基底1〇。例如 後碎聰 於基底10〇上形成墊氧化層101，以避免 法：如：：損f基底100表面，其中塾氧化層101的形成方 =Γ 。之後，於基底100上全面性地形成材 彻+曰3 /以覆盍墊氧化層101。其中，材料層102的材質 • σ疋2於基底1 〇 〇具有蝕刻選擇性的材質，其例如是氮 =石夕、氮化矽、氮氧化矽或是多晶矽等材料，而材料層 的形成方法例如是進行化學氣相沈積製程。 接著，請繼續參照第1Α圖，於材料層102上形成圖案 化f光阻層104。其中，圖案化之光阻層1〇4的形成方法例 如疋於材料層丨0 2上全面性地形成光阻材料層（未繪示）， 再進行微影製程，而形成之。 曰 之後，請參照第1 B圖，以光阻層1 04為蝕刻罩幕，進1220273 V. Description of the invention (l) Manmin's technology The present invention relates to a semiconductor process and a method for manufacturing a source / drain region. Terabetsu has related to a previous metal oxide semiconductor (Metal Oxide SemiCD), which has the advantages of small amount of electricity and suitable for high-integration production, etc., and has recently been replaced by :: generation of traditional double-carrier transistors. A metal-oxygen crystal said earlier that it was composed of a base, a bit and _, [oxygen =: r, a broad base on both sides of the bit-transport, and a channel region between a metal gas pole region and an infinite region. In general, the logic circuit or the memory is open. The situation is quite extensive, all of which are oxidative abundance, or the sudden application of materials. As the component accumulation gradually increases, the gold crystal ’s The size must be reduced accordingly. The reduction of the bulk electricity will cause the source region and the non-electrode region. In addition, the problem of metal oxide half body ^^) occurs. Source / impedance resistance increases. If the day-to-day size is reduced, it will also make the junction (Depth of Depth) to solve the problem of resistance value = pole = deep surface of the junction, if it is to solve the problem of junction ===. On the other hand, the use of high concentration of doping to create the problem of breakdown leakage, the source / drain region of the f junction, and then 12168twf.ptd page 7 i 1220273 V. Description of the invention (2) The limitation of solubility cannot solve the problem of increased resistance. Because of this, how to solve the problems arising from increasing the degree of component accumulation is a topic of concern to all circles.鉴于 Content area In view of this, the purpose of the present invention is to provide a method for manufacturing a source / drain product to reduce the resistance value of the source / drain region. The present invention provides a source electrode and a polar region: a question? To avoid the occurrence of breakdown leakage between adjacent source regions and non-polar regions, etc. The present invention proposes a source / amp region manufacturing Method: Before forming a patterned first bismuth striker source / drain region on the substrate, a substrate surface is formed, and I4 // is used to expose a predetermined surface to be formed, where the first cake is, for example, It is an etching selective process for the substrate, and a vapor deposition process, so that the substrate and the first material are chemically selective. = = = = = = = = Has an implantation step to form a deep doped region J in the substrate. Ion = Suddenly =; = =: Human mask, proceed: the off-region and the deeply doped region together as a source; the doped-hetero region. Wherein, this is due to the shallow source / drain region of the present invention. Therefore, it is possible to avoid the problem that the adjacent junctions can be used for leakage, it improves the reliability of the component and the breakdown between the f poles is caused. In addition, the source of the present invention 12168twf.ptd page 8 1220273 V. Description of the invention (3) / > and the deep doped region junction of the electrode region ^, the bulk resistance value can be reduced.卞 'Wood' makes the integration of the source / drain region as a guide to the present invention; +, it is easy to understand, the following special ==, and other purposes, characteristics, and advantages can be explained in more detail as follows: Examples' and the detailed description of the implementation of the formula i The source / non-polar or memory elements of the present invention _ _ I μ system can be applied to logic circuits ^ yr m semiconductor parts clothing process Among them, the hemp use of the present invention is not limited to the contents disclosed below. As shown in Figure 1 through Figure 1 through Figure 1E, they show cross-sectional schematic diagrams of the manufacturing process of the source / drain region according to the preferred embodiment of the present invention. It is only that Shi Xizhao according to Fig. 18 provides a base ι0 and a base 10. For example, Hou Satoshi forms a pad oxide layer 101 on the substrate 100 to avoid methods such as: damaging the surface of the f substrate 100, where the formation of the hafnium oxide layer 101 = Γ. After that, a material is completely formed on the substrate 100 to cover the pad oxide layer 101. Among them, the material of the material layer 102 σ 蚀刻 2 has a material with an etching selectivity on the substrate 100, which is, for example, nitrogen = shixi, silicon nitride, silicon oxynitride, or polycrystalline silicon, and a method for forming the material layer For example, a chemical vapor deposition process is performed. Next, please continue to refer to FIG. 1A to form a patterned f photoresist layer 104 on the material layer 102. Among them, the method for forming the patterned photoresist layer 104 is, for example, forming a photoresist material layer (not shown) on the material layer and forming a photolithography process. After that, please refer to FIG. 1B, and use the photoresist layer 104 as an etching mask.
1220273 五、發明說明（4) 定形成$5/、及以極形「成®案化之材料層102a，並且暴露出預 刻製=是：乾之=氧， 餻 钇式蝕刻製程或疋濕式蝕刻製程。 進行：；氣⑽，在移除光阻侧之後， 的表面形点丘以於墊氧化層101與材料層l〇2a 的材質‘如:、fi於：料層1 〇8。值得一提的是，材料層1 08 於材料展1 η 〇 ; 土底1 〇 〇具有蝕刻選擇性的材質，且對 的材質i視：：二有蝕刻選擇性的材質’因此材料層108 鼠夕、氧化石夕、說氧化石夕或是多晶石夕等算兴 的材ί可！Ϊ:層，的材質係為氮切，則材料層10: 二材負可以選擇軋化矽或多晶矽。或者是，若 今材質係為多晶矽，則材料層j〇8 搵、曰a 或氧化矽。此外，所進杆之外與々/負j以選擇虱化矽 ^ ¥ a ^ t iKAPCVD) .¾ ，)’以使所沈積之材料層m具有較佳之沈、::勻 然後’請參照第1C圖’以材料層1〇8為植 ::子植入步驟110，以於基底10。中形成深摻：’進 值件一提的是，於此步驟所形成之深摻雜 ？、12。 以作深，以降低後續所形成之整個源^的深度可 值。 口你往/及極區的電阻 接著，參照第1D圖，移除材料層1〇8。並 料層1 08的方法例如是進行濕式#刻製 /由^移除材 ® W材料層1 0 81220273 V. Description of the invention (4) It is determined to form a material layer 102a of $ 5 /, and polarized, and expose a pre-etched = Yes: dry = oxygen, yttrium-yttrium etching process or wet-type The etching process is carried out :; gas, after the photoresist side is removed, the surface of the surface is shaped as a material of the pad oxide layer 101 and the material layer 102a, such as: fi, material layer 108. It is worth It is mentioned that the material layer 1 08 is at the material exhibition 1 η 〇; the soil bottom 100 has a material with an etching selectivity, and the material i is regarded as :: two materials with an etch selectivity, therefore, the material layer 108 , Oxidized stone, oxidized stone, or polycrystalline stone, and so on! Ϊ: layer, the material is nitrogen cut, then the material layer 10: two materials can choose rolled silicon or polycrystalline silicon. Or, if the material is polycrystalline silicon today, the material layer j08 搵, said a or silicon oxide. In addition, the outside of the rod and 之外 / negative j to select lice silicon ^ ¥ a ^ t iKAPCVD). ¾ ,) 'In order to make the deposited material layer m have a better sedimentation, and then:' Please refer to FIG. 1C 'with the material layer 108 as the implantation: sub-implantation step 110, A deep dopant is formed in the substrate 10. "The value-added part mentions that the deep dopant formed in this step ?, 12. It is used for deepening to reduce the depth of the entire source formed later." Your resistance to the pole area Then, referring to Figure 1D, remove the material layer 108. The method of combining the layers 108 is, for example, wet # etching / removing the material from the W material layer 1 0 8
1220273 五、發明說明（5)1220273 V. Description of the invention (5)
Hi為分別對於基底100及材料層i〇2a具有蝕刻選擇 性T才貝，因此可以在不損傷基底100及材料層102a的情 況下’將材料層108去除。 月 :後’繼續參照第〇圖’以材料層102a為植入罩幕， 二:：二的離子植入步驟114，以於深摻雜區ιΐ2兩側形 區116。其中所形成之淺摻 =2其摻質濃度可以是相同，但也可以是不上 之、、罙二^况之需求而定。而所形成之淺摻雜區116與上述 ::,相12係共同作為源極"及極區U8之用 一 ί Ξ二此f驟所形成之淺摻雜區112，其深度可以作 “二避免相鄰的源極區以及没極區之間發生擊穿漏電的 例如：J行圖，移除材料層l〇2a，其移除方法 完成罝ί:ί1 然後，移除塾氧化層101，以 的製作。 &116以及深摻雜區112之源極/汲極區118 同之：二區的製作完成之後，則可依照不 的製作，行後續的製程，“完成各種元件 ^ ^ °己丨$體凡件或是邏輯電路等等。 之後，將接；：m體來說，在源極/汲極區製作完成 於基底之上方开成絕緣結構與閘氧化層。之後， 極區亦可以是埋入$ ^、、-。其中，上述所形成之源極/汲 j从疋埋入式位元線。 此外，以氮化物唯讀記憶體（_)來說，當源極/及Hi has an etching selectivity T for the substrate 100 and the material layer 102, respectively. Therefore, the material layer 108 can be removed without damaging the substrate 100 and the material layer 102a. Month: Afterwards, 'continue to refer to FIG. 0', the material layer 102a is used as the implant mask, and the second: two ion implantation step 114 is used to form the region 116 on both sides of the deeply doped region ι2. The shallow dopant = 2 formed therein may have the same dopant concentration, but it may also be inferior to the above requirements. The shallowly doped region 116 formed as described above is used as the source electrode 12 and the phase 12 and the electrode region U8 is used. The depth of the shallowly doped region 112 formed in this step can be “ Second, to avoid breakdown leakage between adjacent source regions and non-electrode regions, for example: J-line diagram, remove the material layer 102a, and the removal method is completed. Then, remove the oxide layer 101. &Amp; 116 and the source / drain region 118 of the deeply doped region 112 are the same: After the production of the second region is completed, the subsequent processes can be performed according to the different production, "Complete various elements ^ ^ ° self 丨 $ body or logic circuit, etc. After that, the connection of the: m body is completed in the source / drain region, and an insulating structure and a gate oxide layer are formed on the substrate. After that, the polar regions can also be embedded in $ ^ ,,-. Wherein, the source / drain j formed above is a buried bit line. In addition, in the case of nitride read-only memory (_), when the source / and
•Ptd 第11頁 1220273 五、發明說明（6) 極區製作穿+ 形成氧化石夕/氮化石"將接著於源極/汲極區之間的基底上 等。 乳化矽/氧化矽（〇肋）堆疊層與控制閘極等上 另卜以快閃（F 1 a s h )記惊體來今，♦上 作完成之後，將桩I §源極/汲極區製 隨氧化層、浮=於源極/汲極區之間的基底上形成穿 成之：，：：二以邏輯電路來說，當源極/汲極區製作-烕之後將接者於源極/汲極區之間的美 衣作元 層與閘極等等。 土 &上形成閘氧化 綜上所述，本發明至少具有以下之優點： 祖f ^1 免相鄰的源極區以及彡及極區之間產4敏^ 漏電的問題，進而接斗 生 土 擊穿 /汲極區的深摻雜區接面可以 二源極 體電阻值可以降低。 以使源極/汲極區之整 十而^ Γ用本發明的方法可以有效解決因縮小元件尺 ^ 目鄰的源極區以及汲極區產生擊穿漏電盥短通 魂宽的制"本可以應用於現今之微小 線冕的衣耘上，進而提高元件的積集度。 几铷3- Ϊ然在上述實施例中係提出罩幕式唯讀記憶體、氮 物唯項,己憶體、十夬閃記憶體以及邏輯電路等應用實例， 但本發明之源極/汲極區的應用並不限於此。亦即在其他 適合的半導體it件的製程中亦可採用第u圖至第u圖之製 程步驟來完成中這些半導體元件中之源極/汲極區的製 12168twf.ptd 第12頁 1220273 五、發明說明（7) 作。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。• Ptd Page 11 1220273 V. Description of the invention (6) Fabrication of the polar region + formation of oxide stone / nitride " will be continued on the substrate between the source / drain region and so on. Emulsified silicon / silicon oxide (0 ribs) stacked layers and control gates, etc. The flash body (F 1 ash) is used to remember the future, after the completion of the above, the post I § source / drain region system With the oxide layer, the floating layer is formed on the substrate between the source / drain region :, 2 :: For logic circuits, when the source / drain region is made-接, it will be connected to the source The beautiful clothes between the drain / drain region are used as the element layer and the gate and so on. As mentioned above, the present invention has at least the following advantages: The ancestor f ^ 1 is free from the problem of leakage current generated between adjacent source regions and between 彡 and the pole region, and the problem is further overcome. The junction of the deeply doped region in the soil breakdown / drain region can reduce the resistance of the two source bodies. In order to make the whole source / drain region ten ^ Γ, the method of the present invention can effectively solve the problem of the breakdown of leakage current caused by the reduced source size and the source region and the drain region of the drain region. It can be applied to the clothing of today's tiny wire crowns, thereby improving the accumulation degree of components. Ji 铷 3 铷 In the above embodiments, application examples such as a veil-type read-only memory, a nitrogen-only item, a memory, a ten flash memory, and a logic circuit are proposed, but the source / sink of the present invention The application of the polar region is not limited to this. That is, in the process of other suitable semiconductor it parts, the process steps from u to u can be used to complete the source / drain region of these semiconductor elements. 12168twf.ptd Page 12 1220273 V. Invention Description (7) Works. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.
12168twf.ptd 第13頁 1220273 圖式簡單說明 第1 A圖至第1 E圖是依照本發明之一較佳實施例的一種 源極/汲極區之製造流程剖面示意圖。 【圖式標記說明】 100 :基底 1 0 1 :墊氧化層 102、102a、108 :材料層 I 0 4 :光阻層 II 0、11 4 :離子植入步驟 11 2 :深摻雜區 11 6 :淺摻雜區 118 :源極/汲極區 1 2 0 :絕緣結構 1 2 2 :閘氧化層 1 2 4 :字元線12168twf.ptd Page 13 1220273 Brief Description of Drawings Figures 1A to 1E are schematic cross-sectional views of a manufacturing process of a source / drain region according to a preferred embodiment of the present invention. [Illustration of diagrammatic symbols] 100: substrate 1 0 1: pad oxide layers 102, 102a, 108: material layer I 0 4: photoresist layer II 0, 11 4: ion implantation step 11 2: deeply doped region 11 6 : Shallow doped region 118: source / drain region 1 2 0: insulating structure 1 2 2: gate oxide layer 1 2 4: word line
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