TW594936B - Apparatus and method for inhibiting dummy cell over erase - Google Patents

Abstract

A semiconductor device that includes a semiconductor substrate including a memory cell region and a dummy cell region, a plurality of substantially parallel bit lines in the semiconductor substrate, a plurality of memory cell gate dielectrics provided over the bit lines in the memory cell region, the memory cell gate dielectrics comprising an oxide-nitride-oxide (ONO) layer, a plurality of dummy cell gate dielectrics provided over the bit lines in the dummy cell region, a material of the dummy cell gate dielectrics comprising a non-trapping material, and a plurality of substantially parallel word lines over the memory cell gate dielectrics and the dummy cell gate dielectrics.

Description

594936 V. Description of the invention α) The present invention relates to the US patent application No. 10/2 1 4, 7 7 with the application titled "Memory Element and Operation" on August 9, 2002. This related application is expressly incorporated herein by reference. TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for suppressing over-erase of dummy cells (d u m m y c e 1 1) in a memory device. Prior art A memory element may traditionally include a transistor that is used as a memory cell to connect a word line to a bit line. A traditional nitride read only memory cell (NROM) includes a substrate having a non-polar region, a source region spaced apart from it, and a channel between the two. Area. The nitride read-only memory cell also includes an oxide-nitride-oxide (ONO) structure formed on the channel region and part of the source and non-electrode regions. The 0N0 structure includes a first oxide layer formed on the substrate, a nitride layer formed on the first oxide layer, and a second oxide layer formed on the nitride layer. The nitride read-only memory cell further includes a gate structure formed on the second oxide layer, and a sidewall spacer (s i d e w a 1 1 spacer) formed at least adjacent to the gate structure. The nitride layer “stores” charges by trapping electrons therein, and the thickness of the first and second oxide layers needs to be thick enough to avoid leakage (1 eakage), such as the direct storage of electrons under normal operating conditions. Wear it. The compound memory cell (m u 1 ΐ i p 1 e m e m ◦ r y c e 1 1) contains nitride only

9649t.wf. Pt.d Page 6 594936 V. Description of the invention (2) Reading memory cells can form a memory array, which usually includes memory cells connected to grid-shaped word lines and bit lines. During the formation of the memory element, the memory lines (word lines and bit lines) located at the edge of the element are always specially and completely etched out, so that the memory cells connected to it can no longer be used. In order to protect the memory cells in use from being damaged, the memory element may include a dummy character line (that is, a character line not used for stylization) at an edge. The dummy character line will not be connected to the character line driver, so each memory cell connected to the dummy character line will not be used to store data. This is a dummy cell. Therefore, the etching of the dummy word lines during the formation will not cause the loss of the memory cells in use. Usually, the dummy word lines at the edges are continuously grounded (c 0 p 1 e t 0 g r o u n d). Therefore, regardless of the voltage supplied to the opposite bit line (whether it is a stylized or erased voltage), the dummy cell is in a fixed state that is weakly erased, which leads to a dummy in some cases. Excessive erasure of cells. In addition, during the read operation of the memory cell (readoperati ο η), the state of the dummy cell will cause a bit line to bit line leakage current (bit 1 inet 〇 bit 1 ine current leakage) in the memory cell and the dummy cell. o SUMMARY OF THE INVENTION Accordingly, the present invention provides a semiconductor device including a semiconductor substrate including a memory cell region and a dummy cell region, a plurality of bit lines located substantially parallel to the semiconductor substrate, and bits located in the memory cell region. Several memory cell dielectrics on the line, wherein the memory cell dielectric includes an oxide-nitride-oxide layer (0 N 0), and a plurality of dummy cell gates on bit lines in the dummy cell region. Dielectric, the material of the dummy cell dielectric includes a non

9649t.wf.ptd Page 7 594936 V. Description of the invention (3) Capture material (η〇η-trappingmateria 1) and several character lines located substantially parallel to the memory cell dielectric and the dummy cell gate dielectric . The invention also provides a method for manufacturing a semiconductor device, which includes providing a semiconductor substrate, and then providing a memory cell region and a dummy cell region in the semiconductor substrate. After that, several bit lines are formed in the semiconductor substrate, and an oxide-nitride-oxide layer is provided on the bit lines in the memory cell region. Next, a non-capturing material layer is provided on the bit line in the dummy cell area, where the non-capturing material layer includes an oxide, and then the oxide-nitride-oxide layer and the non-capacitive material layer in the memory cell area and the dummy cell area. A plurality of characters and lines are provided on the capture material layer. . The invention further provides a method for manufacturing a semiconductor device, including providing a semiconductor substrate, providing a memory cell region and a dummy cell region in the semiconductor substrate, and forming at least one memory cell in the memory cell region. The steps include: A first source region and a first drain region are provided in the substrate, and an oxide-nitride-oxide layer is provided on the first source and drain regions, and then the oxide-nitrogen is patterned and etched. A compound-oxide layer to form at least one gate dielectric, and then providing a first gate electrode on the gate dielectric. After that, at least one dummy cell is formed in the dummy cell region. The steps include providing a second source region and a second drain region in the semiconductor substrate, and then providing a non-capturing region on the second source and drain region. Material layer, where the material of the non-capturing material layer includes silicon dioxide or aluminum oxide, and then patterning and etching the non-capturing material layer to form at least one dummy cell dielectric, and then providing a second Gate. In order to make the above and other objects, features, and advantages of the present invention clearer

9649t.wf. Pt.d Page 8 594936 V. Description of the invention (4) It is easy to understand. The preferred embodiment will be described in detail below with reference to the accompanying drawings. In addition, the features and advantages of the present invention are specifically defined in the appended patent application scope. In addition, the foregoing description of the present invention and the following preferred embodiments are provided by way of example and are not intended to limit the present invention. Embodiments In one embodiment of the present invention, a multi-layer oxide-nitride-oxide (oxide-nitride-oxide) structure in a dummy cell 1 1 region is One layer is used instead to reduce or prevent electric charge (e 1 ectriccharge) from being trapped therein, so it can reduce and prevent the over-erasing of dummy cells in the conventional 0 N 0 layer and other disadvantages. The material of the non-trapping material layer can include any material that does not trap electric charges, such as oxides, stone dioxide, or aluminum oxide. To facilitate the description, an oxide layer is used as the non-capturing material layer. The thickness of this oxide layer in the memory device is the same as that of the conventional 0 N 0 layer, and it is generally flat. In addition, the width of the bit line below the character line should be reduced and transformed into a dummy cell channel length that is longer than the channel length of the memory cell, in order to reduce or eliminate the problem of excessive erasure of dummy cells. The method for forming a memory element of the present invention is to form a plurality of bit lines or diffusion regions (diffusi ο nregi ο η) in a semiconductor substrate as a source / drain region of a transistor of a memory cell and a dummy cell. . Thereafter, a multilayer oxide-nitride-oxide is provided on the substrate between the bit lines of each memory cell in the memory cell region. Then, an oxide layer is formed on the substrate between the bit lines of each dummy cell in the dummy cell area. Oxygen in individual areas

9649 t.wf. pt.d Page 9 594936 V. Description of the invention (5) Deposit gate or bit line on the compound-nitride-oxide or oxide layer. After that, it will continue the traditional semiconductor process to complete the formation of memory cells, dummy cells, and final memory elements. FIG. 1 is a schematic top view of a memory array (mem o r y a r r a y) of a nitride read only memory device (NROM) according to a preferred embodiment of the present invention. The memory array 100 includes a semiconductor substrate (not shown), which has a memory cell region 104 formed with a plurality of memory cells (not shown) therein and one of a plurality of dummy cells (not shown) formed therein. The dummy cell area is 1.06. The dummy cell region 106 can be formed on one or both sides of the memory cell region 104. In the base are formed a plurality of bit-line pairs 108 and 110 which are substantially parallel, and each bit-line pair 108 and 110 represents the source and drain of a cell or transistor. Polar region. The bit lines 108 and 1 10 of each pair define a memory cell and a dummy cell of a section (c ο 1 u m η). Those skilled in the art should understand that the bit lines 108 and 110 named "source" and "drain" regions are not important purposes of the present invention. Referring to FIG. 1, a plurality of first word lines 1 1 2 are formed on the base and bit lines 1 0 8 and 1 1 0 in the memory cell area 104, and each first word is substantially parallel. The element lines 1 1 2 are approximately perpendicular to the bit lines 108 and 110. In addition, substantially parallel second word lines 1 1 4 are formed on the base and the bit lines 1 0 8 and 1 1 0 in the dummy cell area 106, which are perpendicular to the bit line 1 0 8 And 11 0. The first word line 1 1 2 and the second word line 1 1 4 function as the gates of the transistors of the memory cell and the dummy cell, respectively. In operation, during the programming cycle of the memory element, one of the selected bit line pairs 108 and 1 10 is biased to make the pair

9649twf. Pt.d Page 10 594936 V. Description of the invention (6) One bit line 1 0 8 is biased at 5 ~ 8 · 2 V, and the other bit line 1 1 0 is biased Ο V. One of the first word lines 1 1 2 in the memory cell area 104 is also selected to be biased at 11.5V, and the second word line 1 1 4 in the dummy cell area 106 is grounded. The substrate is always grounded. Under such a bias condition, data will be written into a memory cell, which is selected by the selected bit line and word line. When the memory element is to be erased, one of the bit line pairs, such as bit line 108, will be biased to 7.5 V, while the other bit line is floating. The first word line 1 1 2 is connected to a high voltage of 11.5 V, and the second word line 1 1 4 is grounded. The substrate is still grounded in this case. The method for manufacturing the memory device includes forming a plurality of substantially parallel bit lines (source / drain regions) in a semiconductor substrate, wherein the substrate includes a memory cell region and a dummy cell region. The method of the present invention continues by masking the entire substrate except for the memory cell area. Then, a plurality of 0 N 0 layers are provided on the memory cell area by any conventional method. After that, the 0 N 0 layer is patterned and etched by a conventional method to form a plurality of gate dielectrics between the bit lines. Then, a photoresist is provided on the entire substrate, and only the dummy cell region is exposed. Then, an oxide layer is provided on the dummy cell region, and the oxide layer is patterned and etched to form a plurality of dummy cell dielectrics between the source / dead region. Gates or bit lines are then deposited on 0 N 0 or oxide layers in individual areas. It then continues the traditional semiconductor manufacturing process to complete the formation of memory cells, dummy cells, and final memory elements. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit of the present invention.

9649twf.pt.d Page 11 594936

9649t.wf. Pt.d Page 12 594936

9649 t.wf. ptd Page 13

Claims (1)

594936 VI. Scope of patent application 1. A semiconductor device comprising: a semiconductor substrate including a memory cell region and a dummy cell region; a plurality of bit lines that are substantially parallel and located in the semiconductor substrate; a plurality of memory cell gates The electric substance is located on the bit lines in the memory cell region. The memory cell dielectrics include an oxide-nitride-oxide (0 N 0) layer; a plurality of dummy cell dielectrics. The bit lines in the dummy cell area, the material of the dummy cell dielectrics includes a non-capturing material; and a plurality of character lines that are substantially parallel and located between the memory cell dielectrics and the These dummy cell gate dielectrics. 2. The semiconductor device according to item 1 of the patent application scope, wherein the non-capturing material comprises silicon oxide. 3. The semiconductor device according to item 1 of the patent application scope, wherein the non-capturing material comprises alumina. 4. The semiconductor device according to item 1 of the scope of the patent application, wherein the thicknesses of the dummy cell dielectrics and the memory cell dielectrics are the same. 5. The semiconductor device according to item 1 of the scope of patent application, wherein a width of the bit lines on the character lines in the dummy cell area is smaller than that of the character lines in the memory cell area. A width of the bit lines. 6. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; providing a memory cell region and a dummy cell region in the semiconductor substrate; 9649t.wf. Pt.d Page 14 594936 6. Application for a patent forms a plurality of bit lines in the semiconductor substrate; an oxide-nitride-oxide is provided on the bit lines in the memory cell region A layer; providing a non-capturing material layer on the bit lines in the dummy cell region, wherein the non-capturing material layer includes an oxide; and the oxide-nitride in the memory cell region and the dummy cell region -Providing a plurality of character lines on the oxide layer and the non-capturing material layer. 7. The method according to item 6 of the scope of patent application, wherein the thickness of the non-capturing material layer provided in the dummy cell area is the same as that of the oxide-nitride-oxide layer provided in the memory cell area. 8. The method according to item 6 of the scope of patent application, further comprising patterning and engraving the oxide-nitride-oxide layer to form a plurality of gate dielectrics. 9. The method according to item 6 of the scope of patent application, further comprising patterning and etching the non-capturing material layer to form a plurality of dummy cell dielectrics. 10. The method according to item 6 of the scope of patent application, wherein a width of the bit lines on the character lines in the dummy cell area is smaller than the character lines on the memory cell area. A width of the bit lines. 1 1. The method according to item 6 of the patent application, wherein providing the oxide-nitride-oxide layer on the bit lines in the memory cell region further includes shielding the dummy cell region. 12. The method according to item 6 of the scope of patent application, wherein providing the non-capturing texture layer on the bit lines in the dummy cell area further includes shielding the memory cell area. 9649twf.ptd Page 15 594936 VI. Application for Patent Scope 1 3. A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; providing a memory cell region and a dummy cell region in the semiconductor substrate; and in the memory cell Forming at least one memory cell in the region includes providing a first source region and a first > and a pole region in the semiconductor substrate, and providing an oxide-nitride- on the first source and drain region. An oxide layer; patterning and engraving the oxide-nitride-oxide layer to form at least one gate dielectric; and providing a first gate electrode on the at least one gate dielectric; and in the dummy Forming at least one dummy cell in the cell region, including providing a second source region and a second > and polar region in the semiconductor substrate, and providing a non-capturing material layer on the second source and drain region, The material of the non-capturing material layer includes silicon dioxide or aluminum oxide; patterning and etching the non-capturing material layer to form at least one dummy cell dielectric; and providing a second on the non-capturing material layer Gate. 14. The method according to item 13 of the scope of patent application, wherein a distance between the first source region and the first drain region is defined as a first channel length, and the second source region A distance from the second drain region is defined as a second channel length. 15. The method according to item 14 of the scope of patent application, wherein the second 9649t.wf. Pt.d Page 16 594936 6. Scope of patent application The channel length is longer than the first channel length. 16 · The method as described in item 13 of the patent application, wherein the first source and drain regions are substantially parallel. 17 · The method as described in item 13 of the scope of patent application, wherein the first gate and the second gate are substantially parallel. 18. The method as described in item 13 of the scope of the patent application, wherein the at least one memory cell is a nitride read-only memory cell. 9649twf.ptd Page 17