TW593787B - Electrochemical mechanical processing with advancible sweeper - Google Patents
Electrochemical mechanical processing with advancible sweeper Download PDFInfo
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- TW593787B TW593787B TW091132514A TW91132514A TW593787B TW 593787 B TW593787 B TW 593787B TW 091132514 A TW091132514 A TW 091132514A TW 91132514 A TW91132514 A TW 91132514A TW 593787 B TW593787 B TW 593787B
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 30
- 229910052802 copper Inorganic materials 0.000 description 30
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B21/00—Machines or devices using grinding or polishing belts; Accessories therefor
- B24B21/04—Machines or devices using grinding or polishing belts; Accessories therefor for grinding plane surfaces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/22—Electroplating combined with mechanical treatment during the deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
Abstract
Description
(發明說明應敘明:發明所屬之技術嶺域、先前技術、内容、實施方式及圈式簡單說明) L· W i^ff Λ j 發明領域 本發明大致是有關於一種半導體積體電路技術,並且 特別是有關於一種用以電處理或電化學處理一工作件的裝 置。 C先前技術3 發明背景 如積體電路(ic)之習知半導體裝置通常包括一通常是 10石夕基材之半導體基材,及多數由絕緣材料層分開之導電材 料層,導電材料層,或相互連接部,形成該積體電路之配 線網路。在配線網路中之各層導體係藉由一般習知之中間 層介電質之該等絕緣層而與相鄰層之導體隔絕。一通常在 矽積體電路中使用之介電材料是二氧化矽,但目前已有將 15在IC結構中之至少某些標準緻密二氧化矽以例如有機、無 機、自旋與CVD選擇物等之低k介電材料來取代的趨勢。 以往,1C連接部係藉由將一如銅之導體以一金屬化製程填 入多數被蝕刻入該介電中間層之構件或凹孔中來形成。由 於銅的低阻抗與良好之電遷移性質而使它成為用於相互連 20接應用上的較佳導體,銅金屬化製程之較佳方法是電鍍, 在-積體電路中,在連續層中形成之相互連接部可以使用 如通孔或接點之構件來電連接。在一典型相互連接部製程 中,首先-絕緣層形成在該半導體基材上,接著進行圖案 化與Μ製程以在該絕緣層中形成如溝槽、塾與通孔等構 件。然後,電鍍銅以填滿所有的構件,在這些電鍍製程中 ,該晶圓係被放在一晶圓載架上且一相對一電極之陰極㈠ 電壓係施加於該晶圓表面,且該電解液濕潤該晶圓表面與 該電極兩者。 5 一旦電鍵結束後,所進行的是一如化學機械拋光 (CMP)步驟之材料移除步驟,以由該工作件之頂面(亦稱為 場區域)去除亦被稱為銅覆蓋層之多餘銅層,並且僅留下銅 於該等構件中。接著可進行另一材料移除步驟以移除如在 該場區域上之障壁/膠層的其他導電層,依此方式製造可產 10 生沈積在該等構件内且互相實體地且電氣地絕緣之銅沈積 物。其他習知之蝕刻方法也可以使用,另亦有可以在一步 驟中由該場區域利除銅與障壁/膠層兩者之方法。一種可有 效地發揮作用之特殊CMP裝置係揭露於名稱為“具有可填 裝殼體之反直線拋光器”之美國專利第6,103,628號中。 15 習知材料移除方法之不良效果可以藉由使用一可以在 該工作件之表面上提供多層薄平面導電材料之平面沈積方 法,以及一平面移除方法來減少或消除。這些平面沈積與 移除方法亦可應用在使用於1C封裝之通孔-抗蝕製程中, 在這些應用中,電鍍層係形成在抗蝕層中之開孔内且在暴 20 露於各孔或開孔之底部上的晶種膜上。 有一種被通稱為電化學機械處理(ECMPR)之方法包括 電化學機械沈積(ECMD)法與亦被稱為電化學機械拋光之電 化學機械蝕刻(ECME)兩者。在此應注意的是通常ECMD 與ECME兩者被稱為電化學機械處理(ECMPR),因為兩者(Explanation of the invention should state: brief description of the technical range, prior art, content, implementation, and circle of the invention) L · W i ^ ff Λ j FIELD OF THE INVENTION The present invention relates generally to a semiconductor integrated circuit technology. And in particular, it relates to a device for electrically or electrochemically treating a work piece. C Prior Art 3 BACKGROUND OF THE INVENTION Conventional semiconductor devices such as integrated circuits (ICs) typically include a semiconductor substrate, typically a 10-square-silicon substrate, and a layer of conductive material, a layer of conductive material, mostly separated by an insulating layer, or The interconnecting portions form a wiring network of the integrated circuit. Each layer of the conductor system in the wiring network is isolated from the conductors of adjacent layers by the insulating layers of the commonly known intermediate layer dielectric. A dielectric material commonly used in silicon integrated circuits is silicon dioxide, but at least some standard dense silicon dioxide has been used in IC structures such as organic, inorganic, spin, and CVD options. The trend is to replace low-k dielectric materials. In the past, a 1C connection was formed by filling a conductor like copper with a metallization process into most members or recesses etched into the dielectric intermediate layer. Because of its low impedance and good electromigration properties, copper is a better conductor for interconnect applications. The preferred method for copper metallization is electroplating. In integrated circuits, in continuous layers The formed interconnecting portions can be electrically connected using components such as through holes or contacts. In a typical interconnection process, an insulating layer is first formed on the semiconductor substrate, and then a patterning and M process is performed to form components such as trenches, trenches, and vias in the insulating layer. Then, copper is electroplated to fill all the components. In these electroplating processes, the wafer is placed on a wafer carrier and a cathode 相对 voltage is applied to the surface of the wafer, and the electrolyte is applied to the wafer. Wet both the wafer surface and the electrode. 5 Once the bond is completed, a material removal step is performed like a chemical mechanical polishing (CMP) step to remove the excess, also called the copper cover, from the top surface of the work piece (also known as the field area). Copper layer, and only copper is left in these components. Then another material removal step can be performed to remove other conductive layers such as barriers / adhesive layers on the field area. In this way, it can be produced to deposit within these components and be physically and electrically insulated from each other. Copper deposits. Other conventional etching methods can also be used, and there are also methods that can remove both copper and barrier / adhesive layer from the field area in one step. A special CMP device that functions effectively is disclosed in U.S. Patent No. 6,103,628 entitled "Inverse Linear Polisher with Refillable Housing". 15 The disadvantages of the conventional material removal method can be reduced or eliminated by using a planar deposition method that can provide multiple layers of thin planar conductive materials on the surface of the work piece, and a planar removal method. These planar deposition and removal methods can also be applied to the through-resist process used in 1C packages. In these applications, the plating layer is formed in the openings in the resist layer and exposed in the holes at 20 ° C. Or on the seed film on the bottom of the opening. One method commonly known as electrochemical mechanical processing (ECMPR) includes both electrochemical mechanical deposition (ECMD) and electrochemical mechanical etching (ECME), also known as electrochemical mechanical polishing. It should be noted here that both ECMD and ECME are commonly referred to as electrochemical mechanical processing (ECMPR) because both
均涉及電化學製程與機械作用 在ECMPR製程中,當該工作件表面與如一墊、一掩 模或一清除器之工作件表面作用裝置(WSID)之間有實體接 觸或緊臨與相對移動時,至少在該等電處理製程之一部份 進仃時’可以使㈣WSID。在由本發明之受讓人所共同 擁有之以下專利及中請案中可以㈣各種平面沈積與平面 飯刻之方法與裝置的說明,即,。 不論是使用一 CMP製程、 一蝕刻製程或一電蝕刻製程 ’減少必須利用這些製程去除之銅覆蓋層厚度均是必要的 。克服該銅覆蓋層問題之重要性可由㈣在該等晶圓表面 上沈積平面且薄之銅層的技術發展得以證實,這些平面沈 積技術通常被稱為,在這些平面化製程中,名稱為“用以 電化學機械沈積之方法與裝置,,之美國專利第6,176,992號 :在2004 12月8日提出中請且名稱為“使用一外部作 用而在沈積於頂面上之添加物與—工作件之表面間產生一 差別之電鑛方法與裝置,,之美國申請案第請74〇,7〇1號; 及在9月2G日提出中請且名稱為“用以控制在—工作件之 預定部份上之沈積之電鍵方法與裝置,,之美时請案第 〇娜U93號。這些方法可將金屬以—平面之方式沈積在 -工作件之凹孔中或凹孔上之新穎結構,它們亦具有,如 有必要的話’不論該等構件之尺寸為何均可於其上產生過 量金屬的能力。 ECMD方法中,該工作件之表面係被—電解液濕潤 且相對—純該電解液μ之電極具㈣姉,這通常會Both involve electrochemical processes and mechanical actions. In the ECMPR process, when the surface of the work piece and the work piece surface-acting device (WSID) such as a pad, a mask, or a remover have physical contact or are close to and relatively moved WSID can be used at least when part of the electrical processing process is performed. A description of various methods and apparatuses for planar deposition and planar rice carving can be found in the following patents and applications commonly owned by the assignee of the present invention, namely ,. Whether using a CMP process, an etch process, or an electro-etch process, it is necessary to reduce the thickness of the copper cover layer that must be removed using these processes. The importance of overcoming the problem of copper overlays can be confirmed by the technological development of ㈣ deposition of flat and thin copper layers on the wafer surfaces. These planar deposition techniques are commonly referred to as, in these planarization processes, the name is " Method and device for electrochemical mechanical deposition, US Patent No. 6,176,992: filed on December 8, 2004 and named "Additives deposited on the top surface using an external action and— An electric smelting method and device that produces a difference between the surfaces of work pieces, US Application No. 74〇, 7〇1; and a request filed on September 2G and named "for controlling the work piece" The key method and device for depositing on the predetermined part, and the beautiful time please file No. Una U93. These methods can be used to deposit metal in a planar manner in the recess of the work piece or a novel structure on the recess. They also have the ability, if necessary, to generate excess metal on these components, regardless of the size of the components. In the ECMD method, the surface of the work piece is wetted with electrolyte and relatively pure electrolyte μ of The electrode has a stunt, which usually
593787 產生在該工作件之構件内的導電材料沈積物,及一在該工 作件之頂面上之薄層。在ECMD時,當在該工作件之表面 與該WSID之間產生該工作件之表面之清除時,該晶圓表 面被推抵或靠該WSID之表面或反之亦然。如上述專利申 5 請案中所述,平面沈積會由於清除作用而達成。 在ECME方法中,該工作件之表面係被該電解液或蝕 刻液濕潤,但所施加的是反向電壓,因此使該工作件之表 面相較該電極更具陽極性。如果未施加電壓差,該餘刻是 化學蝕刻且可以在該工作件與該WSID之間有實體接觸或 10 緊密相臨時進行。該化學蝕刻可以使用處理溶液或蝕刻溶 液來進行。 非常薄之平面沈積物可以藉由先使用一 ECMD法並且 接著使用一 ECME法在相同之電解液中之平面膜上藉由使 所施加之電壓反向來沈積一平面層,或者該ECME步驟可 15 以在另一機器與一不同蝕刻溶液中進行,該沈積物之厚度 可以一平面之方式減少。事實上,一 ECME法可以繼續直 到在場區域上之所有金屬被移除為止。在此應注意的是在 該電蝕刻或蝕刻製程時可使用或不使用WSID,因為大致 平面之蝕刻可以利用或不利用WSID來達成。 20 第1A圖是用以處理晶圓之習知ECMPR系統100之示 意圖,在第1A圖中,一其中具有多數孔104之WSID102 係設置在靠近一欲處理之工作件或晶圓106之附近。該晶 圓106是一欲電鍍一以銅或銅合金為佳之導電材料的矽晶 圓,該晶圓106係被一晶圓載架111保持以將該晶圓之前 9 593787593787 Generates a deposit of conductive material within the component of the work piece and a thin layer on the top surface of the work piece. At ECMD, when the removal of the surface of the work piece occurs between the surface of the work piece and the WSID, the wafer surface is pushed against or against the surface of the WSID or vice versa. As described in the aforementioned patent application 5, planar deposition is achieved due to the removal effect. In the ECME method, the surface of the work piece is wetted by the electrolyte or etching solution, but a reverse voltage is applied, so that the surface of the work piece is more anodic than the electrode. If no voltage difference is applied, the remainder is chemically etched and can be carried out with physical contact or close contact between the work piece and the WSID. This chemical etching can be performed using a processing solution or an etching solution. Very thin planar deposits can be deposited by first using an ECMD method and then using an ECME method on a planar film in the same electrolyte by reversing the applied voltage, or the ECME step can be 15 By performing in another machine with a different etching solution, the thickness of the deposit can be reduced in a planar manner. In fact, an ECME method can continue until all metals in the field area are removed. It should be noted here that the WSID can be used or not used in the electro-etching or etching process, because the etching of a substantially flat surface can be achieved with or without the WSID. Fig. 1A is a schematic diagram of a conventional ECMPR system 100 for processing wafers. In Fig. 1A, a WSID 102 having a plurality of holes 104 therein is disposed near a work piece or wafer 106 to be processed. The wafer 106 is a silicon wafer to be electroplated with a conductive material, preferably copper or a copper alloy. The wafer 106 is held by a wafer carrier 111 to hold the wafer 9 593787.
5 方表面112定位靠抵該WSID102之頂面113。該等孔104 係設計成可確實由一以箭號114表示之電解液將銅均勻地 沈積在該前方表面112上,或者由該前方表面112上均勻 地電蝕刻。該等穿孔110可以精確地或不精確地配合該等 孔104之結構,通常,該等孔104係設計成供均勻沈積用 ,且穿孔110係可使電場與電解液大致不受阻礙地通至該 WSID102。因此,每單位面積之支持板108之穿孔面積等 於或大於每單位面積之WSID102之孔的面積,面對該晶圓 之前方表面112之該WSID102之頂面113係被用來當作清 10 除器且該WSID102本身建立流至該前方表面112的適當電 解液流與電場流以達成全體均勻沈積或蝕刻之目的。這種 ECMPR系統100亦包括一浸於電解液114中之電極116, 該電解液114係經由在該WSID 102中之孔1〇4而與該電極 116及該晶圓106之前方表面112流體性地連通。 15 該電極116通常是一供銅沈積用之銅塊,它也可以是 一由,例如塗有Ti之Pt的惰性電極製成。一銅電解液可 為一硫酸銅溶液,其具有如促進劑、抑制劑、整平劑、氣 之添加劑及一般在工業中使用者。在如ECMD之平面沈積 法中,該整平劑不是必要的,整平可由該製程自動完成。 2〇 但是仍可整平劑,以使其他如間隙填充等處理結果最佳化 。該WSID102之頂面113掃過該晶圓之前方表面112且在 該電極116與該晶圓之前方表面112之間產生一電位差, 為了沈積一如銅之平面膜,該晶圓106係作成較成為陽極 之該電極116更具有陰極性(負)。為了在相同之ECMPR系 10The square surface 112 is positioned against the top surface 113 of the WSID 102. The holes 104 are designed so that copper can be evenly deposited on the front surface 112 by an electrolyte indicated by an arrow 114, or can be uniformly electrically etched from the front surface 112. The perforations 110 can be precisely or imprecisely matched to the structure of the holes 104. Generally, the holes 104 are designed for uniform deposition, and the perforations 110 allow the electric field and the electrolyte to pass substantially unhindered. The WSID102. Therefore, the perforated area of the support plate 108 per unit area is equal to or greater than the area of the WSID 102 hole per unit area. The top surface 113 of the WSID 102 facing the front surface 112 of the wafer is used as a clear 10 And the WSID 102 itself establishes an appropriate electrolyte flow and electric field flow to the front surface 112 to achieve the purpose of uniform deposition or etching throughout. The ECMPR system 100 also includes an electrode 116 immersed in an electrolyte 114, and the electrolyte 114 is fluid with the electrode 116 and the front surface 112 of the wafer 106 through a hole 104 in the WSID 102. Ground Connected. 15 The electrode 116 is usually a copper block for copper deposition. It may also be made of an inert electrode such as Pt coated with Ti. A copper electrolyte may be a copper sulfate solution, which has additives such as accelerators, inhibitors, leveling agents, gas, and general users in the industry. In a planar deposition method such as ECMD, the leveling agent is not necessary, and the leveling can be automatically performed by the process. 2〇 But leveling agent can still be used to optimize other processing results such as gap filling. The top surface 113 of the WSID 102 is swept across the front surface 112 of the wafer and a potential difference is generated between the electrode 116 and the front surface 112 of the wafer. In order to deposit a planar film such as copper, the wafer 106 is made relatively The electrode 116 that becomes the anode is more cathodic (negative). To be in the same ECMPR system 10
593787 統中電蝕刻,該晶圓表面係作成比該電極更具陽極性,為 了進行化學蝕刻,化學蝕刻或蝕刻,在該晶圓與該電極之 間施加一電位差。 如第1B圖所示,該WSID102之結構可具有一頂層 5 120、一中間層122及一底層124。該頂層120宜由一如一 種由3M公司提供之固定研磨膜的研磨性材料,或者如由 Rodel公司所提供之IC-1000材料之使用於CMP應用中之 其他所謂墊材料來製成。該頂層120之厚度通常是在0.05-2mm之範圍内,該中間層122是該頂層120之安裝層,該 10 中間層122通常是由一厚度範圍為l-3mm之如聚碳酸酯之 硬質塑膠材料製成,該底層124係作為整個結構的一施壓 層,該底層係由一如聚胺基甲酸酯或聚丙烯之聚合發泡材 料製成。讓渡給本發明之受讓人的美國專利第6,413,403與 6,413,388號揭露各種WSID之例子,而在2001年9月20 15 日申請且名稱為“掩模板結構”之美國申請案第 09/960,236號則揭露各種WSID之實施例。此外,在2002 年5月23日申請且名稱為“低力電化學機械沈積方法與裝 置”之美國申請案第10/155,828號則揭露一具有一連接在 一可高度壓縮層上之撓性與研磨頂層的WSID結構,且這 20 兩件申請案均讓渡給本發明之受讓人。該WSID係被放置 在一可以是或不是該WSID整體之一部份的多孔性支持板 上,在這特殊結構中,電解液係流經該可壓縮層之多數孔 或穿孔及在該撓性層中之孔。 但是,為達此目的,雖然這些方法有助於在工作件與 11 593787593787 In the electrical system, the surface of the wafer is made more anodic than the electrode. In order to perform chemical etching, chemical etching or etching, a potential difference is applied between the wafer and the electrode. As shown in FIG. 1B, the structure of the WSID 102 may have a top layer 5 120, a middle layer 122, and a bottom layer 124. The top layer 120 is preferably made of an abrasive material such as a fixed abrasive film provided by 3M Company, or other so-called pad materials used in CMP applications such as the IC-1000 material provided by Rodel Company. The thickness of the top layer 120 is usually in the range of 0.05-2mm, the intermediate layer 122 is the mounting layer of the top layer 120, and the 10 intermediate layer 122 is usually made of a hard plastic such as polycarbonate with a thickness ranging from 1 to 3mm. The bottom layer 124 is used as a pressure layer for the entire structure. The bottom layer 124 is made of a polymer foam material such as polyurethane or polypropylene. Examples of various WSIDs are disclosed in U.S. Patent Nos. 6,413,403 and 6,413,388 assigned to the assignee of the present invention, and U.S. Application No. 09 / 960,236, filed on September 20, 2001 and entitled "Mask Structure" Embodiments of various WSIDs are disclosed. In addition, US Application No. 10 / 155,828, filed on May 23, 2002 and entitled "Low-Electrochemical Mechanical Deposition Method and Apparatus," discloses a flexible and highly flexible layer connected to a highly compressible layer. The top-level WSID structure is ground, and both of these 20 applications are assigned to the assignee of the present invention. The WSID is placed on a porous support plate which may or may not be an integral part of the WSID. In this particular structure, the electrolyte system flows through most of the holes or perforations of the compressible layer and is flexible. Holes in layers. However, to this end, although these methods help in the work piece and 11 593787
晶圓上獲得平面金屬沈積物或新穎金屬結構,但仍需要有 可以產生具有更佳之均勻性與高產率之高產量方法與裝置 明内容】 5 概要 因此,本發明提供藉由使用處理溶液來電化機械處理 -工作件之表面的裝置,本發明之裝置包括—接觸該處理 溶液之電極,一延伸在一供應捲軸與一接收捲軸之間的帶 式工作件表面作用裝置。此外,該工作件表面作用裝置之 10處理區段係設置在靠近該工作件之表面附近,該處理溶液 流經該處理區段且流至該工作件表面上。在處理時,一電 壓差可保持在該電極與該工作件表面之間。當該溶液流經 該工作件表面作用裝置時,一機構使該工作件表面作用裝 置之處理區段移動β 15 此外,本發明提供一種電化學機械處理一工作件表面 之方法,該方法包括提供一具有通道圖案之工作件表面作 用裝置’該工作件表面作用裝置延伸在且連接於一供應捲 軸與_接收捲軸之間。該工作件係放置於靠近於該工作件 表面作用裝置之第-處理區段處,一處理溶液流經該工作 20件表面作用裝置之第一處理區段之通道且流至該工作件表 面上。當在該X作件表面作用裝置之第—處理區段與該工 作件表面之間於該化學機械處理時產生相對移動時該表 面被化學機械處理。在處理時,在該電極與該工作件之間 保持一電位差。 12A planar metal deposit or a novel metal structure is obtained on the wafer, but there is still a need for a method and apparatus that can produce a high yield with better uniformity and high yield. 5 SUMMARY Therefore, the present invention provides a method for electrification by using a processing solution. Mechanical treatment-a device for the surface of a work piece, the device of the invention comprises an electrode contacting the treatment solution, a belt-type work piece surface acting device extending between a supply reel and a receiving reel. In addition, the 10 processing section of the work piece surface acting device is disposed near the surface of the work piece, and the processing solution flows through the processing section and onto the surface of the work piece. During processing, a voltage difference can be maintained between the electrode and the surface of the work piece. When the solution flows through the work piece surface acting device, a mechanism moves the processing section of the work piece surface acting device β 15 In addition, the present invention provides a method for electrochemical mechanically treating a work piece surface, the method comprising providing A work piece surface acting device having a channel pattern. The work piece surface acting device extends between and is connected between a supply reel and a receiving reel. The work piece is placed near the first processing section of the work piece surface acting device, and a processing solution flows through the channel of the first processing section of the work piece surface acting device and flows onto the surface of the work piece. . When the relative movement between the first processing section of the X-workpiece surface acting device and the work piece surface occurs during the chemical mechanical treatment, the surface is chemically mechanically treated. During processing, a potential difference is maintained between the electrode and the work piece. 12
593787 本發明之一目的是提供一種帶式wsid結構,其有助 於提供具有較佳均勻性之金屬層。 本發明之另一目的是提供一種帶式wsid結構,其具 有多數成組地位於該帶式WSID之多數區段中的孔或通道 5 ° 本發明係在一電化學機械處理裝置中使用一帶式 WSID來單一地或組合地達成本發明之這些與其他目的。 圖式簡單說明 第1A圖是一習知ECMPR系統之示意圖; 10 第1B圖是一工作件表面作用裝置之示意圖; 第2A圖是一具有多數構件形成於其中之基材表面之 表面區域的示意圖; 第2B圖是顯示在第2A圖中之基材的示意圖,其中銅 已被沈積在該基材表面上;593787 An object of the present invention is to provide a belt-type wsid structure, which helps to provide a metal layer with better uniformity. Another object of the present invention is to provide a belt-type wsid structure having a plurality of holes or channels located in groups in most sections of the belt-type WSID 5 ° The present invention is to use a belt-type in an electrochemical mechanical processing device WSID serves these and other purposes of the invention singly or in combination. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of a conventional ECMPR system; 10 FIG. 1B is a schematic diagram of a surface-acting device of a work piece; FIG. 2A is a schematic diagram of a surface region having a substrate surface in which most components are formed Figure 2B is a schematic view of the substrate shown in Figure 2A, in which copper has been deposited on the surface of the substrate;
15 第3圖是一使用一帶式工作件表面作用裝置之ECMPR 系統之示意圖; 第4A圖是該帶式工作件表面作用裝置之處理區段之 示意圖; 第4B圖是另一帶式工作件表面作用裝置之處理區段 20 之示意圖; 第5圖是一具有多數有相同通道圖案之處理區段的工 作件表面作用裝置之示意圖,其中該等處理區段並未分開 第6圖是一具有多數有相同通道圖案之處理區段的工 1315 Figure 3 is a schematic diagram of an ECMPR system using a surface acting device of a belt work piece; Figure 4A is a schematic diagram of a processing section of the surface acting device of the belt work piece; Figure 4B is a surface acting device of another belt work piece Schematic diagram of the processing section 20 of the device; Figure 5 is a schematic diagram of a surface-acting device with a majority of processing sections with the same channel pattern, where the processing sections are not separated. Figure 6 is a diagram with a majority of 13 of the processing section of the same channel pattern
作件表面作用裝置之示意圖,其中該等處理區段是分開的 593787 第7圖是一具有多數有不同通道圖案之處理區段的工 作件表面作用裝置之示意圖; 第8圖是在第3圖所示之ECMPR系統中之電接點位 置的示意圖; 第9圖疋本發明之工作件表面作用裝置之調整裝置的 示意圖;Schematic diagram of the surface acting device of the workpiece, where the processing sections are separated 593787. Figure 7 is a schematic diagram of the surface acting device of the workpiece with most processing sections with different channel patterns; Figure 8 is in Figure 3. The schematic diagram of the electrical contact position in the ECMPR system shown in FIG. 9; FIG. 9 is the schematic diagram of the adjustment device of the surface-acting device of the work piece of the present invention;
第10A-12圖係該帶式工作件表面作用裝置之示意圖; 第13A-13C圖是另一帶式支持裝置之示意圖;及 第14A-14B圖是多數工作件表面作用裝置之示意圖。 t實施方式;J 詳細說明 以下將使用製造積體電路應用之相互連接部的例子來 15說明較佳實施例,但是,在此應了解的是本發明可以被用 來在具有如 Au、Ag、Ni、Pt、Pd、Fe、Sn、Cr、Pb、Zn 、Co及其相互間及與其他材料之合金的電鍍材料之工作件 上操作,以進行如封裝、平板顯示器、磁頭等許多不同應 用。在以下所述之例子中,被電鍍之該例舉材料係以銅來 2〇說明,但在此應了解的是也可以使用其他材料來替代。 此外,該較佳實施例將在沈積平面層之本文中說明, 如在上述ECMPR專利與申請案中之其他亦需要電姓刻、 化學蝕刻與其他處理之新穎結構亦可以使用本發明來獲得 。在一實施例中,例如,一平面導電層係使用本發明之一 14Figures 10A-12 are schematic diagrams of the surface acting device of the belt type work piece; Figures 13A-13C are schematic diagrams of another belt type supporting device; and Figures 14A-14B are schematic diagrams of the surface acting device of most work pieces. tEmbodiment; J Detailed description The following will use the example of manufacturing interconnected parts of integrated circuit applications to illustrate the preferred embodiment 15; however, it should be understood here that the present invention can be used in applications such as Au, Ag, Ni, Pt, Pd, Fe, Sn, Cr, Pb, Zn, Co, and other electroplating materials and alloys with other materials are operated on the work piece to perform many different applications such as packaging, flat panel displays, magnetic heads, and so on. In the example described below, the illustrated material to be plated is described with copper 20, but it should be understood here that other materials may be used instead. In addition, this preferred embodiment will be explained in the text of the deposition plane layer, as in the above ECMPR patents and applications, other novel structures that also require electrical engraving, chemical etching and other processing can also be obtained using the present invention. In one embodiment, for example, a planar conductive layer uses one of the present invention 14
593787 帶式WSID結構並藉由一 ECMD製程形成在一晶圓表面上 。其他結構也可以如在前述申請案中所述地使用低力電化 學機械蝕刻(ECME)來形成。 一以本發明來處理之基材200之表面區域之細部結構 5 係顯示於第2A-2B圖中,該基材200包含一較佳為一形成 在一工作件204上之絕緣層的圖案化層202,該絕緣層可 由一如氧化矽之絕緣材料構成且使用適用於金屬互連結構 規則之習知圖案化與蝕刻方法來形成。在這實施例中,該 絕緣層202可包含多數凹孔或間隙,即,被場區域210互 10 相分開之第一凹孔206與第二凹孔208,在這實施例中, 該等凹孔可以形成為使該第一凹孔206可為一通孔,該第 二凹孔208可以是一在底部包括一第二通孔209之溝槽。 頂面210亦被稱為場區域,一或多層具有例如Ta、TaN、 Ti、TiN或WN之材料的障壁或膠層217塗覆該等凹孔及 15 該等頂面。一銅之薄膜218係塗覆在隨後電鍍銅層之障壁 層頂面上成為晶種層,該銅晶種層提供一基底層,而該隨 後之沈積層的晶核形成與成長可在該基底層上進行。請參 閱第2B圖,一平面銅層220可以沈積在該等凹孔206、 208、209中且在該場區域210上。該沈積製程與使用本發 20 明實行之其他製程係說明如下。 第3圖顯示一包含本發明之一帶式WSID總成301與 一載架頭302之ECMPR系統300之實施例,該帶式WSID 總成301包含一具有一上表面304或一處理表面與一背面 306及一組滾輪308之WSID帶303。該WSID帶可由一撓 15593787 The tape WSID structure is formed on a wafer surface by an ECMD process. Other structures may also be formed using low-force electro-chemical mechanical etching (ECME) as described in the aforementioned application. A detailed structure 5 of the surface area of a substrate 200 treated in accordance with the present invention is shown in Figures 2A-2B. The substrate 200 includes a patterning of an insulating layer preferably formed on a work piece 204. Layer 202, which can be formed of an insulating material such as silicon oxide and formed using conventional patterning and etching methods suitable for metal interconnect structure rules. In this embodiment, the insulating layer 202 may include a plurality of recessed holes or gaps, that is, a first recessed hole 206 and a second recessed hole 208 that are separated from each other by the field region 210. In this embodiment, the recesses The hole may be formed so that the first recessed hole 206 may be a through hole, and the second recessed hole 208 may be a groove including a second through hole 209 at the bottom. The top surface 210 is also referred to as a field region, and one or more barriers or glue layers 217 having a material such as Ta, TaN, Ti, TiN, or WN coat the recesses and 15 the top surfaces. A copper thin film 218 is coated on the top surface of the barrier layer of the subsequent copper plating layer to become a seed layer. The copper seed layer provides a base layer, and the nucleation and growth of the subsequent deposited layer can be formed on the base. Performed on layers. Referring to FIG. 2B, a planar copper layer 220 may be deposited in the recessed holes 206, 208, 209 and on the field region 210. The deposition process and other processes implemented using the present invention are described below. FIG. 3 shows an embodiment of an ECMPR system 300 including a belt WSID assembly 301 and a carrier head 302 of the present invention. The belt WSID assembly 301 includes an upper surface 304 or a treated surface and a back surface. 306 and a set of rollers 308 have a WSID band 303. The WSID band can be flexed 15
593787 性材料製成且最好具有一研磨處理表面以進行清除動作, 該帶WSID可具有多數孔314或通道以便讓一如電鍍液或 電蝕刻溶液之以箭號316表示的處理溶液在一電極317與 一工作件320或一晶圓之前方表面318之間流動。為了達 5 到清楚的目的,保存該處理溶液之容器或凹孔未顯示於圖 中。該晶圓之前方表面318可包含在第2A-2B圖所示之基 材,如以下所述,該帶303之處理表面亦可包括突起表面 以進行清除動作(見第4B圖)。該帶式WSID303係藉由一 移動機構(圖未示)而以單向或雙向之方式在該等滚輪308 10 上移動,該帶式WSID可在電蝕刻或電沈積製程時移動而 靠近該晶圓之前方表面,該帶式WSID可以在該晶圓之前 方表面上移動以便在該電蝕刻或電鍍時清除該前方表面。 該移動機構亦適當地拉伸該帶式WSID303以在ECMPR時 確實接觸該工作件表面,該帶式WSID303之背面306係被 15 放在一板309之頂面307上,該板309可由一或多層構成 。在這實施例中,該板309係由一上層322與一下層324 所形成,該上層322可由一可壓縮材料製成,而該下層 322係一支持層且由一剛性材料製成,因此它可以以支持 該可壓縮層。在該可壓縮層中之多數孔310A與在該剛性 20 層中之多數孔310B可讓處理溶液流經該板309。此外,該 可壓縮層322可具有多數孔310或可由一可讓處理溶液流 經其開孔之多孔性材料所製成。該帶式WSID在該板之頂 面上是被拉伸的,因此該板309之頂面307與覆蓋該頂面 307之帶式WSID之底面部份完全接觸。如有必要,當該 16593787 is made of a non-ferrous material and preferably has an abrasive surface for cleaning. The tape WSID may have a plurality of holes 314 or channels to allow a treatment solution such as a plating solution or an electroetching solution indicated by arrow 316 at an electrode 317 flows between a work piece 320 or a wafer front surface 318. For the purpose of clarity, the containers or recesses holding the treatment solution are not shown in the figure. The front surface 318 of the wafer may include the substrate shown in Figs. 2A-2B. As described below, the processing surface of the tape 303 may also include a protruding surface for cleaning operations (see Fig. 4B). The belt WSID303 is moved on the rollers 308 10 in a one-way or two-way manner by a moving mechanism (not shown). The belt WSID can be moved close to the crystal during the electro-etching or electrodeposition process. Round the front surface, the tape WSID can be moved on the front surface of the wafer to remove the front surface during the electrical etching or plating. The moving mechanism also appropriately stretches the belt WSID303 to actually contact the surface of the work piece during ECMPR. The back surface 306 of the belt WSID303 is placed on the top surface 307 of a plate 309. Multi-layered composition. In this embodiment, the plate 309 is formed by an upper layer 322 and a lower layer 324. The upper layer 322 may be made of a compressible material, and the lower layer 322 is a support layer and made of a rigid material, so it This compressible layer can be supported. The majority of holes 310A in the compressible layer and the majority of holes 310B in the rigid 20 layer allow the treatment solution to flow through the plate 309. In addition, the compressible layer 322 may have a plurality of pores 310 or may be made of a porous material that allows the treatment solution to flow through its pores. The belt WSID is stretched on the top surface of the plate, so the top surface 307 of the plate 309 is completely in contact with the bottom surface portion of the belt WSID covering the top surface 307. If necessary, when the 16
593787 帶式WSID在該上層移動時,該帶式WSID之底面在該板 之上表面上滑動且該處理溶液316流經該板與該帶式 WSID303。 該帶式WSID可由一如通常使用在CMP製程中且可由 5 3M公司購得之固定研磨膜的聚合物膜製成,該帶式WSID 之撓性材料是薄的且具有〇.2-2mm之厚度範圍。該帶式 WSID亦具有一複合結構,該複合結構具有多數薄層。該 帶式WSID可具有相當平坦之表面,如含有0.05-0.5微米 尺寸之研磨顆粒(由例如,Buehler或3M公司所購得者)之 10 搭接膜,或具有平坦頂面之小徑柱或如使用在由3M公司 提供之固定研磨墊中的角錐形柱。該帶式WSID之表面最 好是有研磨性的以充份地清除該工作件之表面。 該板之上層是由一可輕易地在一施力情形下壓縮且一 旦解除該力就回復到其初始形狀的發泡或膠質材料製成, 15 該板之上層具有l-5mm之厚度範圍,這些材料之可舉例如 ,聚胺基曱酸酯、聚丙烯、橡膠、EVA、它們的混合物等 。該板之下層是一多孔性板或它具有多數孔以便讓電解液 與電場自由地流向該基材表面,該下層324可以本身就是 該電極。 20 在處理時,該晶圓320是被該載架頭固持而緊臨該帶 式WSID,使得流經該板309與該帶式WSID303之處理溶 液濕潤該晶圓之前方表面。如第4A圖之分解圖所示,該 晶圓320係在一預定區域321或該帶式WSID303之處理表 面之處理區域上進行處理,當該帶被拉緊在該板之頂面 17593787 When the belt WSID moves in the upper layer, the bottom surface of the belt WSID slides on the upper surface of the plate and the treatment solution 316 flows through the plate and the belt WSID303. The belt WSID may be made of a polymer film that is commonly used in a CMP process and a fixed abrasive film commercially available from 5 3M. The flexible material of the belt WSID is thin and has a thickness of 0.2-2 mm. Thickness range. The belt-type WSID also has a composite structure with most thin layers. The tape WSID can have a fairly flat surface, such as a 10-lap film containing abrasive particles of 0.05-0.5 micron size (purchased by, for example, Buehler or 3M), or a small diameter post with a flat top surface or Such as the use of pyramid cones in the fixed polishing pad provided by 3M company. The surface of the belt WSID is preferably abrasive to sufficiently remove the surface of the work piece. The upper layer of the board is made of a foam or gel material that can be easily compressed under a force and returns to its original shape once the force is released. 15 The upper layer of the board has a thickness range of 1-5mm, Examples of these materials include polyurethane, polypropylene, rubber, EVA, and mixtures thereof. The lower layer of the plate is a porous plate or it has a plurality of holes to allow the electrolyte and electric field to flow freely toward the surface of the substrate. The lower layer 324 may itself be the electrode. 20 During processing, the wafer 320 is held by the carrier head and next to the tape WSID, so that the processing solution flowing through the plate 309 and the tape WSID303 wets the front surface of the wafer. As shown in the exploded view of FIG. 4A, the wafer 320 is processed on a predetermined area 321 or a processing area of the processing surface of the tape WSID303. When the tape is tightened on the top surface of the board 17
593787 307上方時,該可壓縮層將該帶向上推。此外,如果該晶 圓320與該處理表面接觸,則該可壓縮層將該晶圓推抵住 該晶圓之前方表面。該處理區域321係藉由使該帶式 WSID前進而更新,因此一使用過的處理區域可藉由使該 5 使用過的處理區域捲繞在該儲存捲軸312上並且因此將該 新的處理區域由該供應捲軸311拉出而被一新的處理區域 取代,在處理大約20-100個晶圓之後或在密集使用相同之 WSID區域開始以一負面方式影響該製程結果之前,可使 該帶前進。由於這種特性,該帶式WSID303可減少製造時 10 間且增加系統之生產量。或者,可以一小的量來轉換 WSID之位置或使WSID逐漸前進,在處理時,該晶圓載 架304可使該晶圓在該帶式WSID303上或上方橫向地移動 且以該晶圓載架之轉動軸z為中心轉動。如上所墀,本發 明之帶式WSID亦可在該晶圓於其上被該載架頭移動時橫 15 向地移動。在另一實施例中,帶可以是一被多數取代儲存 與供應捲軸之滚輪所轉動之環形或連續帶,帶被捲繞在該 等滾輪上並且拉緊。在這實施例中,該等滚輪被一驅動系 統轉動且該等滾輪之轉動使該帶相對被處理之晶圓表面直 線地移動。 20 又,如第4A圖所示,該帶式WSID之寬度宜小於欲 處理之晶圓之直徑,如以下所述,該帶的這種特性可在該 晶圓之前方表面與一電源(圖未示)之間產生電氣接觸。對 於化學蝕刻製程而言,該WSID之寬度可等於或大於該晶 圓之直徑,因為不需要產生電氣接觸。該帶式WSID可以 18Above 593787 307, the compressible layer pushes the band up. In addition, if the wafer 320 is in contact with the processing surface, the compressible layer pushes the wafer against the front surface of the wafer. The processing area 321 is updated by advancing the tape WSID, so a used processing area can be wound by winding the 5 used processing area on the storage reel 312 and thus the new processing area Pulled out by the supply reel 311 and replaced by a new processing area, the belt can be advanced after processing approximately 20-100 wafers or before intensive use of the same WSID area begins to affect the process result in a negative way . Because of this feature, the belt WSID303 can reduce manufacturing time and increase system throughput. Alternatively, the position of the WSID can be changed in a small amount or the WSID can be gradually advanced. During processing, the wafer carrier 304 can move the wafer laterally on or above the tape WSID 303 and use the The rotation axis z rotates around the center. As described above, the tape WSID of the present invention can also be moved laterally in 15 directions when the wafer is moved by the carrier head thereon. In another embodiment, the belt may be an endless or continuous belt rotated by a plurality of rollers instead of storage and supply reels, and the belt is wound around and tensioned. In this embodiment, the rollers are rotated by a drive system and the rotation of the rollers causes the tape to move linearly relative to the surface of the wafer being processed. 20 Also, as shown in Figure 4A, the width of the tape WSID should be smaller than the diameter of the wafer to be processed. As described below, this characteristic of the tape can be (Not shown). For a chemical etching process, the width of the WSID may be equal to or greater than the diameter of the crystal circle, as no electrical contact is required. The tape WSID can be 18
593787 是單一層或一由一或多層構成之複合層結構,如果該帶包 括一或多層,這些層可以是或不是相同之大小。但是,這 種複合層之總厚度通常是〇.5-2mm。如第4B圖之立體圖所 示,一 WSID500可具有一比該WSID500之頂面504小之 5 突起表面502,在這實施例中,該清除動作係由該突起表 面502來執行,該突起表面502則以含有一研磨層為佳。 第3圖之ECMPR系統300可以進行平面或非平面電 鍍以及平面與非平面電蝕刻,依此方式,如果選擇的是非 平面處理方法,該晶圓之前方表面將會靠近該帶式 10 WSID303之處理表面,但並未碰觸它,因此可進行非平面 金屬沈積。此外,如果所選擇的是平面處理,則當在該帶 式WSID與該晶圓之前方表面之間產生一相對移動時,該 晶圓之前方表面接觸該處理表面。當該處理溶液被傳送通 過該帶中之孔時,該帶橫向移動或該晶圓轉動且橫向移動 15 ,或者當該前方表面接觸該處理表面時,該帶式WSID與 該晶圓兩者均移動。當在該晶圓與該電極之間施加一電壓 時,且在有上升通過該帶式WSID303之處理溶液存在的情 形下,如銅之金屬係依據在該晶圓表面與該電極間之電壓 的極性而被電鍍在該晶圓之前方表面上或由其上蝕刻移除 20 ° 第5至7圖顯示各種處理區域結構,依據本發明之原 理,該帶式WSID可具有可作成一沿該帶式WSID之連續 圖案或一或多種沿該帶式WSID重覆之圖案的多組孔或通 道圖案,如第5圖所示,在一實施例中,一帶式WSID330 19 593787593787 is a single layer or a composite layer structure composed of one or more layers. If the tape includes one or more layers, these layers may or may not be the same size. However, the total thickness of this composite layer is usually 0.5-2 mm. As shown in the perspective view of FIG. 4B, a WSID500 may have a 5 protruding surface 502 smaller than the top surface 504 of the WSID500. In this embodiment, the cleaning action is performed by the protruding surface 502, the protruding surface 502 It is better to include an abrasive layer. The ECMPR system 300 in FIG. 3 can perform planar or non-planar plating and planar and non-planar electro-etching. In this way, if a non-planar processing method is selected, the front surface of the wafer will be close to the processing of the tape 10 WSID303 Surface, but not touching it, allowing non-planar metal deposition. In addition, if planar processing is selected, when a relative movement occurs between the tape WSID and the front surface of the wafer, the front surface of the wafer contacts the processing surface. When the processing solution is transferred through a hole in the tape, the tape moves laterally or the wafer rotates and moves laterally 15 or when the front surface contacts the processing surface, both the tape WSID and the wafer are mobile. When a voltage is applied between the wafer and the electrode, and in the presence of a processing solution rising through the tape WSID303, the metal such as copper is based on the voltage between the wafer surface and the electrode. It is electroplated on the front surface of the wafer or removed by etching 20 °. Figures 5 to 7 show the structure of various processing areas. According to the principle of the present invention, the tape WSID can be formed along the tape. The continuous pattern of the type WSID or one or more patterns of multiple sets of holes or channels along the pattern repeated on the strip WSID, as shown in Figure 5. In one embodiment, a strip WSID 330 19 593787
可具有一以沿著該帶式WSID330延伸之連續圖案形成的通 道332。在這特殊結構中,通道332係成形為多數平行的 槽孔,但是它們也可以成形為孔或具有各種不同幾何形狀 或各種徑向結構之孔。在這實施例中,依據處理之要求與 5 該晶圓之尺寸,多數處理區域334可以端至端方式延伸。 該帶式WSID330可以在該板上橫向地移動以進行機械清除 動作,在一些晶圓於相同之處理區域上處理後,該帶式 WSID前進以獲取一新的處理區域,或者,該帶可以在處 理時朝一特定之方向逐段地移動,這種方式中,一段新的 10 帶式WSID部份會以一連續之方式移入該處理區域。 如第6圖中之另一實施例所示,一帶式WSID336可具 有在互相分開之處理區域338中分成多組之通道338 ’在 每次使用後,該等處理區域前進以便以一新的處理區域來 取代它們。以這種帶而言,在處理時該橫向移動主要是由 15 該晶圓載架來提供。It may have a channel 332 formed in a continuous pattern extending along the belt WSID 330. In this particular structure, the channels 332 are shaped as mostly parallel slots, but they can also be shaped as holes or holes with various geometries or radial structures. In this embodiment, depending on the processing requirements and the size of the wafer, most processing regions 334 can extend end-to-end. The tape WSID330 can be moved laterally on the board to perform mechanical cleaning actions. After some wafers are processed on the same processing area, the tape WSID 330 advances to obtain a new processing area, or the tape can During processing, it is moved piece by piece in a specific direction. In this way, a new 10-band WSID section is moved into the processing area in a continuous manner. As shown in another embodiment in FIG. 6, a belt WSID 336 may have channels 338 divided into groups in separate processing areas 338. 'After each use, the processing areas advance to perform a new process. Area to replace them. In the case of such a belt, the lateral movement during processing is mainly provided by the wafer carrier.
雖然該帶式WSID可具有一如第5與6圖所示之沿著 該帶式WSID延伸之單一通道圖案,但該帶式WSID也可 以包含多數孔或通道圖案。如第7圖所示,一帶式 WSID340可具有多數含有多數具有不同尺寸與形狀之通道 20 344之處理區域342A-342D,及多數在該等處理區域上用 以進行該清除動作之突起表面。例如,該處理區域342A 包含多數成形為圓孔之通道344,而該處理區域342B則包 含多數成形為槽孔狀之通道344,又,該處理區域342C包 含具有一徑向圖案之通道344且該處理區域342D包含形 20Although the belt WSID may have a single channel pattern extending along the belt WSID as shown in Figs. 5 and 6, the belt WSID may also include a plurality of hole or channel patterns. As shown in Fig. 7, the one-belt WSID 340 may have most of the processing areas 342A-342D containing most of the channels 20 344 having different sizes and shapes, and most of the protruding areas on these processing areas for performing the cleaning action. For example, the processing region 342A includes a plurality of channels 344 shaped as circular holes, and the processing region 342B includes a plurality of channels 344 shaped as slots, and the processing region 342C includes channels 344 having a radial pattern and the Processing area 342D contains shape 20
593787 成為多數矩形孔之通道344。在各處理區域342A-342D中 之通道344的形狀與尺寸亦可不同並且它們如何分布在該 特殊之處理區域上的方式也可不同,藉由使該特殊處理區 域之帶式WSID前進或回捲,各處理區域可以反覆地供 5 ECMD或ECME使用或進行化學蝕刻處理。藉由使該等通 道具有特定之形狀與分布,可以控制該銅層之輪廓。藉由 使用一特定之處理區域,該銅層之厚度輪廓可作成均勻或 可以改變成一必要之輪廓。例如,在一操作順序中,該晶 圓可先在該處理區域342A上進行ECMD處理,接著,相 10 同之晶圓可進行ECME處理或化學機械蝕刻以蝕回在該處 理區域342B上之平面銅層。在這例子中,該處理區域 342A可具有一適用於產生均勻沈積之ECMD製程之通道 圖案,且該處理區域342B可具有一適用於產生均勻材料 蝕刻或移除效果之ECME或CME製程之通道圖案。 15 在該ECMPR時,在該晶圓之前方表面與該電極317 之間有一電壓,如第8圖之該系統300的側視圖所示,該 晶圓320之前方表面係經由與該晶圓之前方表面318之周 緣區域接觸並在其上滑動之接點350而與一電源(圖未示) 連接。這些接點係揭露在於2001年1月17日申請且名稱 20 為“電沈積具有在基材上最小邊緣排除區域之均勻膜的方 法與裝置”之美國專利申請案第〇9/760,757號與於2001 年10月26日申請且名稱為“用以提供電處理製程用之電 氣接點的方法與系統”之美國專利暫時申請案第 60/348,758號,且這兩申請案係為本發明之受讓人所共同 21593787 becomes the passage 344 for most rectangular holes. The shape and size of the channels 344 in each processing area 342A-342D may also be different and how they are distributed on the special processing area may also be different, by advancing or rewinding the belt WSID of the special processing area Each processing area can be used repeatedly for 5 ECMD or ECME or chemical etching treatment. By making the channels have a specific shape and distribution, the contour of the copper layer can be controlled. By using a specific processing area, the thickness profile of the copper layer can be made uniform or can be changed to a necessary profile. For example, in an operation sequence, the wafer may first be subjected to ECMD processing on the processing region 342A, and then the same wafer may be subjected to ECME processing or chemical mechanical etching to etch back the plane on the processing region 342B. Copper layer. In this example, the processing region 342A may have a channel pattern suitable for an ECMD process that produces uniform deposition, and the processing region 342B may have a channel pattern suitable for an ECME or CME process that produces a uniform material etch or removal effect. . 15 In the ECMPR, there is a voltage between the front surface of the wafer and the electrode 317. As shown in the side view of the system 300 in FIG. 8, the front surface of the wafer 320 passes through the front of the wafer. The contact area 350 on the peripheral surface of the square surface 318 contacts and slides on it, and is connected to a power source (not shown). These contacts are disclosed in U.S. Patent Application No. 09 / 760,757, filed on January 17, 2001 and entitled "Method and Apparatus for Electrodepositing a Uniform Film with a Minimum Edge Exclusion Area on a Substrate" US Patent Provisional Application No. 60 / 348,758, filed on October 26, 2001 and titled "Method and System for Providing Electrical Contacts for Electrical Processing Processes", and these two applications are subject to the present invention. Make People Common 21
擁有。 593787 在有關該WSID緊臨且通常是接觸該晶圓之前方表面 的處理步驟中,在該前方表面上之金屬的小粒子或來自該 等來源之非導電粒子可附著在該WSID材料上。這些粒子 5 會由於它們僅由該基材表面上被移除或它們會因為該電鍍 溶液之不良過濾而由該電鍍溶液中產生而存在,這些粒子 可以使用本發明之調整裝置來清潔,如第9圖所示,該載 架頭302可包括一具有刷子362之調整裝置360,如圖所 示,如圖所示,該等刷子362係設置在該載架頭302之周 10 緣,該等刷子362係用以藉將粒子機械式清除而移除它們 來調整該帶式WSID303。在這實施例中,在該工作件320 上之ECMPR製程,不論是ECMD或ECME,與該帶式 WSID303之調整均可在同時,在相同之製程中發生。在這 特殊情形中,為了調整整個帶式WSID303,該載架頭302 15 或該帶式WSID303之橫向移動應較佳地等於或大於該載架 頭302之半徑,因此可有效地清潔該載架頭覆蓋之WSID 部份。或者,該等調整刷子未連接於該頭上,但它們使用 適當之裝置而被置於一被該頭之橫向移動所掃過之區域之 末端外,接著該帶可移動以使該處理區域之全長可確實地 20 被該等調整刷子刷過。 第10A-12圖顯示該帶式WSID之各種實施例,第10A 圖顯示一在一 ECMPR系統402中之帶式WSID400,如第 10B圖所詳示,該帶式WSID400係由一具有一頂層404與 一連接於該頂層之底層406之雙層結構形成,該頂層404 22 593787have. 593787 In the processing step concerning the WSID immediately and usually contacting the front surface of the wafer, small particles of metal on the front surface or non-conductive particles from these sources may be attached to the WSID material. These particles 5 may exist because they are only removed from the surface of the substrate or they may be generated from the plating solution due to poor filtering of the plating solution. These particles may be cleaned using the adjusting device of the present invention, as As shown in FIG. 9, the carrier head 302 may include an adjusting device 360 having a brush 362. As shown in the figure, as shown in the figure, the brushes 362 are disposed on the periphery of the carrier head 302. The brush 362 is used to adjust the band WSID303 by removing particles mechanically and removing them. In this embodiment, the adjustment of the ECMPR process on the work piece 320, whether it is ECMD or ECME, and the adjustment of the belt type WSID303 can occur at the same time and in the same process. In this special case, in order to adjust the entire belt WSID303, the lateral movement of the carrier head 302 15 or the belt WSID303 should preferably be equal to or larger than the radius of the carrier head 302, so the carrier can be effectively cleaned The WSID part covered by the header. Alternatively, the adjustment brushes are not attached to the head, but they are placed outside the end of an area swept by the lateral movement of the head using a suitable device, and then the band can be moved to make the entire length of the processing area It can be surely brushed by such adjustment brushes. Figures 10A-12 show various embodiments of the tape WSID. Figure 10A shows a tape WSID400 in an ECMPR system 402. As detailed in Figure 10B, the tape WSID400 consists of a tape with a top layer 404. Formed with a double layer structure connected to the bottom layer 406 of the top layer, the top layer 404 22 593787
可以是一研磨層或一含有研磨粒之層,而該底層406是一 可壓縮層。多數通道408係穿過該帶400而形成以便讓一 處理溶液407流過一電極408與一晶圓412之前方表面 410之間,請參閱第10A圖,在使用時,該帶400之可壓 5 縮層係放置在該系統402之板414上,該板包含多數通道 416以便讓處理溶液流過該板。在處理時,被該系統之硬 質板支持之該帶之可壓縮層將該帶推向該晶圓。在這實施 例中,與前述實施例不同,該可壓縮層是該帶式WSID全 體之一部份。在這例子與前述例子中,在該可壓縮層與該 10 板414之間的表面界面宜為一低摩擦界面。對上述實施例 之帶而言,該頂層之厚度宜為〇.2-2mm且該底層之厚度通 常是l-5mm,這兩層係被膠合在一起,並且該等通道之尺 寸係作成可讓流體流經其中。It may be an abrasive layer or a layer containing abrasive particles, and the bottom layer 406 is a compressible layer. Most of the channels 408 are formed through the band 400 so that a processing solution 407 flows between an electrode 408 and a front surface 410 of a wafer 412. Please refer to FIG. 10A. In use, the band 400 is compressible. 5 The drawdown is placed on a plate 414 of the system 402, which contains a plurality of channels 416 to allow the treatment solution to flow through the plate. During processing, the compressible layer of the tape supported by the system's rigid board pushes the tape towards the wafer. In this embodiment, unlike the previous embodiment, the compressible layer is an integral part of the tape WSID. In this example and the foregoing example, the surface interface between the compressible layer and the 10 plate 414 should be a low-friction interface. For the belts of the above embodiments, the thickness of the top layer should be 0.2-2mm and the thickness of the bottom layer is usually 1-5mm. The two layers are glued together, and the dimensions of the channels are made to allow Fluid flows through it.
第11A圖顯示一在一 ECMPR系統422中之帶式 15 WSID420,如在第11B.圖中所詳示,該帶式WSID420是由 一可為一研磨層或一含有研磨粒之層的單一層構成。通道 424係穿過該帶420而形成以便讓一處理溶液426流過一 電極428與一晶圓432之前方表面430之間,請參閱第 11A圖,在使用時,該帶420之係放堇在一具有多數置於 20 一框架438上之滾輪436的滾輪系統434上,該框架被浸 在該處理溶液中且可讓該處理溶液流過該滾輪系統。滚輪 係被並排地沿著該帶之寬度放置且它們可以在該製程中, 該晶圓接觸該帶時上下移動。在處理時,該滾輪系統將該 帶推抵住該晶圓且具有如同一在前述實施例所示之可壓縮 23FIG. 11A shows a belt 15 WSID420 in an ECMPR system 422. As detailed in FIG. 11B., The belt WSID420 is a single layer which can be a polishing layer or a layer containing abrasive particles. Make up. The channel 424 is formed through the band 420 to allow a treatment solution 426 to flow between an electrode 428 and a front surface 430 of a wafer 432. Please refer to FIG. 11A. On a roller system 434 having a plurality of rollers 436 placed on a frame 438, the frame is immersed in the processing solution and allows the processing solution to flow through the roller system. The rollers are placed side by side along the width of the tape and they can be moved up and down as the wafer contacts the tape during the process. During processing, the roller system pushes the belt against the wafer and has the same compressibility as shown in the previous embodiment 23
593787 層的作用。滾輪表面可較佳地含有可壓縮材料以在該晶圓 表面與該帶表面間建立接觸。 第12圖顯示在一在一 ECMPR系統442中之帶式 WSID440,該帶式WSID440是由一可為一研磨層或一含有 5 研磨粒之層的單一層構成。多數通道444係穿過該帶440 而形成以便讓一處理溶液446流過一電極448與一晶圓 452之前方表面451之間,該處理溶液係被貯置於一容器( 圖未示)中,該帶係在該製程時被支持在該容器之側壁之頂 端450。除此以外,該處理溶液之流動壓力將該帶推抵住 10 該晶圓且提供另一支持。該溶液之壓力係具有如同在前述 實施例所示之可壓縮層的作用。 第13A-13C圖顯示用以支持在第12圖中所示之前述 實施例中所述的帶440之各種另外的機構,如第13A圖所 示,該帶式WSID440亦可被多數位在該帶440下方且浮在 15 該處理溶液446上並且被該處理容器之壁頂部450包圍之 中空球體452,該等球體可填充有一如空氣的氣體或較輕 之氣體。除了該溶液之壓力外,球體452對該帶增加一另 外之可壓縮支持。 在第13B圖中,可藉由使用一可浮起層454而達成 20 相同之效果,該可浮起層454係放在該帶440下方且具有 多數可讓處理溶液446流經其中之通道456。該可浮起層 454可以由一如聚胺基甲酸酯之似海綿材料,該可浮起層 中亦可具有空氣囊(圖未示)。此外,如第13C圖所示,該 可浮起層454與該等球體452係被放在該帶440下方以達 24593787 layer role. The roller surface may preferably contain a compressible material to establish contact between the wafer surface and the belt surface. FIG. 12 shows a belt WSID440 in an ECMPR system 442. The belt WSID440 is composed of a single layer which can be an abrasive layer or a layer containing 5 abrasive particles. A plurality of channels 444 are formed through the strip 440 so that a processing solution 446 flows between an electrode 448 and a front surface 451 of a wafer 452. The processing solution is stored in a container (not shown). The belt is supported on the top 450 of the side wall of the container during the process. In addition, the flow pressure of the processing solution pushes the strip against the wafer and provides another support. The pressure of the solution has the effect of the compressible layer as shown in the previous embodiment. Figures 13A-13C show various additional mechanisms to support the band 440 described in the previous embodiment shown in Figure 12. As shown in Figure 13A, the band WSID440 can also be majority Hollow spheres 452 below the band 440 and floating on the processing solution 446 and surrounded by the top 450 of the processing container wall, these spheres may be filled with a gas such as air or a lighter gas. In addition to the pressure of the solution, the sphere 452 adds an additional compressible support to the band. In Figure 13B, the same effect can be achieved by using a floatable layer 454, which is placed under the belt 440 and has a majority of channels 456 through which the treatment solution 446 can flow. . The floatable layer 454 may be made of a sponge-like material like polyurethane, and the floatable layer may also have air bladders (not shown). In addition, as shown in FIG. 13C, the floatable layer 454 and the spheres 452 are placed under the belt 440 to reach 24.
成相同之目的。 593787 第14A與14B圖顯示一包含一第一帶式WSID602與 一位在該第一帶式WSID附近之第二帶式WSID604的多重 WSID系統600,如有需要,該系統600可具有兩個以上之 5 WSID帶。該系統600使一晶圓606可在處理時於帶602 與604兩者上被處理,該等帶602、604可具有如第5與6 圖所示之重覆通道圖案。該等帶亦可具有被設計用來供不 同厚度分布用之不同通道圖案,例如,該製程之第一步可 以一種產生邊厚沈積輪廓之方式來使用在該第一帶602上 10 ECMD,接著,該帶604可用於一 ECME步驟以減少該沈 積物之整體厚度。該帶604之圖案可由該等邊緣部份上蝕 刻掉更多之材料以產生均勻厚度輪廓,如果有需要,該製 程可在該第一帶上繼續並且反之亦然。 雖然各種較佳實施例已詳細說明過了,但是所屬技術 15 領域中具有通常知識者可以輕易地了解在不實質地偏離本 發明之新教示與優點的情形下所舉出之實施例可以有許多 變化例。 L圖式簡單說明3 第1A圖是一習知ECMPR系統之示意圖; 20 第1B圖是一工作件表面作用裝置之示意圖; 第2A圖是一具有多數構件形成於其中之基材表面之 表面區域的示意圖; 第2B圖是顯示在第2A圖中之基材的示意圖,其中銅 已被沈積在該基材表面上, 25For the same purpose. 593787 Figures 14A and 14B show a multiple WSID system 600 including a first tape WSID602 and a second tape WSID604 near the first tape WSID. If necessary, the system 600 may have more than two Of 5 WSID band. The system 600 enables a wafer 606 to be processed on both the strips 602 and 604 during processing. The strips 602, 604 may have repeating channel patterns as shown in Figures 5 and 6. The strips may also have different channel patterns designed for different thickness distributions. For example, the first step of the process may be to use a method of generating an edge thickness deposition profile on the first strip 602 10 ECMD, and then The strip 604 can be used in an ECME step to reduce the overall thickness of the deposit. The pattern of the tape 604 can be etched away from the edge portions to create more uniform thickness contours, and the process can continue on the first tape if necessary and vice versa. Although various preferred embodiments have been described in detail, those with ordinary knowledge in the field of the art 15 can easily understand that there can be many embodiments cited without substantially deviating from the new teachings and advantages of the present invention. Variations. Brief description of L diagram 3 FIG. 1A is a schematic diagram of a conventional ECMPR system; 20 FIG. 1B is a schematic diagram of a surface acting device of a work piece; and FIG. 2A is a surface region having a substrate surface in which most components are formed Figure 2B is a schematic view of the substrate shown in Figure 2A, in which copper has been deposited on the surface of the substrate, 25
置之ECMPR 第3圖疋一使用一帶式工作件表面作用裝 系統之示意圖; -第4A圖是該帶式工作件表面作用裝置之處理區段之 示意圖; 第4B圖是另一帶式工作件表面作用裝置之處理區段 之示意圖; 第5圖疋一具有多數有相同通道圖案之處理區段的工 件表面作用裝置之示意圖,其中該等處理區段並未分開 第6圖疋一具有多數有相同通道圖案之處理區段的工 作件表面作用裝置之示意圖,其中該等處理區段是分開的 ’ 第7圖是一具有多數有不同通道圖案之處理區段的工 作件表面作用裝置之示意圖; 第8圖是在第3圖所示之ECMPR系統中之電接點位 置的示意圖; 第9圖是本發明之工作件表面作用裝置之調整裝置的 示意圖; 第10A-12圖係該帶式工作件表面作用裝置之示意圖; 第13A-13C圖是另一帶式支持裝置之示意圖;及 第14A-14B圖是多數工作件表面作用裝置之示意圖。 【圖式之主要元件代表符號表】 100...ECMPR 系統 104···孔 10 6…晶圓Figure 3 of ECMPR: a schematic diagram of the surface acting system using a belt work piece;-Figure 4A is a schematic view of the processing section of the surface acting device of the belt work piece; Figure 4B is the surface of another belt work piece Schematic diagram of the processing section of the acting device; Figure 5: a schematic diagram of the workpiece surface acting device with most processing sections with the same channel pattern, wherein the processing sections are not separated; Figure 6: a majority having the same Schematic diagram of the work piece surface acting device of the processing section of the channel pattern, wherein the processing sections are separated. 'FIG. 7 is a schematic diagram of the work piece surface acting device having most processing sections with different channel patterns; Figure 8 is a schematic diagram of the electrical contact position in the ECMPR system shown in Figure 3; Figure 9 is a schematic diagram of the adjustment device of the surface-acting device of the work piece of the present invention; Figures 10A-12 are the belt type work pieces Schematic diagrams of surface acting devices; Figures 13A-13C are schematic diagrams of another belt support device; and Figures 14A-14B are schematic diagrams of surface acting devices of most work pieces. [Representative symbol table of main components of the drawing] 100 ... ECMPR system 104 ··· hole 10 6… wafer
102...WSID 593787102 ... WSID 593787
玖、.發明說明A 108.. .支持板 110…穿孔 111…晶圓載架 112…前方表面 5 113.··頂面 114…電解液 116.. .電極 120.. .頂層 122.. .中間層 10 124...底層 200.. .基材 202…圖案化層;絕緣層 204.. .工作件 206.. .第一凹孑L 15 208···第二凹孔 209…第二通孔 210…場區域;頂面 217.. .障壁或膠層 218.··薄膜 20 220…平面銅層 300.. .ECMPR 系統 301…帶式WSID總成 302.. .載架頭 303.. .帶式 WSID 304···上表面 306…背面 307.. .頂面 308…滾輪 309··.板 310A5310B,314···孔 311…供應捲軸 312.. .儲存捲軸 316.. .電蝕刻溶液 317.. .電極 318.. .前方表面 3 2 0...晶圓 321…處理區域 322···上層;可壓縮層 324…下層 330…帶式WSID 332…通道 334.··處理區域 336…帶式WSID 338.. .處理區域;通道 340…帶式WSID 342A-342D··.處理區域 27 593787 玖、發明說明:心. > ,-·《 " V Π- V //V、 V 344,..通道 4 3 4…滾輪糸統 3 5 0...接點 436...滾輪 352...周緣區域 438...框架 360...調整裝置 440.··帶式 WSID 5 362…刷子 442...ECMPR 系統 400···帶式 WSID 444...通道 402...ECMPR 系統...... 446…處理溶液 404...頂層 448...電極 406...底層 450··.前方表面 10 408…通道 4 5 2...晶圓 410...前方表面 451...頂端 412...晶圓 452...球體 414···板 454…可浮起層 416…通道 500...WSID 15 420…帶式WSID 502...突起表面 422".ECMPR 系統 504…頂面 424...通道 600...WSID 系統 426…處理溶液 602···第一帶式 WSID 428...電極 604···第二帶式 WSID 20 430··.前方表面 4 3 2...晶圓 606··.晶圓 28发明 .. Description of the invention A 108.... Support plate 110 ... perforation 111 ... wafer carrier 112 ... front surface 5 113 ... top surface 114 ... electrolyte 116 ... electrode 120 top layer 122 middle Layer 10 124 ... Bottom layer 200 ... Base material 202 ... Patterned layer; Insulation layer 204 ... Workpiece 206 ... First recess L 15 208 ... Second recess 209 ... Second pass Hole 210 ... field area; top surface 217 ... barrier or glue layer 218 ... film 20 220 ... plane copper layer 300 ... ECMPR system 301 ... belt WSID assembly 302 ... carrier head 303 ... .Belt type WSID 304 ... upper surface 306 ... back surface 307 ... top surface 308 ... roller 309 ... plate 310A5310B, 314 ... hole 311 ... supply reel 312 ... storage reel 316 ... electro-etching Solution 317 ... electrode 318 ... front surface 3 2 0 ... wafer 321 ... processing area 322 ... upper layer; compressible layer 324 ... lower layer 330 ... belt WSID 332 ... channel 334 ... processing area 336 ... belt WSID 338 ... processing area; channel 340 ... belt WSID 342A-342D ... processing area 27 593787 发明, invention description: heart. ≫,-· "" V Π- V // V , V 344, .. channel 4 3 4… roller system 3 5 0. .. contact 436 ... roller 352 ... peripheral area 438 ... frame 360 ... adjustment device 440 ... belt WSID 5 362 ... brush 442 ... ECMPR system 400 ... belt WSID 444 ... channel 402 ... ECMPR system ... 446 ... processing solution 404 ... top layer 448 ... electrode 406 ... bottom layer 450 ... front surface 10 408 ... channel 4 5 2. ..Wafer 410 ... front surface 451 ... top 412 ... wafer 452 ... sphere 414 ... plate 454 ... floatable layer 416 ... channel 500 ... WSID 15 420 ... belt type WSID 502 ... protruding surface 422 " .ECMPR system 504 ... top surface 424 ... channel 600 ... WSID system 426 ... processing solution 602 ... first band WSID 428 ... electrode 604 ... Two-belt WSID 20 430 ... Front surface 4 3 2 ... Wafer 606 ... Wafer 28
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US35021401P | 2001-11-02 | 2001-11-02 |
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EP (1) | EP1439935A2 (en) |
JP (1) | JP2005509092A (en) |
KR (1) | KR20040064699A (en) |
CN (1) | CN1646263A (en) |
AU (1) | AU2002363479A1 (en) |
TW (1) | TW593787B (en) |
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US6838149B2 (en) * | 2001-12-13 | 2005-01-04 | 3M Innovative Properties Company | Abrasive article for the deposition and polishing of a conductive material |
KR100767047B1 (en) * | 2006-05-20 | 2007-10-17 | 한국기계연구원 | A electro-polishing jig and the electro-polishing method of metal mask |
CN101987429B (en) * | 2009-08-07 | 2012-09-26 | 中芯国际集成电路制造(上海)有限公司 | Grinding method and device by chemical machinery |
CN109277655B (en) * | 2018-09-12 | 2020-02-21 | 南京航空航天大学 | Electrolytic spraying processing device and method for multi-pattern hollowed-out thin sheet metal band |
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US6176992B1 (en) * | 1998-11-03 | 2001-01-23 | Nutool, Inc. | Method and apparatus for electro-chemical mechanical deposition |
US6610190B2 (en) * | 2000-11-03 | 2003-08-26 | Nutool, Inc. | Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate |
US6241583B1 (en) * | 1999-02-04 | 2001-06-05 | Applied Materials, Inc. | Chemical mechanical polishing with a plurality of polishing sheets |
US6464855B1 (en) * | 2000-10-04 | 2002-10-15 | Speedfam-Ipec Corporation | Method and apparatus for electrochemical planarization of a workpiece |
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2002
- 2002-11-04 EP EP02802846A patent/EP1439935A2/en not_active Ceased
- 2002-11-04 JP JP2003543071A patent/JP2005509092A/en not_active Withdrawn
- 2002-11-04 CN CNA028264908A patent/CN1646263A/en active Pending
- 2002-11-04 KR KR10-2004-7006513A patent/KR20040064699A/en not_active Application Discontinuation
- 2002-11-04 AU AU2002363479A patent/AU2002363479A1/en not_active Abandoned
- 2002-11-04 TW TW091132514A patent/TW593787B/en not_active IP Right Cessation
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WO2003041126A3 (en) | 2003-11-06 |
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KR20040064699A (en) | 2004-07-19 |
CN1646263A (en) | 2005-07-27 |
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