588372 玖、發明說明 【發明所屬之技術領域】 _ 本發明係關於使用於半導體記憶體之出廠測試等之中· 的半導體記憶體測試圖案之製作方法。 【先前技術】 習知半導體記憶體之測試圖案的開發大槪依下述順序 進行的。 步驟1 半導體記憶體的電路設計。 步驟2 制定半導體記憶體的測試規格。 步驟3 測試規格的解讀、瞭解。 步驟4 測試圖案之製作。 步驟5 測試圖案之檢驗。 即’在步驟1中施fj半導體5己彳思體電路之開發後，便在 步驟2中利用人工製作半導體記憶體的測試規格書。此乃 因爲在分散工作量負擔等目的之下，便分別設定爲半導體 記憶體設計與記憶體評估的不同工作，步驟1與2由半導 體記憶體設計者負責，而步驟3以後的部分則由半導體記 憶體設計者之外不同的記憶體評估者負責執行的緣故所 致。 半導體記憶體之評估負責者便在步驟3中，針對由半導 體記憶體者所製作的測試規格書進行讀取、理解，並在步 驟4中利用人工製作對應於規格的測試圖案，同時在步驟 5中執行測試圖案的動作檢驗（譬如：參照專利文獻1 )。 (專利文獻1 ) 5 312/發明說明書(補件)/92-06/92106479 588372 曰本專利特開平4 - 1 8 6 1 7 8號公報（P 9 5 1 8行〜P ] Ο，1 2行） 【發明內容】 (發明所欲解決之問題） 習知測試圖案乃因爲依如上述順序進行製作，因此將存 在有下述問題：於步驟2中由半導體記憶體設計者所製作 的半導體記憶體測試規格書、及於步驟4中由半導體記憶 體評估負責者所製作的測試圖案將產生人爲失誤，而潛在 隨此失誤所衍生出的時間性損失，或爲防止上述失誤而增 加進行測試圖案確認作業的問題點。此外，利用人工所製 作的半導體記億體測試規格書，在格式化、描述內容方面 將存在誤差，導致半導體記憶體設計者、評估負責者間產 生解釋偏差的問題點。 本發明乃爲解決如上述問題點，其目的在於提供一種可 根據半導體記憶體設計者的半導體記憶體測試規格，製作 正確的半導體記憶體測試圖案，並可輕易的進行驗證，而 且亦可產生半導體記億體測試規格書的半導體記憶體測試 圖案之製作方法。 (解決問題之手段） 本發明的半導體記憶體測試圖案之製作方法，係製作出 依照未依存於半導體測試裝置種類的格式，所描述的半導 體記憶體測試圖案之動作資料，對上述動作資料利用對應 於上述格式的模倣（emu late)功能進行驗證之後，再根據上 述動作資料而輸出上述半導體記憶體的測試規格書。藉由 依照此順序而進行製作，便可解除習知技術中，在半導體 6 312/發明說明書(補件)/92-06/921〇6479 588372 記憶體設計者所製成的半導體記憶體測試規格書、以及半 導體記憶體評估負責者所製成的測試圖案的人爲失誤情 形，而可製作出正確的半導體記憶體測試圖案，且其驗證 亦變爲較容易。 【實施方式】 (實施形態1) 以下，針對本發明實施形態1根據圖式進行說明。圖i 所示乃實施形態1中的測試圖案開發順序流程圖。即，在 步驟S 1 1中執行半導體記憶體電路的開發之後，再於步驟 S 1 2中，於所開發記憶體電路的動作驗證、不良單元與預 備單元間的交換、以及去除不良晶片之目的下，製作出半 導體記憶體測試規格，但是在本實施形態中並非利用人工 製成規格書，而是採用文字編輯或專用工具而製作出半導 體記憶體測試中所需要的測試圖案動作資料。 再者，此測試圖案動作資料乃由未依存於半導體測試裝 置種類的格式進行描述。針對格式的內容，則容後述。 其次，在步驟S 1 3中，採用上述格式所對應的測試圖案 動作模倣功能，對上述測試圖案動作資料進行驗證。此驗 證乃由半導體記憶體設計者、或評估負責者之其中任何 者、或二者而執行。 然後，在步驟S 1 4中便根據經完成檢驗的測試圖案動作 資料’考慮每個半導體測試裝置的圖案表記差異而產生測 試圖案。 > 其次’針對上述測試圖案動作資料之未依存於半導體測 7 312/發明說明書(補件)/92-06/92106479 獨y/2 試裝置種類的格式進行說明。 圖2所示係半導體記憶體測試圖案動作資料的格式描述 例圖。此測試圖案動作資料的格式係具有A〜E的5個描述 邙。即，A係Const描述部，乃描述著圖案中未變更的資 汛。B係指pattern描述部，乃描述圖案動作的部分，如以 下所例不，描述圖案中進行變化的資訊。 即’ •寫人/讀取資料選擇（10=…） •資料編碼選擇（Data SCR=…） •位址編碼選擇（AddSCR=…） •更新時間設定（R e f r e s h =…） •電壓位準設定選擇（Level =…） •X位址最大値設定（XMAX=…） • Y位址最大値設定（YMAX =…） •C AS延遲設定（CL=…） •圖案列編號 •Row位址範圍設定（R〇w =…） •Column位址範圍設定（Co 1 =…） •遞增/遞減的優先順序設定（Prion.. } •適用指令選擇（Com=…） •位址跳躍目的地設定（JMPn) •位址跳躍次數設定（Loop=…） •資料反轉命令（DINV) •位址反轉命令（AINV) •停止命令（STOP) 312/發明說明書(補件)/92-06/92106479 8 588372 此外，C係I n c P r i ο ι·描述部，乃利用R 〇 w / C ο 1 u m η的各 位元名（RAn，CAn)定義位址遞增（Address Increment)、位址 遞減（a d d ι· e s s d e c r e m e n t)順序。 譬如當「P r i o r = R o w」的情況時，便依 R A 0 > R A 1 … 今R A 1 0 C A 0 + ·_· + C A 4 的順序進行遞增、遞減。D係 C o m m a n d S e t描述部，乃定義著利用P a 11 e r η描述部B中， 所描述「適用指令選擇（C o m =…）」所選擇到的指令名。以 下所例示資訊進行描述。 即 •圖案列編號 •應輸出波形的針腳資訊（如：CLK，ACT) •位址跳躍設定（JMPn) •位址跳躍次數設定（Loop ==…） •資料反轉命令（DINV) 再者，E係Level Set描述部，乃定義著利用Co n st描述 部A、或Pattern描述部B中所描述之「電壓位準設定選 擇（Lev el=…）」所選擇到的指令名。以下所例示資訊進行 描述。 即 •圖案列編號 •VDD電源電壓設定 •全輸入針腳的” Η ”，” L ”輸入位準設定 •全輸出針腳的”H”，”L”判定位準設定 其次，針對圖1中，步驟S 1 3所說明之測試圖案動作資 料之驗證手法進行詳細說明。記憶體圖案動作必須進行對 象物單元（位址）是否正確存取、寫入資料是否正確、以及 9 312/發明說明書(補件)/92-06/92106479 588372588372 发明 Description of the invention [Technical field to which the invention belongs] _ The present invention relates to a method for manufacturing a semiconductor memory test pattern that is used in factory testing of semiconductor memory and the like. [Prior art] The development of test patterns for conventional semiconductor memories has been performed in the following order. Step 1 Circuit design of semiconductor memory. Step 2 Develop test specifications for semiconductor memory. Step 3 Interpret and understand the test specifications. Step 4 Production of test pattern. Step 5 Inspection of test pattern. That is, after the development of the fj semiconductor 5 circuit in step 1 is implemented, the test specification of the semiconductor memory is manually produced in step 2. This is because for the purpose of spreading the workload and other purposes, it is set to different tasks of semiconductor memory design and memory evaluation. Steps 1 and 2 are the responsibility of the semiconductor memory designer, and the parts after step 3 are performed by the semiconductor. Caused by different memory evaluators other than the memory designer. The person in charge of the evaluation of the semiconductor memory reads and understands the test specifications made by the semiconductor memory person in step 3, and manually creates a test pattern corresponding to the specifications in step 4 and at the same time in step 5 The operation check of the test pattern is performed during the test (for example, refer to Patent Document 1). (Patent Document 1) 5 312 / Invention Specification (Supplement) / 92-06 / 92106479 588372 Japanese Patent Laid-Open No. 4-1 8 6 1 7 8 (P 9 5 1 8 lines to P) 〇, 1 2 [Contents] [Summary of the Invention] (Problems to be Solved by the Invention) Since the conventional test pattern is made in the above-mentioned order, there will be the following problem: a semiconductor memory produced by a semiconductor memory designer in step 2 The human body test specification and the test pattern produced by the person responsible for semiconductor memory evaluation in step 4 will cause human error, and the time loss resulting from this error may be increased, or the test may be added to prevent the above errors. Problems with pattern confirmation work. In addition, the manual use of the semiconductor memory test specification produced by the manual, there will be errors in the formatting and description of the content, leading to semiconductor memory designers, the person responsible for the evaluation of interpretation problems. The present invention is to solve the problems as described above, and the object thereof is to provide a semiconductor memory test pattern that can be made according to the semiconductor memory designer's specifications, and the correct semiconductor memory test pattern can be made, which can be easily verified, and can also generate semiconductor Manufacturing method of semiconductor memory test pattern of memory test specification. (Means for Solving the Problem) The method for making a semiconductor memory test pattern of the present invention is to create the operation data of the semiconductor memory test pattern according to a format that does not depend on the type of semiconductor test device, and use the corresponding operation data for the above operation data After the emu late function of the format is verified, a test specification of the semiconductor memory is output according to the operation data. By making in this order, the conventional technology can be lifted. In Semiconductor 6 312 / Invention Specification (Supplement) / 92-06 / 921〇6479 588372, a semiconductor memory test specification made by a memory designer. The human error of the test pattern made by the person in charge of the book and the semiconductor memory evaluation can make the correct semiconductor memory test pattern, and its verification becomes easier. [Embodiment 1] (Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings. Figure i is a flowchart of a test pattern development sequence in the first embodiment. That is, after the development of the semiconductor memory circuit is performed in step S 1 1, the operation verification of the developed memory circuit, the exchange between the defective unit and the standby unit, and the purpose of removing the defective wafer are performed in step S 12. Next, a semiconductor memory test specification is prepared. However, in this embodiment, instead of manually creating a specification book, a text editor or a special tool is used to create test pattern operation data required for the semiconductor memory test. Furthermore, the test pattern operation data is described in a format that does not depend on the type of the semiconductor test device. The content of the format will be described later. Next, in step S13, the test pattern action simulation function corresponding to the above format is used to verify the test pattern action data. This verification is performed by the semiconductor memory designer, or any of the persons responsible for the evaluation, or both. Then, in step S1, a test pattern is generated based on the test pattern operation data of the completed inspection, taking into account the difference in the pattern representation of each semiconductor test device. > Secondly, the format of the test pattern operation data which is not dependent on the semiconductor test 7 312 / Invention Specification (Supplement) / 92-06 / 92106479 alone / 2 type of test device will be described. Figure 2 shows an example of the format description of the operation data of the semiconductor memory test pattern. The format of the test pattern action data is 5 descriptions A to E 邙. That is, the A-series description department describes the unchanging resources in the pattern. B refers to the pattern description section, which describes the movement of the pattern. As shown in the following example, it describes the changes in the pattern. That's: • Write / read data selection (10 =…) • Data code selection (Data SCR =…) • Address code selection (AddSCR =…) • Update time setting (Refresh =…) • Voltage level setting Selection (Level =…) • X address maximum setting (XMAX =…) • Y address maximum setting (YMAX =…) • C AS delay setting (CL =…) • Pattern row number • Row address range setting (R〇w = ...) • Column address range setting (Co 1 =…) • Increment / decrement priority setting (Prion ..} • Applicable instruction selection (Com =…) • Address jump destination setting (JMPn ) • Number of Address Jumps (Loop =…) • Data Inversion Command (DINV) • Address Inversion Command (AINV) • Stop Command (STOP) 312 / Invention Manual (Supplement) / 92-06 / 92106479 8 588372 In addition, the C department is the I nc P ri ο · description department, which uses the meta names (RAn, CAn) of R 〇 w / C ο 1 um η to define Address Increment and Add ι · Essdecrement) sequence. For example, when "P rior = Row", then RA 0 > RA 1… now RA 1 0 CA 0 + · _ + + CA 4 in the order of increasing and decreasing. D is the Command Set description part, which defines the use of P a 11 er η in the description part B, so Describe the name of the instruction selected by "Applicable instruction selection (C om = ...)". The following information is used for description. That is: • Pattern row number • Pin information of the waveform to be output (eg: CLK, ACT) • Address jump setting (JMPn) • Setting of the number of address jumps (Loop ==…) • Data inversion command (DINV) Furthermore, E is the Level Set description section, which defines the use of Co n st description section A or Pattern description section B The name of the instruction selected in the described "Voltage level setting selection (Lev el = ...)". The following information is used to describe it. That is: • Pattern row number • VDD power supply voltage setting • “Η” for all input pins, ” L ”Input level setting • The“ H ”and“ L ”determination levels of all output pins are set next. The verification method of the test pattern action data described in step S 1 3 in Figure 1 will be described in detail. Memory pattern Action must be performed on the object Means (address) is correct access, write data is correct, and 9312 / present specification (complement member) / 92-06 / 92106479588372
Pause/Refresh時間是否正確等的確認。因此，位址動作便 如圖3所示，形成視覺式顯示俾容易判斷。 圖3所示係圖2所示動作資料所對應的輸出例。箭頭係 指位址動向，橫軸係R 〇 w，縱軸係c 〇 ] u m η，方塊內的文字 係記憶體指令名。當利用W R I Τ Ε指令寫入於半導體記憶體 中的資料爲"Η”的情況時，便如圖所示，對單元賦予顏色。 因爲依此方式進行顯示，當如位址在最大値以上進行動 作、或Row/Column優先順序不同等位址動作產生異常的 情況時’便可由圖中輕易得知其不同處。 其次’針對輸出從半導體記憶體設計者提供給評估負責 者的半導體記憶體測試規格書之功能進行說明。相關根據 圖2之動作資料所輸出的資料圖案的資訊例，乃如圖4所 示。此資訊在習知技術中乃如上述，係由半導體記憶體設 計者利用人工進行製作的，但是依照本實施形態的話，因 爲可從圖2所示測試圖案動作資料自動的產生，因此不致 產生描述內容誤差現象’且半導體記憶體設計者、評估負 責者間的解釋亦無偏差現象發生，可無須爲防止隨該等現 象所衍生出之時間損耗或失誤等現象，而所採取的測試圖 案確認作業等事項。 (發明之效果） 本發明的半導體記憶體測試圖案之製作方法，乃因爲製 作出依照未依存於半導體測試裝置種類的格式，所描述的 半導體記憶體測試圖案之動作資料，對上述動作資料利用 對應於上述格式的模倣功能進行驗證之後，再根據上述動 10 312/發明說明書(補件)/92-06/92106479 588372 作資料而輸出上述半導體記憶體的測試規格書，因此可無 須進行爲防止隨半導體記憶體測試規格書、或測試圖案的 人爲失誤而衍生時間損耗或失誤等現象所做的測試圖案確 §忍作業等事項。 【圖式簡單說明】 圖1爲本發明實施形態1中，測試圖案之開發順序流程 圖。 圖2爲實施形態1中，半導體記憶體測試圖案動作資料 的格式描述例圖。 圖3爲圖2所示動作資料所對應的輸出例圖。 圖4爲根據圖2之動作資料所輸出讀測試圖案資訊例 圖。 11 312/發明說明書(補件)/92-06/92106479Check whether the Pause / Refresh time is correct. Therefore, the address operation is as shown in FIG. 3, and a visual display is formed, which is easy to judge. FIG. 3 is an example of an output corresponding to the action data shown in FIG. 2. The arrows refer to the direction of the address, the horizontal axis is R o w, the vertical axis is c o] u m η, and the text in the box is the name of the memory command. When the data written in the semiconductor memory using the WRI Τ Ε instruction is " Η ", the cell is given a color as shown in the figure. Because the display is performed in this way, when the address is above the maximum 値When an operation is performed or an abnormality occurs in an address operation such as a different Row / Column priority order, the difference can be easily known from the figure. Secondly, the semiconductor memory provided by the semiconductor memory designer to the person in charge of evaluation for the output. The function of the test specification is explained. An example of information related to the data pattern output according to the action data of Fig. 2 is shown in Fig. 4. This information is as described above in the conventional technology and is used by the semiconductor memory designer. It is made manually, but according to this embodiment, because the test pattern action data shown in FIG. 2 can be automatically generated, there is no description content error phenomenon, and there is no explanation between the semiconductor memory designer and the person in charge of evaluation. Deviation phenomena do not need to be taken to prevent phenomena such as time loss or errors caused by these phenomena. Matters such as test pattern confirmation work (Effects of the invention) The method of making the semiconductor memory test pattern of the present invention is because the operation data of the semiconductor memory test pattern described in accordance with a format that does not depend on the type of semiconductor test device is produced. After verifying the above-mentioned action data by using the imitation function corresponding to the above-mentioned format, according to the above-mentioned action 10 312 / Invention Specification (Supplement) / 92-06 / 92106479 588372, the test specifications of the semiconductor memory are output, Therefore, there is no need to perform test pattern confirmation operations to prevent phenomena such as time loss or errors caused by human error caused by semiconductor memory test specifications or test patterns. [Schematic description] Figure 1 is A flowchart of the development sequence of the test pattern in Embodiment 1 of the present invention. Fig. 2 is a format description example of the operation data of the semiconductor memory test pattern in Embodiment 1. Fig. 3 is an output example corresponding to the operation data shown in Fig. 2 Figure 4. Figure 4 is an example of reading test pattern information output based on the action data of Figure 2. 11 312 / Send Description (up member) / 92-06 / 92106479