JP2004118301A - Forming method and device of developable test program tool - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a forming method of a developable test program tool for allowing even an inexperienced engineer to make a test pattern program in a short period in the forming method and the device of the developable test program tool, and a device thereof. <P>SOLUTION: This device comprises a CPU 10 for controlling the whole operation, a display 12 connected to the CPU 10 and displaying an editing image screen, a map image screen tool 21, a flowchart making tool 22, a converting tool 23 for converting a flowchart made by the flowchart making tool 22 into a pseudo-test program, a write/read operation forming tool 24 for making write/read operation and a storage device 20 including a joining tool 25 for joining the pseudo-test program converted by the converting tool 23 and a program formed by the write/read operation forming tool 24. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for generating an expandable test program tool.
[0002]
In recent years, with the progress of semiconductor technology, the configuration of ICs, LSIs, and the like has also become complicated. For this reason, a test apparatus for testing this kind of IC or LSI has become complicated and sophisticated. Therefore, an operator who operates the test apparatus also needs a specialized operator who is familiar with the test apparatus. However, it is preferred that even beginners can easily operate the device.
[0003]
[Prior art]
Conventional devices of this type include a semiconductor test device having a function of generating a memory test pattern by automatically generating a pattern execution program and a function of determining whether a test pattern program can be generated and reporting whether a pattern can be generated. It is known (see Patent Document 1). Also, a plurality of test conditions describing a two-dimensional scanning direction for generating a write signal and a test pattern required for the semiconductor memory are prepared, and a list of the prepared plurality of test conditions is displayed to select a test condition. Generating a test pattern program based on a process, a process of setting a two-dimensional scanning region for generating a test pattern, and test conditions for the selected plurality of steps and the set two-dimensional scanning region. An LSI test pattern program automatic generation method having a process is known (see Patent Document 2).
[0004]
In this type of system, a specialized engineer manually develops a test program.
[0005]
[Patent Document 1]
JP-A-4-186178 [Patent Document 2]
JP 2001-155497 A
[Problems to be solved by the invention]
The above-described conventional technique has the following problems.
(1) Since the development of memory test programs requires specialized knowledge, the training of development engineers requires at least two to three years. In order to test a memory IC, it is necessary to create a test pattern. However, since a test pattern is conventionally created using an assembler system and the creation procedure is very complicated, a skilled technician is required.
{Circle around (2)} The test program creation method is completely different for each type of semiconductor (DDR, SDRAM, etc.).
(3) The programming language is complicated and debugging is difficult.
(4) Development time is required. For example, an average test program takes about three weeks on average.
[0007]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a method and an apparatus for generating an unfoldable test program tool that enable even an inexperienced engineer to create a test pattern program in a short time. And
[0008]
[Means for Solving the Problems]
(1) FIG. 1 is a flowchart showing the principle of the present invention. According to the present invention, the test pattern operation is mapped (Step 1), the mapped pattern operation is divided into each event (Step 2), the pattern operation is formed into a flowchart (Step 3), and a pseudo test program is created from the flowchart. (Step 4), a write / read operation is generated in a plurality of stages (Step 5), and the pseudo test program is combined with the generated write / read operation (Step 6).
[0009]
According to the present invention, the pattern operation can be made into a flowchart by mapping the test pattern operation. Since the creation of this flowchart is a normal flowchart creation, the creation is easy. When the creation of this flowchart is completed, the development test program can be easily created by combining the creation of the pseudo test program and the write / read operation.
(2) The invention according to claim 2 is characterized in that the test pattern is any one of Mscan, March, and Massest methods.
[0010]
According to this, the present invention can be applied to any of the existing technologies such as Mscan, March, and Massest.
(3) The invention according to claim 3 is a CPU for controlling the entire operation, a main storage device connected to the CPU, a display connected to the CPU for displaying an editing screen, various operation commands, An operation unit for inputting symbols and numerical values, a map screen tool, a flowchart creation tool, a conversion tool for converting a flowchart created by the flowchart creation tool into a pseudo test program, and a write / read action creation tool for creating a write / read action And a storage device including a combining tool for combining the pseudo test program converted by the conversion tool and the program generated by the write / read operation generation tool.
[0011]
According to this structure, the test pattern operation is mapped by the map screen tool, so that the pattern operation can be made into a flowchart by the flowchart creation tool. Since the creation of this flowchart is a normal flowchart creation, the creation is easy. When the creation of the flowchart is completed, the development test program can be easily created by combining the creation of the pseudo test program and the write / read operation using the conversion tool and the combining tool.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0013]
Hereinafter, the flowchart shown in FIG. 1 will be described in more detail.
(Step 1) Mapping Test Pattern Operation FIG. 2 is a diagram showing the correspondence between memory cells and addresses. In (a), a to d are memory cells. In order to represent the cell (element) by coordinates, the coordinates in the x (row) and y (column) directions are considered. The coordinates of each cell are represented as shown in FIG. That is, the value of the cell a in the x-axis direction is 0, and the value in the y-direction is 0. Similarly, the value of the cell b in the x-axis direction is 1, and the value in the y-direction is 0. In this manner, the values of the cells a to d are represented by coordinates as shown in FIG. Although FIG. 2 illustrates the case where the number of cells is 2 × 2 = 4 for simplicity, the actual number of cells is enormous.
[0014]
The features of the present invention are that the writing and reading operations to and from the cell are represented by a map (MAP), and the operation of the cell is represented by a general flowchart. Hereinafter, mapping of the March method will be described. FIG. 3 is an explanatory diagram of the operation of the first event. For a 2 × 2 memory cell, data “0” is written (Write) from the cell at the address (0, 0) to the cell at the address (1, 1).
[0015]
FIG. 4 is an explanatory diagram of the operation of the second event. In this case, the operation of reading “0” and writing “1” is repeated from the cell (0, 0) to the element (1, 1). For example, "0" is read first, and then "1" is written to the cell (0, 0). Since the data of each memory cell is all "0" in the first event, the first operation in the second event is to read this "0". Such a read operation of “0” and a write operation of “1” are repeated up to the cell of (1, 1).
[0016]
FIG. 5 is an explanatory diagram of the operation of the third event. In this event, the operation is performed from the cell (1, 1) to the cell (0, 0) in the reverse direction. First, data “1” is read from the cell (1, 1). Since the value of each cell is all "1" in the second event, data "1" is read. After reading "1", "0" is written to the cell having the same coordinates. Next, data "1" is read from the cell at (0, 1), and "0" is then written into the cell at the same coordinates. This operation is repeated until (0,0).
[0017]
FIG. 6 is an explanatory diagram of the fourth event. In event 3, the content of each cell is "0". Therefore, a read operation is performed on all cells from (0, 0) to (1, 1). Consider mapping the operation so far.
[0018]
FIG. 7 is an explanatory diagram of mapping of a test pattern operation. (A) of the figure is an explanatory diagram of the first event, (b) is an explanatory diagram of the second event, (c) is an explanatory diagram of the third event, and (d) is an explanatory diagram of the fourth event. For example, (a) is composed of 2 × 2 cells similar to the case shown in FIG. (A) shows that "0" is written to all cells. Here, W0 indicates that "0" is to be written.
[0019]
(B) shows that "0" is first read from each cell and then "1" is written. The symbol <1> R0 in the cell in the figure indicates that "0" is to be read, and the symbol W1 in the same cell indicates that "1" is to be written. (C) indicates that "1" is first read from the cell, and then "0" is written to the same cell. (D) indicates that "0" is read from each cell. As is clear from the above description, the first event shown in (a) is shown in FIG. 3, the second event shown in (b) is shown in FIG. 4, the third event shown in (c) is shown in FIG. The events shown in parentheses) correspond to FIG. The feature of the present invention is that the test pattern operation is mapped as shown in FIG. (Step 2) Dividing the Pattern Operation into Events Each map operation shown in FIG. 7 shows that each map operation is independent of the other map operations. Therefore, it is considered that these maps are divided for each map operation. FIG. 8 shows a state in which the map of each stage shown in FIG. 7 is divided for each event.
(Step 3) Making a Flowchart of Pattern Operations As shown in FIG. 8, when each pattern operation is divided into events, it is considered that the operations of these events are made into a flowchart. FIG. 9 is a diagram showing an operation flowchart of the first event. The first event is, as described with reference to FIG. 3, an operation of writing “0” to all the 2 × 2 memory cells. Therefore, it will be proved below that the flowchart shown in FIG. 8 faithfully reproduces this operation.
[0020]
First, x = 0 is set (S1), and then y = 0 is set (S2). As a result, the coordinates of the first cell (0, 0) have been obtained. Next, "0" is written to the cell at the address (0,0) (S3).
[0021]
After the writing of "0" to the cell at the address (0,0) is completed, x = x + 1 is calculated (S4). As a result, the coordinates of the new cell are (1, 0). next,
It is checked whether x> 1 (S5). Now, since x = 1, this condition does not hold. Therefore, the process returns to step S3 again to write "0". As a result, "0" is written in the cell (1, 0).
[0022]
Next, x = x + 1 is calculated (S4). As a result, x = 2. Here, it is checked whether x> 1 (S5). Since x = 2, x> 1 holds. Then, x = 0 is set next (S6). Next, y = y + 1 is calculated (S7). Since y is initially “0”, the calculation of y = y + 1 results in y = 1. The address (0, 1) is designated by the above procedure.
[0023]
Next, it is checked whether or not y> 1 (S8). Since y = 1 and y> 1 are not satisfied, the process returns to step S3. Then, "0" is written to the cell at the address (0, 1) (S3). Next, x = x + 1 is calculated (S4). Since x = 0 now, x + 1 becomes "1". In this state, the address (1, 1) is designated.
[0024]
Next, it is checked whether x> 1 (S5). Since x> 1 is not satisfied, the process returns to step S3 and writes "0". Thus, "0" has been written to the cell at the address (1, 1). Next, when x = x + 1 is calculated (S4), x = 2. Next, it is checked whether x> 1 holds. Since x> 1 holds, next, x = 0 is set (S6). Then, y = y + 1 is calculated (S7). As a result, y = 2. Next, it is checked whether y> 1 is satisfied (S8). Since y = 2, y> 1 is satisfied, and then y = 0 (S9). Thus, the coordinates of the cell return to (0, 0), and the process ends.
[0025]
As is clear from the above operation, the flowchart shown in FIG. 8 indicates the operation of event 1 (writing "0" to all 2 × 2 cells).
(Step 4) Creation of a pseudo test program When the flowchart of the pattern operation is completed in step 3, a pseudo test program is created from this flowchart. FIG. 10 is a flowchart for generating the pseudo test program. As apparent from comparison with the flowchart shown in FIG. 9, FIG. 10 corresponds to FIG. In FIG. 10, x in FIG. 9 is indicated as X, and y in FIG.
[0026]
The procedure for creating a test pattern is generally difficult to understand, and the test pattern creating unit can be generally considered as a black box. "Pseudo" in the pseudo test program means the first conversion. Symbols “XMAX”, “YMAX”, “JNI1”, and “JNI2” used in the flowchart of FIG. 9 are languages used in actual test patterns. The symbol “X <0” used in FIG. 10 has the same meaning as “x = 0” used in the flowchart of FIG. 9, and the symbol “Y <0” used in FIG. , "Y = 0" used in the flowchart of FIG. XMAX and JNI1 form a combination, and YMAX and JNI2 form a combination.
[0027]
The flowchart shown in FIG. 10 is not actually displayed, but is shown for reference. The test pattern creation unit inputs the flowchart shown in FIG. 9 and converts it into a pattern for a test program. Although this conversion sequence is not actually visible, it is shown with a part thereof visible. In short, it is shown by inputting the normal flowchart shown in FIG. 9 so that it can be visually observed that the sequence is automatically converted into the sequence for the test pattern.
(Step 5) Generation of Write / Read Operation Next, the second conversion is performed. FIG. 11 is a diagram showing a write / read generation step. More specifically, it shows a step of generating WRITE '0' shown in step S5 of FIG. The figure shows a WRITE “0” operation of an SDRAM (a type of RAM). The sequence differs according to the type of RAM.
[0028]
In step 1, WRITE and READ portions are extracted. Next, in step 2, the operation is an active operation. This ACTIVE enables chip select (CS) and RAS (a type of command). The WRITE sequence includes an active (S1), a WRITE (S2), a TPH (an expected value of an exit bit), and a precharge (PRE: a type of command) (S3).
[0029]
Step 3 is a sequence for defining a connection between an IC tester (for example, an LSI tester) and an IC. FIG. 12 is a diagram showing a physical connection state between the IC tester and the IC. In the figure, 1 is an IC tester, and 2 is an IC connected to the IC tester 1. C1, C2, C3 and C4 are terminal names of the IC tester 1. On the other hand, CS, RAS, CAS (a type of command), and write enable (WE) are terminal names on the IC2 side. When the terminal names C1 to C4 on the IC tester 1 side become "0", they become low active.
[0030]
In step 3, CS and RAS are enabled (ENABLE) (S1), then CS, CAS and WE are enabled (S2), and then CS, RAS and WE are enabled (S3).
[0031]
In step 4, as shown in the figure, the operations of steps S1 to S3 are performed. That is, CS = C1, RAS = C2 (S1), then CS = C1, CAS = C3, WE = C4 (S2), and then CS = C1, RAS = C2, WE = C4 (S3). . With the above processing, the sequence of generating the WRITE operation in four stages ends. Note that the processing at each stage is different depending on the type of RAM used.
(Step 6) Combination processing By combining the pseudo test program created in Step 4 and the write / read operation created in Step 5, a final test pattern for an integrated circuit such as an IC is created. Will be. Specifically, the write sequence created by the sequence shown in FIG. 11 is inserted into step S5 in FIG.
[0032]
The above description describes the case of event 1. For the events 2 to 4, it is necessary to create a flowchart as shown in FIG. 9, then generate a pseudo test program as shown in FIG. 10, and generate a write / read as shown in FIG. .
[0033]
As described above, according to the present invention, an expanded test program can be easily created.
[0034]
The test pattern generation sequence described above is based on the March method, but the present invention is not limited to this, and can be used in other methods, for example, the Mscan or Massest method. Here, the Mscan method is a method of writing all “0” to all memory cells and reading all “0”, or writing all “1” to all memory cells and reading all “1”. is there.
[0035]
The Massest method performs a read / write operation alternately from the end of a cell. FIG. 13 is an explanatory diagram of the Massest method. For example, 4 × 4 memory cells are used as shown in FIG. Then, as shown in (a), all "0" is written in column 0, all "1" is written in column 1, all "0" is written in column 2, and all "1" is written in column 3. That is, "0" and "1" are written alternately.
[0036]
When the writing to the memory cell is completed, the operation proceeds to the cell reading operation. The cell read operation is as shown in FIG. First, "0" is read from the cell (0,0), and then "1" is read from the cell (3,3). Next, "0" is read from the cell (1, 0), and "1" is read next from the cell (2, 3). Such an operation is repeated. That is, the read operation is performed while moving the cells from both ends of the four corners toward each other.
[0037]
FIG. 14 is a block diagram showing a system configuration example of the present invention. In the figure, reference numeral 10 denotes a CPU for performing the overall control operation, 11 denotes a main storage device connected to the CPU 10, 12 denotes a display connected to the CPU 10 and displays a sequence status and the like, and 13 denotes various operation commands, symbols and numerical values. Is an operation unit for inputting the "." For example, a RAM or the like is used as the main storage device 11, and a CRT or a liquid crystal display is used as the display 12, for example. As the operation unit 13, for example, a keyboard, a mouse, or the like is used.
[0038]
Reference numeral 20 denotes a storage device connected to the CPU 10. As the storage device 20, for example, a large-capacity hard disk device or the like is used. In the storage device 20, 21 is a MAP screen tool for generating a map screen as shown in FIG. 6, and 22 is a flowchart creation tool for creating a flowchart as shown in FIG. 23 is a conversion tool for converting a flowchart into a test program corresponding to the type of test pattern, 24 is a write / read operation generation tool for generating a write / read operation in a plurality of stages, 25 is a test program converted by the conversion tool 23, This is a combination tool for combining the program generated by the write / read operation generation tool 24. In the conversion tool 23, a pattern storage unit 30 stores a pattern type corresponding to a test pattern generation method. The storage pattern 30 stores a test pattern corresponding to the type of the device under test. Each of such tools is configured by a program (software) here.
[0039]
In the apparatus configured as described above, various commands for performing a series of operations are input from the operation unit 13, and the CPU 10 interprets the commands and generates a test program. The MAP screen tool 21 MAPs the operation of the test pattern. The flowchart creation tool 22 creates a flowchart for realizing the pattern generated by the MAP screen tool 21. The conversion tool 23 performs conversion into a test pattern by referring to the storage pattern 30 according to the type of the device under test (for example, a memory IC). The write / read operation generation tool 24 converts a write or read operation into a test pattern. The combination tool 25 combines the test program converted by the conversion tool 23 and the test program generated by the write / read operation generation tool 24.
[0040]
By mapping the test pattern operation with the map screen tool 21, the pattern operation can be converted into a flowchart with the flowchart creation tool 22. Since the creation of this flowchart is a normal flowchart creation, the creation is easy. When the creation of this flowchart is completed, the output of the conversion tool 23 and the output of the write / read operation tool 24 are combined using the combining tool 25, so that the development test program can be easily created.
[0041]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
[0042]
(1) According to the first aspect of the invention, by mapping the test pattern operation, the pattern operation can be made into a flowchart. Since the creation of this flowchart is a normal flowchart creation, the creation is easy. When the creation of this flowchart is completed, the development test program can be easily created by combining the creation of the pseudo test program and the write / read operation.
[0043]
(2) According to the second aspect of the present invention, the present invention can be applied to any of the existing techniques, such as the Mscan, March, and Massest methods.
[0044]
(3) According to the third aspect of the invention, by mapping the test pattern operation with the map screen tool, the pattern operation can be made into a flowchart with the flowchart creation tool. Since the creation of this flowchart is a normal flowchart creation, the creation is easy. When the creation of the flowchart is completed, the development test program can be easily created by combining the creation of the pseudo test program and the write / read operation using the conversion tool and the combining tool.
[0045]
As described above, according to the present invention, it is possible to provide a method and an apparatus for generating a developed test program tool that enable even an inexperienced engineer to create a test pattern program in a short period of time.
[Brief description of the drawings]
FIG. 1 is a flowchart showing the principle of the present invention.
FIG. 2 is a diagram showing correspondence between memory cells and addresses.
FIG. 3 is an explanatory diagram of an operation of a first event.
FIG. 4 is an operation explanatory diagram of a second event.
FIG. 5 is an explanatory diagram of an operation of a third event.
FIG. 6 is an explanatory diagram of a fourth event.
FIG. 7 is an explanatory diagram of mapping of a test pattern operation.
FIG. 8 is an explanatory diagram of division of a pattern operation into events.
FIG. 9 is a diagram showing an operation flowchart of a first event.
FIG. 10 is a generation flowchart of a pseudo test program.
FIG. 11 is a diagram showing a write / read generation step.
FIG. 12 is a diagram showing a physical connection state between an IC tester and an IC.
FIG. 13 is an explanatory diagram of the Masest method.
FIG. 14 is a block diagram showing a system configuration example of the present invention.
[Explanation of symbols]
10 CPU
11 Main Storage Device 12 Display 13 Operation Unit 20 Storage Device 21 Map Screen Tool 22 Flowchart Creation Tool 23 Conversion Tool 24 Write / Read Operation Generation Tool 25 Combination Tool 30 Pattern Storage Unit

Claims (3)

Map the test pattern operation (step 1),
The mapped pattern operation is divided into each event (step 2),
A flow chart of the pattern operation (step 3),
A pseudo test program is created from the flowchart (step 4),
Write / read operation is generated in multiple stages (step 5),
Combining the pseudo test program with the generated write / read operation (step 6)
A method for generating a deployment-type test program tool, characterized in that: The method according to claim 1, wherein the test pattern is one of a Mscan, March, and Massest method. A CPU for controlling the entire operation;
A main storage device connected to the CPU;
A display connected to the CPU and displaying an editing screen;
An operation unit for inputting various operation commands, symbols, and numerical values,
A map screen tool, a flowchart creation tool, a conversion tool for converting a flowchart created by the flowchart creation tool into a pseudo test program,
A write / read operation generation tool for generating a write / read operation;
A storage device including a combination tool for combining the pseudo test program converted by the conversion tool and the program generated by the write / read operation generation tool;
An operation device of a deployable test program tool configured to include:

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