TW586677U - Stack structure of chip package - Google Patents

Stack structure of chip package

Info

Publication number
TW586677U
TW586677U TW92201153U TW92201153U TW586677U TW 586677 U TW586677 U TW 586677U TW 92201153 U TW92201153 U TW 92201153U TW 92201153 U TW92201153 U TW 92201153U TW 586677 U TW586677 U TW 586677U
Authority
TW
Taiwan
Prior art keywords
chip package
stack structure
stack
package
chip
Prior art date
Application number
TW92201153U
Other languages
English (en)
Inventor
Steven Lee
Andy Liao
Jen-Te Tseng
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW92201153U priority Critical patent/TW586677U/zh
Priority to US10/604,409 priority patent/US6919628B2/en
Publication of TW586677U publication Critical patent/TW586677U/zh

Links

Classifications

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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
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    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW92201153U 2003-01-22 2003-01-22 Stack structure of chip package TW586677U (en)

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US20080224305A1 (en) * 2007-03-14 2008-09-18 Shah Amip J Method, apparatus, and system for phase change memory packaging
SG149724A1 (en) * 2007-07-24 2009-02-27 Micron Technology Inc Semicoductor dies with recesses, associated leadframes, and associated systems and methods
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US7906853B2 (en) * 2007-09-06 2011-03-15 Micron Technology, Inc. Package structure for multiple die stack
JP2012094592A (ja) * 2010-10-25 2012-05-17 Elpida Memory Inc 半導体装置及びその製造方法
JP5514134B2 (ja) * 2011-02-14 2014-06-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9824924B2 (en) * 2013-03-29 2017-11-21 Stmicroelectronics Pte Ltd. Semiconductor packages having an electric device with a recess
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020150159A1 (en) 2019-01-14 2020-07-23 Invensas Bonding Technologies, Inc. Bonded structures
CN111834438B (zh) * 2019-04-18 2024-05-31 西部数据技术公司 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
KR20210017271A (ko) * 2019-08-07 2021-02-17 삼성전기주식회사 반도체 패키지
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element

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