TW584969B - Method for manufacturing poly-Si of thin-film transistor - Google Patents

Method for manufacturing poly-Si of thin-film transistor Download PDF

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Publication number
TW584969B
TW584969B TW92106556A TW92106556A TW584969B TW 584969 B TW584969 B TW 584969B TW 92106556 A TW92106556 A TW 92106556A TW 92106556 A TW92106556 A TW 92106556A TW 584969 B TW584969 B TW 584969B
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layer
film transistor
thin film
substrate
manufacturing
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TW92106556A
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TW200419807A (en
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Ching-Lin Fan
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Ritdisplay Corp
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Abstract

A method for manufacturing poly-Si of a thin-film transistor comprises providing a substrate; depositing a first amorphous silicon layer on the substrate; using an excimer laser to irradiate the first amorphous silicon layer to form a seed crystal layer; depositing a second amorphous silicon layer on the seed crystal layer; and performing a furnace annealing.

Description

584969 五、發明說明(1) (一)、【發明所屬之技術領域】 本發明係關於一種薄膜電晶體之多晶矽製造方法,特 別是一種應用於低溫(low temperature processed, LTP)多晶石夕薄膜電晶體之多晶石夕製造方法。 (二)、【先前技術】 低溫多晶石夕薄膜電晶體一般係用於主動式液晶顯示器 (active matrix liquid crystal display, AMLCD)以及 主動式有機電激發光顯示器(active matrix organic light-emitting display,AM0LED)等大面積之顯示器 中。由於低溫多晶矽薄膜電晶體具有電子移動速率較快等 優點’使其成為新一代主流製程之一。然而,欲製作高性 能之低溫多晶矽薄膜電晶體,其中最困難的步驟之一係將 非晶石夕(amorphous silicon, α - S i )轉換成多晶矽(p〇! y silicon, po1y-Si ) o · 於習知技術中,一般係利用固相結晶法(s〇Hd phase crystallization,SPC)在溫度約60(rc的環境下將玻璃基 板上的非晶矽層轉換成多晶矽層。如圖丨A所示,於形成有& 緩衝氧化層2 2的一石夕基材2 1表面上沉積一非晶石夕層2 3。 接著,以固相結晶法將非晶矽層23轉換成一多晶矽層24, 如圖1B所示。然而,固相結晶法需要非常長的製程時間, (約2 0 — 6 0小時)以形成較大的晶粒尺寸,所以並不適合 工f上的應用。另外,利用固相結晶法所形成之多晶矽^ 有高密度的晶粒内部缺陷(in-grain defect),更進一 % 一歩584969 V. Description of the invention (1) (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing polycrystalline silicon of a thin film transistor, particularly a low temperature processed (LTP) polycrystalline silicon thin film Method for manufacturing polycrystalline stone of transistor. (2) [Previous technology] Low temperature polycrystalline silicon thin film transistors are generally used in active matrix liquid crystal display (AMLCD) and active organic organic light-emitting display (active matrix organic light-emitting display, AM0LED) and other large area displays. The low temperature polycrystalline silicon thin film transistor has the advantages of a faster electron movement rate and the like, making it one of the new generation mainstream processes. However, to make a high-performance low-temperature polycrystalline silicon thin film transistor, one of the most difficult steps is to convert amorphous silicon (α-S i) into polycrystalline silicon (po! Y silicon, po1y-Si). · In the conventional technology, a solid phase crystallization method (sohd phase crystallization (SPC)) is generally used to convert an amorphous silicon layer on a glass substrate into a polycrystalline silicon layer at a temperature of about 60 (rc). See Figure 丨 A As shown in the figure, an amorphous stone layer 23 is deposited on the surface of a stone substrate 21 with the & buffer oxide layer 22 formed. Then, the amorphous silicon layer 23 is converted into a polycrystalline silicon layer 24 by a solid phase crystallization method. As shown in Figure 1B. However, the solid-phase crystallization method requires a very long process time (about 20-60 hours) to form a larger grain size, so it is not suitable for applications in industrial processes. In addition, the use of Polycrystalline silicon formed by solid-phase crystallization ^ has high-density in-grain defects, even more than one%

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584969 五、發明說明(2) 減低了低溫多晶矽薄膜電晶體的電性。 為了縮短製程的時間’目前工業界普遍使用準分子雷 射退火法(Excimer laser annealing, ELA)將非晶石夕層 轉換成多晶矽層,除了利用準分子雷射退火法取代固相結 晶法之外,其餘的製程步驟皆與圖1A及·圖1 B相同。然而, 由於準分子雷射退火法的結晶速率極高,使得所形成之晶 粒尺寸皆小於1 0 0 nm。此外,更由於雷射光束的重疊 (overlapping)現象以及脈衝與脈衝之間(pulse_t〇 — PUlse)的穩定度較i,使得再結晶之多晶石夕層的元件特性 發明人爰因於此 亟思一種可 方法」,幾 -,▼,一 奉於積極發明之精神 以解決上述問題之「薄膜電晶體之 經研究實驗終至完成此項嘉惠世人之發:製 (三)、【發明内容】 有於上述課題,本發 短、晶粒缺陷少 目的為棱供一種製程時間 製造方法。 疋、性一致的薄膜電晶體之多晶矽 本發明之特徵係利用 電晶體中之多晶矽層。 種二步驟退火方法來製造薄膜 緣是, 多晶石夕製造 沉積一第一 以形成一種 為達上述目 方法,包含 非晶>5夕層; 晶層;於種 的,依本發 下列步驟: 用一準分子 晶層上沉積 明之一種薄 提供一基板 雷射照射第 一第二非晶 膜電晶體之 ;於基板上 一非晶矽層 矽層;以及584969 V. Description of the invention (2) Reduced the electrical properties of low temperature polycrystalline silicon thin film transistors. In order to shorten the process time, excimer laser annealing (ELA) is widely used in the industry to convert the amorphous stone layer into a polycrystalline silicon layer, in addition to using the excimer laser annealing method instead of the solid-phase crystallization method. The rest of the process steps are the same as those in FIG. 1A and FIG. 1B. However, due to the extremely high crystallization rate of the excimer laser annealing method, the crystal grains formed are all smaller than 100 nm. In addition, due to the overlapping phenomenon of the laser beam and the stability between pulse and pulse (pulse_pulse_pulse) is higher than i, the inventor of the element characteristics of the recrystallized polycrystalline stone layer was in urgent need of this. "Think of a possible method", several-, ▼, a "thin film transistor research and experiment in the spirit of active invention to solve the above problems until the completion of this benefit of the world: system (three), [invention content In view of the above-mentioned problems, the purpose of the present invention is to produce a process with a short process time and few grain defects. 疋 Polycrystalline silicon with uniform thin film transistors. The feature of the present invention is to use a polycrystalline silicon layer in a transistor. Two steps The annealing method to manufacture the thin film edge is that polycrystalline stone is manufactured and deposited first to form a method for achieving the above purpose, including an amorphous layer, a crystal layer, and a seed layer. According to the present invention, the following steps are used: A thin layer deposited on the excimer crystal layer to provide a substrate laser to irradiate the first and second amorphous film transistors; an amorphous silicon layer silicon layer on the substrate; and

584969 五、發明說明(3) 進行爐管退火。 承上所述,本發明之一種薄膜電晶體之多晶矽層製造 方法係利用二步驟退火方法來製造薄膜電晶體中之多晶矽 層。與習知技術之固相結晶法相比,本發明減少了製程時 間,同時亦降低了晶粒内部的缺陷密度:另外,與習知技 術之準分子雷射法相比,利用本發明所形成之多晶矽薄膜 電晶體具有一致的元件特性,且同時多晶矽層擁有較大的 晶粒尺寸。詳細之比較如下表所示。 固相結晶法 準分子雷射法 本發明 元件特性一致性 較佳 較差 較佳 製程時間 較長 較短 較短 晶粒缺陷 高密度 低密度 低密度 晶粒尺寸 較大 較小 較大 為達上述目的,依本發明之一種薄膜電晶體之多晶矽 製造方法,包含下列步驟:提供一基板;於基板上沉積一 第一非晶矽層;用一準分子雷射照射第一非晶矽層以形成 一種晶層;於種晶層上沉積一第二非晶矽層;以及進行快584969 V. Description of the invention (3) Perform furnace tube annealing. As mentioned above, a method for manufacturing a polycrystalline silicon layer of a thin film transistor according to the present invention uses a two-step annealing method to manufacture a polycrystalline silicon layer in a thin film transistor. Compared with the conventional solid-phase crystallization method, the present invention reduces the process time and also reduces the defect density inside the crystal grains. In addition, compared with the conventional excimer laser method, the polycrystalline silicon formed by the present invention is used. Thin-film transistors have consistent device characteristics, and at the same time, polycrystalline silicon layers have larger grain sizes. The detailed comparison is shown in the table below. Solid-phase crystallization method Excimer laser method The device of the present invention has better uniformity and poorer performance. The process time is longer. Shorter and shorter. Grain defects. High density. Low density. Low density. According to the present invention, a thin-film transistor polycrystalline silicon manufacturing method includes the following steps: providing a substrate; depositing a first amorphous silicon layer on the substrate; irradiating the first amorphous silicon layer with an excimer laser to form a Crystal layer; depositing a second amorphous silicon layer on the seed layer; and

584969584969

速熱製程(RTP )退火。 元件:ΐ上述杜i;明之薄膜電晶體之多晶石夕製造方法- 下,择A ^ 、 一致性以及產品生產力之間的考量 係為目刖工業應用上之最佳選擇。 (四)、【實施方式】 以下將參照相關圖式, 膜電晶體之多晶矽製造方法 參照符號加以說明。 說明依本發明較佳實施例之薄 ’其中相同的元件將以相同的 ^圖2所示,依據本發明第一實施例之一種薄膜電晶體 夕曰日矽製造方法,包含下列步驟:提供一基板(s〇丨); 2 f板上沉積一第一非晶矽層(S0 2 );用-準分子雷射照 非晶矽層以形成一種晶層(s〇3);於種晶層上沉積 一第二非晶矽層(s〇4 );以及進行爐管退火(S05 )。 如圖3A所示,於步驟SOI中係提供一基板丨丨。在此,基 板1 1係可為一矽基板或一玻璃基板。於本實施例中,基板& 11上形成有一緩衝氧化層(Buffer 〇xide丨ayerH2,其 係利用加熱氧化法生成於基板丨丨的表面上,此緩衝氧化層 1 2係用以提昇之後欲沉積材料對基板丨1表面的附著能力。 接著,如圖3B所示,在步驟S 02中,於基板11上沉積一 第一非晶矽層1 3。於本實施例中,係以s i H4 (矽甲烷)為反 應氣體,於溫度約5 5 0 °C的環境下以低壓化學氣相沉積法 (Low Pressure Chemical Vapor Deposition,LPCVD)沈積 第一非晶矽層1 3。以低壓化學氣相沉積法沈積的第一非晶Rapid thermal process (RTP) annealing. Components: The above-mentioned manufacturing method of polycrystalline stones for thin film transistors is described below. The choice between A ^, consistency and product productivity is the best choice for industrial applications. (IV) [Embodiment] Hereinafter, a method for manufacturing a polycrystalline silicon of a film transistor will be described with reference to related drawings and symbols. A thin film according to a preferred embodiment of the present invention will be described in which the same elements will be shown in the same figure. FIG. 2 shows a method for manufacturing a thin film transistor according to the first embodiment of the present invention. A substrate (s〇 丨); a first amorphous silicon layer (S0 2) is deposited on the 2 f plate; the amorphous silicon layer is irradiated with an excimer laser to form a crystal layer (s〇3); on the seed layer A second amorphous silicon layer is deposited thereon (s04); and furnace tube annealing is performed (S05). As shown in FIG. 3A, a substrate is provided in step SOI. Here, the substrate 11 may be a silicon substrate or a glass substrate. In this embodiment, a buffer oxide layer (Buffer OXide 丨 ayerH2) is formed on the substrate & 11, which is generated on the surface of the substrate 丨 using a thermal oxidation method. Adhesion of the deposition material to the surface of the substrate 1. Next, as shown in FIG. 3B, in step S 02, a first amorphous silicon layer 13 is deposited on the substrate 11. In this embodiment, si H4 is used. (Silicon methane) is a reactive gas, and the first amorphous silicon layer 13 is deposited by a low pressure chemical vapor deposition (LPCVD) method at a temperature of about 5 50 ° C. A low pressure chemical vapor phase is used. First amorphous

584969 五、發明說明(5) 矽層1 3有較佳的步階覆蓋能力,且第一非晶矽層丨3的均勻 佳、純度高。於此,第一非晶石夕層1 3的厚度約為6奈米 (nm )到1 2奈米。 另外,於步驟S03中,係以一準分子雷射照射第一非晶 石夕層13 ’用以形成一種晶層(Seed lay §r) 14,如圖3C所 示。於本實施例中,係於室溫且接近真空(〜1〇_3 t〇rr ) 的環境中,以氟化氪(KrF )準分子雷射(雷射強度為12〇 m J / c m2 )照射第一非晶矽層1 3,使其轉換成一種晶層丨4。 其中’準分子雷射的波長為248nm、脈衝維持時間為丨5ns以 及重複速度為1 OHz。另外,準分子雷射亦可以用氟化氬584969 V. Description of the invention (5) The silicon layer 13 has better step coverage ability, and the first amorphous silicon layer 3 has good uniformity and high purity. Here, the thickness of the first amorphous stone layer 13 is about 6 nanometers (nm) to 12 nanometers. In addition, in step S03, the first amorphous stone layer 13 'is irradiated with an excimer laser to form a seed layer (Seed lay §r) 14, as shown in FIG. 3C. In this embodiment, it is at room temperature and close to vacuum (~ 10_3 t〇rr), using erbium fluoride (KrF) excimer laser (laser intensity is 12m J / c m2 ) The first amorphous silicon layer 13 is irradiated to convert it into a crystalline layer 4. Among them, the excimer laser has a wavelength of 248 nm, a pulse sustaining time of 5 ns, and a repetition rate of 1 OHz. In addition, excimer laser can also use argon fluoride

UrF)雷射或是氣化氙(XeC1 )雷射。於此,種晶層“之 係為多晶碎結構。 曰功來,在步驟304中,係於種晶層14上沉積一第二非 日日矽層15,如圖3D所示。其中,第二非晶矽層15的,,冗錄方 法係與第一非曰石々爲彳Q 4门 开日日/續1 ΰ的/儿積方 中,第非曰::/相同,於此不再贅述。於本實施例 第一;:;石夕層13係較第二非晶石夕層15薄。 步驟传將第如:3ΒΕ所不’於步驟so5中,進行爐管退火’此 例中,係於溫度550,0 tJ_充成^多晶石夕層16。於本實施 方式(約2到24小時)、隹/充滿虱氣的環境中以爐管退火 多晶矽層1 6。 進订結晶,使第二非晶矽層1 5轉換成 再來,於形成夕曰 化以形成複數個獨:::2 16之後’係將多晶矽層1 6圖案 動元件區域。接著,於溫度約為UrF) laser or vaporized xenon (XeC1) laser. Here, the seed layer is a polycrystalline fragment structure. In step 304, a second non-Japanese silicon layer 15 is deposited on the seed layer 14, as shown in FIG. 3D. Among them, The method of redundant recording of the second amorphous silicon layer 15 is the same as that of the first non-Japanese stone 々Q 4 door opening day / continued 1 // 儿 product formula, the second non-Japanese :: /, here No further details. In the first embodiment of this embodiment ::; Shi Xi layer 13 is thinner than the second amorphous Shi Xi layer 15. Steps will be as follows: 3 ΒΕ 'in step so5, the furnace tube annealing is performed. In the example, the polycrystalline silicon layer 16 is charged at a temperature of 550,0 tJ_. The polycrystalline silicon layer 16 is annealed in a furnace tube in an environment where the present embodiment (about 2 to 24 hours) is filled with lice / gas. The crystal is ordered to convert the second amorphous silicon layer 15 to come again, and then formed to form a plurality of unique ::: 2 16 after '16 is a pattern of the polycrystalline silicon layer 16 moving element region. Then, at temperature About

第8頁 584969 30 0 °C的環境下以電漿輔助化學氣相沉積法(piasmaPage 8 584969 Plasma-assisted chemical vapor deposition (piasma) at 30 ° C

Enhanced Chemical Vapor Deposition,PECVD)沉積一厚 度約為120奈米的TE OS-oxide當作閘極絕緣層。接著,沉積 一層厚度約為200奈米的多晶矽層,並且圖案化使其形成元 件閘極。接著,·形成源極/汲極與閘極區。接下來,於充滿 氮氣且溫度6 0 0 °C的環境下進行2小時活化佈植退火步驟。 再來’於溫度300 C的環境下沉積一厚度約5〇〇奈米的pe 一 TEOS oxide以形成保護膜。最後,將周邊之電極接合端子 部分露出,以形成低溫製作多晶矽薄膜電晶體。 於本實施例中,係利用準分子雷射照射第一非晶矽層 使其形成種晶層,由於種晶層具有極佳的結晶中心,使得 接下來之結晶晶粒成長時具有低密度的晶粒内部缺陷。再 來’由於爐管退火步驟只包含結晶晶粒成長所需的時間, 使彳于整個退火製成時間大大的縮短。且,由於晶粒成長機 構與固相結晶法相似,使得本實施例所產生之多晶矽薄膜 電晶體的元件特性有較佳的一致性。 如圖4所示,依據本發明第二實施例之一種薄膜電晶體 之多晶矽製造方法,包含下列步驟:提供一基板(sn ); 於基板上沉積一第一非晶石夕層(S1 2 );用一準分子雷射照 =第一非晶矽層以形成一種晶層(S1 3 );於種晶層上沉積 一第二非晶矽層(S1 4 );以及進行快速埶製程退火 (S15 )。 上述本發明第二實施例之一種薄膜電晶體之多晶矽製 ^方去’其中步驟S11〜s 1 4係與圖2所示之步驟s 〇 1〜s 〇 4相Enhanced Chemical Vapor Deposition (PECVD) deposits a TE OS-oxide with a thickness of about 120 nm as the gate insulating layer. Next, a polycrystalline silicon layer with a thickness of about 200 nm is deposited and patterned to form a component gate. Then, a source / drain and a gate region are formed. Next, an activation implantation annealing step was performed in an environment filled with nitrogen at a temperature of 600 ° C for 2 hours. Then again, a TEOS oxide with a thickness of about 500 nm is deposited at a temperature of 300 ° C to form a protective film. Finally, the peripheral electrode bonding terminals are partially exposed to form a low-temperature polycrystalline silicon thin film transistor. In this embodiment, the first amorphous silicon layer is irradiated with an excimer laser to form a seed layer. Since the seed layer has an excellent crystal center, the subsequent crystal grains have a low-density Internal grain defects. Furthermore, since the annealing step of the furnace tube only includes the time required for crystal grain growth, the whole annealing time is greatly shortened. Moreover, since the grain growth mechanism is similar to the solid phase crystallization method, the device characteristics of the polycrystalline silicon thin film transistor produced in this embodiment have better consistency. As shown in FIG. 4, a method for manufacturing polycrystalline silicon of a thin film transistor according to a second embodiment of the present invention includes the following steps: providing a substrate (sn); and depositing a first amorphous stone layer (S1 2) on the substrate Using an excimer laser = the first amorphous silicon layer to form a crystal layer (S1 3); depositing a second amorphous silicon layer (S1 4) on the seed layer; and performing a rapid annealing process ( S15). The thin film transistor made of polycrystalline silicon according to the second embodiment of the present invention is described above, wherein steps S11 to s 1 4 are the same as steps s 〇 1 to s 〇 4 shown in FIG. 2.

第9頁 584969 五、發明說明(7) 同’而於步驟S1 5中,進行快速熱製程退火,此步驟同樣係 將第二非晶石夕層1 5轉換成一多晶石夕層1 6。於本實施例中, 係於溫度600〜750 °C且充滿氮氣的環境中以快速熱製程退火 方式(約1 2 0到3 0秒)進行結晶,使第二非晶矽層1 5轉換成 多晶矽層1 6。Page 9 584969 V. Description of the invention (7) Same as in step S15, the rapid thermal process annealing is performed. This step is also to convert the second amorphous stone layer 15 to a polycrystalline stone layer 1 6 . In the present embodiment, the second amorphous silicon layer 15 is converted into crystals by rapid thermal process annealing (approximately 120 to 30 seconds) in an environment filled with nitrogen at a temperature of 600 to 750 ° C, so that the second amorphous silicon layer 15 is converted into Polycrystalline silicon layer 1 6.

本發明之一種薄膜電晶體之多晶矽製造方法係利用二 少驟退火方法來製造薄膜電晶體中之多晶矽層。與習知技 術之固相結晶法相比,本發明減少了製程時間,同時亦降 低了晶粒内部的缺陷密度。另外,與習知技術之準分子雷 射法相比’利用本發明所形成之多晶矽薄膜電晶體具有一 致的元件特性’且同時多晶矽層擁有較大的晶粒尺寸。總 括上述,本發明之薄膜電晶體之多晶矽製造方法在元件效 能、元件特性一致性以及產品生產力之間的考量下,係為 目前工業應用上最佳的選擇。 以上所述僅為舉例性,而非為限制性者。任何未脫離 本發明之精神與範疇,而對其進行之等效修改或變更,均 應包含於後附之申請專利範圍中。A method for manufacturing polycrystalline silicon of a thin film transistor according to the present invention is to manufacture a polycrystalline silicon layer in a thin film transistor by using a two-step annealing method. Compared with the solid phase crystallization method of the prior art, the present invention reduces the process time, and also reduces the defect density inside the crystal grains. In addition, compared with the conventional excimer laser method, 'the polycrystalline silicon thin film transistor formed by using the present invention has consistent device characteristics' and the polycrystalline silicon layer has a larger grain size. In summary, the polycrystalline silicon manufacturing method of the thin film transistor of the present invention is the best choice for current industrial applications under consideration of element performance, consistency of element characteristics, and product productivity. The above description is exemplary only, and not restrictive. Any equivalent modification or change made without departing from the spirit and scope of the present invention shall be included in the scope of the attached patent application.

第10頁 584969 圖式簡單說明 (五)、【圖式簡單說明】 圖1 A及圖1 B係為習知薄膜電晶體之多晶矽製造方法的 實施示意圖; 圖2係為第一實施例中薄膜電晶體之多晶矽製造方法的 方塊圖; 圖3A至圖3E係為第一實施例中薄膜電晶體之多晶矽製 造方法的實施示意圖;以及 圖4係為第二實施例中薄膜電晶體之多晶矽製造方法的 方塊圖。Page 10 584969 Brief description of the drawings (five), [Simplified description of the drawings] Figures 1 A and 1 B are schematic diagrams of a method for manufacturing a conventional polycrystalline silicon manufacturing method of a thin film transistor; Figure 2 is a thin film of the first embodiment A block diagram of a polycrystalline silicon manufacturing method for a transistor; FIGS. 3A to 3E are schematic diagrams of a polycrystalline silicon manufacturing method for a thin film transistor in the first embodiment; and FIG. 4 is a polycrystalline silicon manufacturing method for a thin film transistor in the second embodiment. Block diagram.

元件符號說明: 11 基板 12 緩衝氧化層 13 第一非晶石夕層 14 種晶層 15 第二非晶矽層 1 6 多晶矽層 SOI 提供一基板Description of component symbols: 11 substrate 12 buffer oxide layer 13 first amorphous stone layer 14 crystal layers 15 second amorphous silicon layer 1 6 polycrystalline silicon layer SOI provides a substrate

S 0 2 於基板上沉積一第一非晶石夕層 503 用一準分子雷射照射第一非晶矽層以形成一種晶層 504 於種晶層上沉積一第二非晶矽層 505 進行爐管退火 S1 1 提供一基板 S1 2 於基板上沉積一第一非晶矽層S 0 2 deposit a first amorphous stone layer 503 on the substrate and irradiate the first amorphous silicon layer with an excimer laser to form a crystal layer 504 deposit a second amorphous silicon layer 505 on the seed layer Furnace tube annealing S1 1 provides a substrate S1 2 to deposit a first amorphous silicon layer on the substrate

第11頁 584969Page 11 584969

第12頁Page 12

Claims (1)

584969 六、申請專利範圍 1、一種薄膜電晶體之多晶矽製造方法,包含·· 提供一基板; 於該基板上沉積一第—非晶矽層; 用一準分子雷射照射該第一非晶矽層以形成一種晶層; 於該種晶層上沉積一第二非晶矽層;以及 進行爐管退火。 晶矽製造 2、如申請專利範圍第丨項所述之薄膜電晶體 方法,更包含: 夕 層 於提供該基板之後,在該基板上形成一緩衝氧化 3方去如申::利範®第1項所述之薄膜電晶Μ之多晶矽製造 方法,/、中該基板係包括矽基板或玻璃基板。 方法,其中該第一非 :申犯圍第1項所述之薄膜電晶體之多晶石夕製造 曰曰石夕層係較該第二非晶矽層薄 5、 如申請專利範圍第1 方法,其中該第一非晶』薄膜電晶體之多晶石夕製造 夕層的厚度為約6奈米到1 2奈米。 6、 如申請專利範圍第1 方法,其中該第二非晶石夕;;,薄膜電晶體之多晶石夕製造 米 B的厚度為約30奈米到150奈 體之多晶碎製造 、如申請專利範圍第1項所述之薄膜電晶584969 VI. Application Patent Scope 1. A method for manufacturing polycrystalline silicon of a thin film transistor, comprising: providing a substrate; depositing a first-amorphous silicon layer on the substrate; irradiating the first amorphous silicon with an excimer laser Layer to form a crystal layer; depositing a second amorphous silicon layer on the seed layer; and performing furnace tube annealing. Silicon silicon manufacturing 2. The thin film transistor method described in item 丨 of the patent application scope, further comprising: after the layer is provided, a buffer oxide 3 is formed on the substrate as claimed :: Lifan® 1 The method for manufacturing polycrystalline silicon of the thin film transistor M described in the item, wherein the substrate includes a silicon substrate or a glass substrate. Method, wherein the first non-: polycrystalline stone manufacturing of the thin film transistor described in item 1 of claim 1 is a thinner layer than the second amorphous silicon layer. The thickness of the polycrystalline layer of the first amorphous thin film transistor is about 6 nm to 12 nm. 6. For example, the first method in the scope of patent application, wherein the second amorphous stone is made of polycrystalline stone of thin film transistor, and the thickness of B is about 30 nm to 150 nm, and the polycrystalline powder is made, such as Thin film transistor as described in the first patent application 第13頁 584969 六、申請專利範圍 ""' '_ " -------一· 方法,其中該準分子雷射係為氟化氪雷射。 如申β月專利範圍第i項所述之薄膜電晶體之造 方法,其中該準分子雷射係為氟化氬雷射。 9如申清專利範圍第1項所述之薄膜電晶體之多晶矽製造 法’其中該準分子雷射係為氯化氙雷射。 1 0、、如申請專利範圍第1項所述之薄膜電晶體之多晶矽製造 方法’其中爐管退火的溫度為約550〜60()。〇。 11、一種薄膜電晶體之多晶矽製造方法,包含: 提供一基板; 於該基板上沉積一第一非晶矽層; 用一準分子雷射照射該第一非晶矽層以形成一種晶層; 於該種晶層上沉積一第二非晶矽層;以及 進行快速熱製程退火。 1 2、如申請專利範圍第丨丨項所述之薄膜電晶體之多聶矽製 造方法,更包含: 於提供該基板之後,在該基板上形成一緩衝氧化層。 1 3、如申請專利範圍第11項所述之薄膜電晶體之多晶矽製 造方法,其中該基板係包括矽基板或玻璃基板。Page 13 584969 VI. Scope of patent application " " '' _ " ------- A method, in which the excimer laser is a fluorinated hafnium laser. The thin-film transistor manufacturing method as described in item i of the patent application for the month of β, wherein the excimer laser is an argon fluoride laser. 9 The method for manufacturing a polycrystalline silicon of a thin film transistor as described in item 1 of the patent application scope, wherein the excimer laser is a xenon chloride laser. 10. The method for manufacturing polycrystalline silicon of a thin film transistor as described in item 1 of the scope of the patent application, wherein the temperature of the furnace tube annealing is about 550 to 60 (). 〇. 11. A method for manufacturing polycrystalline silicon of a thin film transistor, comprising: providing a substrate; depositing a first amorphous silicon layer on the substrate; irradiating the first amorphous silicon layer with an excimer laser to form a crystalline layer; Depositing a second amorphous silicon layer on the seed layer; and performing rapid thermal process annealing. 1 2. The method for manufacturing a thin film transistor as described in item 丨 丨 of the patent application scope further comprises: after providing the substrate, forming a buffer oxide layer on the substrate. 1 3. The method for manufacturing polycrystalline silicon of the thin film transistor according to item 11 of the scope of the patent application, wherein the substrate comprises a silicon substrate or a glass substrate. 申π專利範圍第丨丨項所述之薄 造方法,纟中該第溥膜電曰曰體之多晶矽製 第非日日矽層係較該第二非晶矽層薄。 15、如申請專利範圍第丨丨 造方法,其中哕笛 《溥膜·電晶體之多晶矽製 Μ第一非s曰矽層的厚度為約6奈米到12奈来。 ^、如申請專利範圍第11項所述之薄膜電曰體之夕曰㈣ 造方法,盆申兮始 碑膜笔日日體之多晶矽製 米。,、中該第二非晶石夕層的厚度為約30奈米到15〇奈 U方Ϊ申Ϊ Ϊ : Ϊ圍第11項所述之薄獏電晶體之多晶矽製 σΛ準分子雷射係為氟化氣雷射。 ^古t申:ί利範圍第1 1項所述之薄《電晶體之多晶矽製 /、 邊準分子雷射係為氟化氩雷射。 U 士 t申:專利範圍第1 1項所述之薄^電晶體之多晶矽製 ^彳’,、中該準分子雷射係為氣化氙雷射。 2 0、如申请專利範圍第11項所述之薄膜電晶體之多晶石夕製 造方法,其中快速熱製程退火的溫度為約6 〇 〇〜7 5 〇 °c。The thin-film manufacturing method described in item π of the patent scope, wherein the first non-Japanese silicon layer made of polycrystalline silicon is thinner than the second amorphous silicon layer. 15. According to the patent application method, the thickness of the first silicon layer is about 6 nanometers to 12 nanometers. ^ As described in the eleventh chapter of the patent application, the method of making thin-film electric body is made of polycrystalline silicon rice. The thickness of the second amorphous stone layer is about 30 nanometers to 15 nanometers. Ϊ: σΛ excimer laser system made of polycrystalline silicon made of thin crystalline silicon as described in item 11 above. It is a fluorinated gas laser. ^ Gu Tshen: The thin "transistor made of polycrystalline silicon /," and the excimer laser system described in item 11 of the scope of interest are argon fluoride lasers. U.S. Application: Thin-transistor polycrystalline silicon made of polycrystalline silicon as described in item 11 of the patent, where the excimer laser is a vaporized xenon laser. 20. The method for manufacturing a polycrystalline silicon thin film transistor as described in item 11 of the scope of patent application, wherein the annealing temperature in the rapid thermal process is about 600-750 ° C. 第15頁Page 15
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