TW584952B - Power supply clamp circuit - Google Patents

Abstract

A power supply clamp circuit for preventing damage on an integrated circuit due to electrostatic discharge on a first voltage source of the integrated circuit. The power supply clamp circuit contains a voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electrically connected to the first voltage source, a gate electrically connected to the first node, and a drain electrically connected to a second node; a first NMOS transistor having a drain electrically connected to the second node, a gate electrically connected to the first node, and a source connected to ground; a second NMOS transistor having a drain electrically connected to the first voltage source, a gate electrically connected to the second node, and a source connected to ground; and a second PMOS transistor having a source electrically connected to the second node, a gate and a drain commonly electrically connected to the first node.

Description

584952 Description of the invention (l) Technical field of the invention $ The invention provides a power supply clamping circuit, especially a power supply clamping circuit capable of a bias control mechanism that is ideal for a driver. Prior art

… Integrated Circuit has the advantages of small size and ffnan, so it is very suitable for the application of circuits with complexity and south integration such as microprocessors and memory, and these use semiconductors to make private ( Semiconductor Manufacturing Process)% of integrated circuits has also become the mainstream of large-scale circuit design and manufacturing. However, compared to the traditional discrete circuit, the integrated circuit presents a very serious problem, that is, it is very vulnerable to internal damage caused by external electrostatic discharge (ESD), which is due to the The size of each element in the body circuit and the distance between components have been greatly reduced, which makes it easier to generate excessive pulses when electrostatic discharge occurs and increase the possibility of damage. This is due to the damage caused by electrostatic discharge. The situation that the component size is shrinking with the progress of process technology is becoming more serious. θ

Usually, the electrostatic discharge phenomenon occurs when an electric carrier (for example, a finger carrying a charge) stores a large amount of static electricity and contacts an integrated circuit.

584952 V. Description of Invention (2)

At the same time, the contact of the integrated circuit is a technology that passes through the grounding terminal to generate a component to promote the circuit of the electrostatic discharge circuit. The carrier power supply path to the contact is the damaged integrated circuit. The f charge on the path generally enters through two kinds of paths. One is to enter the integrated circuit through the signal terminal, that is, the path (Pin-to-Pin Route), and the second opposite end carries the integrated circuit. So-called power to Powei-to-Ground Route). Generally, the degree to which the integrated circuit can withstand the electrostatic discharge phenomenon is generally called the ESD level (ESD Level). It is the ESD level of the road. The conventional technology usually sets a clamping circuit between the possible endpoints (Clamp Please Please refer to FIG. 1. FIG. 1 shows a schematic circuit diagram of a power supply clamp circuit 10 connected to a ground of a first voltage source pa in the conventional art. The power supply clamp circuit 10 includes a first A PM0S transistor 12 whose source is electrically connected to a first voltage source P! 'Its gate is electrically connected to a first node N 1 and its drain is electrically connected to a second node Nr-the first NMOS transistor 14. Its drain is electrically connected to the first node N 2 ′, its gate is electrically connected to the first node ni, its source is grounded, and a second NMOS transistor 16 is connected to its first voltage. A source ρ, whose gate is electrically connected to the second node N 2 and whose source is grounded; a resistor 18 whose one end is electrically connected to the first voltage source Pi, and whose other end is electrically connected to the first node NJ and a capacitor 20, one end of which is electrically connected to the first node Nι, and the other Ground. ^

584952 V. Description of the invention (3) In Figure 1, the combination of resistor 18 and capacitor 20 can be regarded as a voltage generator in function. The voltage generator will generate a voltage at the second node N & The voltage is a pair of electrostatic discharge phenomena with sensitivity, C ESD Sensitive) value, that is, the voltage will be different in the normal operating condition of the integrated circuit and the condition where the electrostatic discharge occurs. The electrostatic discharge phenomenon is a phenomenon in which a large amount of charge is discharged to & a voltage source p, so it will cause a rising pulse = often rapid voltage pulse at the first voltage source P. Specifically, when the first voltage source p When it is turned on under forward operation, its voltage value will rise at a relatively slow speed. For example, it will take several microseconds (" s) or even milliseconds (ms) to increase from 0V to the preset 3 · 3V. However, when an electrostatic discharge occurs, the time that the first voltage source rises from 0v to 3.3V due to the generation of a voltage pulse may only take a few nanoseconds (ns). The voltage generator composed of the resistor 18 and the capacitor 20 described above will generate the voltage according to different voltage rising speeds. As is widely known to those skilled in the art, the function of resistor 18 and capacitor 20 is a low-pass filter (Low-Pass F i 1 ter). When the first voltage source P is turned on under normal operation, Because its voltage value will rise at a slower rate, the voltage at the first node N & will rise synchronously with the voltage value of the first voltage source. However, when an electrostatic discharge occurs, the voltage value of the first voltage source p & rises at a very fast speed. At this time, due to the effect of the low-pass filter, the voltage value of the first voltage source P 1 starts to rise. For a short period of time, this voltage will not be fully reversed.

584952 V. Description of the invention (4) Value] The rising speed is such that there is a significant voltage difference between the first voltage source P and the first node L center within a short period of time between the -th voltage source. The voltage generator composed of the above and the capacitor 20 has the first and second voltage sources—after the voltage source p is turned on under normal operation, it will not rise: the voltage between the voltage source and the first voltage source is 1 9 :% / Field voltage difference, that is, the voltage difference between the first PM0S source and the M source (that is, the first voltage source P1) and the gate (that is, the first node I) ίVsppi = 〇V And the first PM0S transistor 12 is in the off state during the W ^ rising process, until the first node 11 is raised to the size that can turn on the first NMOS transistor 14 = the voltage value of the private second node N It will drop to the ground voltage because of I of the first NMOS transistor 14, so that the second NMOS transistor 16 will be kept in an off state, so that the first voltage source p 丨 can exert its original circuit provided by the integrated circuit. The function of the power supply voltage. When the first voltage source P generates a fast rising voltage pulse due to the occurrence of the electrostatic discharge phenomenon, the first node N and the first voltage source P will be as described above. The voltage difference is generated by the action of the low-pass filter, that is, the first The voltage difference V SPP between the source of the PM0S transistor 12 (that is, the first voltage source P 1) and the gate (that is, the first node N 0) is greater than 0V, so that the first PM0S transistor 12 enters the on state. When the first PM0S transistor 12 is turned on, the voltage value of N 矣 at the second node will be

IIM Page 10 584952 V. Description of the invention (5) A voltage source P is pulled high to the extent that the second NMOS transistor 6 enters an on state. Through the above action, the power supply clamping circuit is provided with a current path from the first voltage source p to the ground terminal by turning on the first N M 0 S electric body 16, so that the first A voltage source P < voltage pulse can discharge the ground terminal through this path without causing damage to the internal circuit of the integrated circuit. Please note that in order to improve the ESD level of the power supply clamping circuit, the second NMOS transistor 16 is usually designed as a larger transistor. However, the ESD level of the power supply clamp circuit 10 is strongly related to the gate bias of the second NMOS transistor 16. This is the so-called Gate Bias Effect, which means When the first PMOS transistor 12 enters the on state and the second NMOS transistor i 6 also enters the on state, the gate of the second NMOS transistor 16 (that is, the second node N 2 > bias must be Only within a proper voltage range can the ESD level of the power supply clamping circuit 10 be maintained at the optimal state. If the gate bias of the second NMOS transistor 16 is too high or too low, both Will greatly reduce the ESD level of the power supply clamping circuit 10. Therefore, in order to control the gate bias voltage of the second NMOS transistor 16 within an appropriate voltage range, the circuit designer must design the power supply clamping circuit 丨 〇 At the same time, the element parameters such as the gate length and width of the first PMOS transistor 12 and the first NMOS transistor 14 are controlled very finely, thereby increasing the time and labor cost of circuit design.

Page 11 584952

V. Description of the invention (6) Summary of the invention This invention can provide a rationale to solve the above problem. Therefore, the main purpose of the present invention is to provide a desired bias control mechanism for the power supply clamping problem. The clamping circuit according to the patent application of the present invention is used to prevent an integrated circuit from discharging and causing the integrated circuit to include a voltage generator electrically connected to a voltage; a first PMOS transistor voltage source whose gate is electrically connected to The second node; a first NMOS transistor node, the gate of which is electrically connected to the first N M0S transistor; its non-pole electrode is electrically connected to the second node, its source crystal, its source The pole is electrically connected to the first electrical connection to the first node. The range 'discloses that a first voltage source of a power supply circuit is statically damaged.' The power supply clamping circuit is connected to a first node for generation, and its source is electrically connected to the first electrical node and its drain Electrically connected in one, its drain is electrically connected to the second node, its source is grounded; a first is connected to the first voltage source, its gate is grounded; and a second PMOS electrical two node, its gate and Drain

# 要 本 ί 明 The power supply clamping circuit is used for the first node and

〃: That is, the design of the second PM0S «crystal is added to the Ξ: Ξ 5 Ϊ limit, f within the desired voltage range, so that the aforementioned 'Ancient E ° SD level and those to maintain the power supply clamp The circuit adjustment process is simplified, and

Page 12

584952 V. Description of the invention (7) The design cost is reduced. Embodiment Please refer to FIG. 2. FIG. 2 shows a schematic circuit diagram of a power supply clamping circuit 30 electrically connected between a first voltage source P and a ground terminal according to the present invention. The power supply circuit 30 includes a first PMO S transistor 32, whose source is electrically connected to the first voltage source P1, whose gate is electrically connected to a first node ^, and whose drain is electrically connected to a second A node-first NMOS transistor 34 ′ is electrically connected to the second node Nr and its gate is electrically connected to the first node ^, and its source is grounded; a second nMOS transistor 36 is electrically connected to the anode At the first voltage source Pi, its gate is electrically connected to the second node N2, and its source is grounded; a resistor 38, one end of which is electrically connected to the first voltage source Pi, and the other end of which is electrically connected to the first node N1; Capacitor 40, one end of which is electrically connected to the second end: point Nl, and the other end of which is grounded; and a second PM0S electrical crystal connection: the pole is electrically connected to the second node Nz, and its gate and non-pole are electrically connected to The capacity of one node NΓ is the same as that of the conventional technology. In Figure 2, the resistor 38 and the electric generator can also be used. The second is a voltage generator. This voltage generates a voltage on the static first node. 'The voltage is the value of a circuit positive & electrical phenomenon has a sensitive X, that is, the voltage working in the same body as the voltage Under the circumstances and the situation where electric discharge occurs, there will be no Μ. When the first voltage source is turned on under normal operation, due to

The 13th stomach 584952 V. Description of the invention (8) The voltage value will increase at a slower speed, so the voltage at the first node n i will rise synchronously with the voltage value of the first voltage source. However, when an electrostatic discharge occurs, the voltage value of the first voltage source P rises at a very rapid rate. At this time, due to the role of the voltage generator, the voltage value of the first voltage source PA starts to rise for a short time. The voltage will not fully reflect the rising speed of this voltage value, so that a significant voltage difference will be generated between the first voltage source P 1 and the first node NA within a short period of time when the voltage value of the first voltage source PA starts to rise. In addition, the capacitor 40 shown in Figure 2 is an integrated circuit capacitor formed by connecting a transistor and a source to the source. This technology is also widely known to those skilled in the art. Next, the operation principle of the power supply clamp circuit 30 of the present invention will be described in detail. When the first voltage source P is turned on under normal operation, the first node NA and the first voltage source P must not have a voltage difference during the voltage rise of the first voltage source P < that is, the first PMOS The voltage difference between the source (ie, the first voltage source P 1) and the gate (ie, the first node N) of the transistor 32 is V sppi = 〇V, so that the first PMOS transistor 32 is at the entire voltage. During the rising process, they are all in the off state. After the voltage value of the first node N rises to a level that can turn on the first NMOS transistor 34, the voltage value of the second node N 妁 will decrease because the first NMOS transistor 34 is turned on. To the ground voltage, in this way, the second NMOS transistor 36 will always be kept in the off state, so that the first voltage source P can perform its function of providing the power supply voltage of the integrated circuit. Please note that at this time, the

Page 14 584952

The ground voltage of the source (ie, the second node Nz) of the two PMOS transistors 42 and the voltage value of its gate (ie, the first node No) are the same as those of the first voltage source P, so that the source of the second PMOS transistor 42 The pressure difference between the poles and the poles: S: gas, two negative values, and the second P_transistor 42 is in a closed state. 'It may not cause any shadow to the power supply clamping circuit 3. And when the first When the voltage source Pi generates a rapidly rising voltage pulse due to the occurrence of the electrostatic discharge phenomenon, the voltage difference between the first node N < and the first voltage source p & as described above, that is, the first pM 〇s transistor 32 source (that is, the first voltage source p 〇 and the gate (that is, the voltage difference between the first node nj VSPP is greater than 0v), so that the first pMOS transistor 32 enters the on state After the first PMOS transistor 32 is turned on, the voltage value of the second node N2 will be pulled up by the first voltage source P to the extent that the second NMOS transistor 36 is turned on. Through the above-mentioned action, the power supply The supply clamp circuit 30 provides the voltage from the first voltage source P to the ground terminal by turning on the second NMOS transistor 36. The flow path, so that the first voltage source P & voltage pulse can discharge the ground terminal through this path due to the electrostatic discharge phenomenon, without causing damage to the internal circuit of the integrated circuit. Please note that at this time because The source of the second PMOS transistor 42 (that is, the voltage value of the second node N 2> is the same as that of the first voltage source p and its gate (that is, the voltage value of the first node N 0 has a voltage difference from the first voltage source p). , So that the voltage difference VSPP between the source and the gate of the second PMOS transistor 42 is a positive value, and the second PMOS transistor 42 is turned on. Therefore, the first and second PMOS transistor 32, The interaction of 42 makes the second quarter

584952 V. Description of the invention (10) " Point N & Voltage can be automatically adjusted to the desired voltage range. Please note that in order to improve the esd of the power supply clamping circuit 30, the second NMOS transistor 36 is usually designed as a larger-sized transistor, or a higher concentration of p + -type ions is implanted on its drain during the manufacturing process. , 'To increase the discharge capacity of the current path. ′ Please refer to FIG. 3, which shows a schematic circuit diagram of another power supply clamping circuit 50 between the first voltage source P and the ground terminal according to the present invention. The power supply clamping circuit 50 is very similar to the conventional power supply clamping circuit 10, so it is not necessary to repeat the description. However, the difference is that, in addition to the first voltage source, the integrated circuit here includes a second voltage source P that is independent of the first voltage source P but has the same voltage value (for example, the same is 3 · 3 V). The voltage source p 2, that is, when the first voltage source P and the electrostatic discharge phenomenon generate a voltage pulse that rises rapidly, the same phenomenon does not occur in the second voltage source P. Therefore, the power supply clamping circuit 50 can make use of this characteristic by using the resistor 58 shown in FIG. 3, the third P MOS transistor 6 0, and the third n Μ 0 S transistor 62. A voltage generator 'achieves the same function as the voltage generating Is composed of the resistor 18 and the capacitor 20 as shown in FIG. One end of the resistor 58 is electrically connected to the second voltage source ρ2, and the other end is electrically connected to a third node N3; the source of the third PMOS transistor 60 is electrically connected to the third node N3, and the gate is electrically connected At a fourth node N. Its drain is electrically connected to the first node N !; and the drain and gate of the third NM 0S transistor 6 2 are electrically connected.

Page 16 584952 V. Description of the invention (11) At the fourth node N 4, its source is grounded. Please note that because the third NMOS transistor 62 is connected in a diode configuration (Diode Connected), it will be in the on state and pull the N-node voltage value of the fourth node to the ground voltage, so the third pM〇s The transistor 60 will also be in the on state and set the first node n < voltage value to be the same as the second voltage source P.

Next, the operation principle of the power supply clamp circuit 50 of the present invention will be described in detail. When the first voltage source p and the second voltage source p are turned on under normal operation, 'Because the first and second voltage sources p and p are rising at the same speed', the first node N and the first voltage source p are between The first voltage source p & will not have a voltage difference during the voltage rise process, that is, the source of the first PM ^ S transistor 52 (ie, the first voltage source p 0 and the gate (ie, the first node N) ), The voltage difference Vsm = μ, so that the first pM0s transistor is turned off during the entire voltage rise process, until the first node voltage value rises to the size that can turn on the first NMOS transistor 54 The voltage value of the second node N 妁 will drop to the ground voltage due to the turning on of the first NMOS transistor 54. In this way, the second question 0§ transistor = 6 will always be kept off and the first voltage The source p can play the role of providing the power supply voltage of the integrated circuit originally. However, when the first voltage source P1 generates a 1 ···, rising voltage pulse due to the occurrence of the electrostatic discharge phenomenon, due to the second voltage The source p is independent of the

Page 17 584952 Supply the ESD level of the clamp circuit 50, which is counted as a larger size transistor, a higher concentration of P + type ion implantation, and power. The fourth embodiment shows that the present invention is electrically connected to one of the other power supply clamp circuits 70, and the system 70 is connected to the above-mentioned power supply without repeating the description. However, it is different from the power supply clamping PMOS transistor 84 shown in FIG. 2 and the second pM0s. V. Description of the invention (12) A voltage source P 1 will not be generated. As mentioned before, the source of the first PMOS transistor 52 (that is, one of the PMOS transistor 52 between the first node N0 and the on node 5 is turned on and the second node N is turned on so that the second NMOS transistor 56 is turned on. The action described above, the power supply clamps the opening of the electric power 56 to provide the first electric path. In this way, the current of the electrostatic discharge can cause damage to the internal circuit of the grounding body circuit through this path. Similarly, in order to improve the power of the second The NMOS transistor 56 is usually set or applied to its drain during the manufacturing process to increase the discharge capacity of the current path. Please refer to Figure 4 for a schematic circuit diagram between the first voltage source P and the ground. Power supply The clamp circuit 50 should be very similar. Therefore, the power supply clamp circuit 70 series circuit 30 generally includes a second voltage pulse. Therefore, the voltage difference generated at the first node NA is the pole (that is, the first Voltage source P1) and The gate voltage difference V SPP is six to 0 v, which makes it the first state, and when the voltage value of the first PMOS transistor will be pulled up by the first voltage source P into the on state. Via the road 50, the second NMOS is used. The current path from the transistor voltage source P to the ground terminal causes the first voltage source voltage terminal to discharge without

Page 18 584952 V. Description of the invention (13) The function of the transistor 84 is the same as that of the second PMOS transistor 42 in FIG. 2. It is used to enter the on state when the first voltage source P is electrostatically discharged. The interaction between the first and second PMOS transistors 72 and 84 enables the N & voltage value of the second node to be automatically adjusted to a desired voltage range. Since the operation principle of the power supply clamping circuit 70 in FIG. 4 is very similar to that of the power supply clamping circuit 300 in FIG. 2, the description will not be repeated. Similarly, in order to improve the ESD level of the power supply clamp circuit 70, the second NMOS transistor 76 is usually designed as a larger-sized transistor, or a higher concentration of P + type ion cloth is applied to its drain during the manufacturing process. To increase the discharge capacity of the current path. Compared with the power supply clamping circuit of the conventional technology, the power supply clamping circuit of the present invention uses the design of adding the second PMOS transistor between the first node and the second node to The voltage value is within the desired voltage range, so that the aforementioned circuit in the conventional technology can simplify the process of adjusting the circuit parameters in order to maintain the high ESD level of the power supply clamping circuit, thereby reducing the design The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the present invention are covered by the patent scope of the present invention.

584952 Brief description of the diagram Brief description of the diagram: Figure 1 is a schematic circuit diagram of a conventional power supply clamping circuit. FIG. 2 is a schematic circuit diagram of a power supply clamping circuit according to the present invention. FIG. 3 is a schematic circuit diagram of another power supply clamping circuit according to the present invention. FIG. 4 is a schematic circuit diagram of another power supply clamping circuit according to the present invention. Symbol description of the icon:

Page 20 10 '30 > 50' 70 Power supply clamp circuit 12 ^ 32 ~ 42 ^ 52 '60 ~ 72' 80 > 84PMOS transistor 14 > 16 > 34 > 36 > 54 ~ 56 ^ 62 ^ 74, 76, 82 NMOS transistor 18 '38 ^ 58 > 78 resistance 20 ^ 40 capacitor

Claims (1)

584952 6. Application Patent Scope 1. A power supply clamp circuit is used to prevent the first voltage source of an integrated circuit from causing damage to the integrated circuit due to electrostatic discharge (ESD). The power supply clamping circuit includes: a voltage generator electrically connected to a first node for generating a voltage; a first PM0S transistor whose source is electrically connected to the first voltage source and whose gate The first node is electrically connected to the second node; the first NMOS transistor is electrically connected to the second node; the gate is electrically connected to the first node; A second NMOS transistor, whose drain is electrically connected to the first voltage source, whose gate is electrically connected to the second node, whose source is grounded; and a second PMOS transistor, whose source is electrically Connected to the second node, its gate and drain are both electrically connected to the first node. 2. The power supply clamping circuit described in item 1 of the scope of patent application, wherein the drain of the second NMOS transistor is subjected to P + ion implantation treatment. 3. The power supply clamping circuit according to item 1 of the patent application scope, wherein the voltage generator includes: a resistor, one end of which is electrically connected to the first voltage source, and the other end of which is electrically connected to the first node; And a capacitor, one end of which is electrically connected to the first node, and the other end of which is connected 584952 6. Scope of Patent Application. 4. The power supply clamping circuit as described in item 3 of the scope of the patent application, wherein the resistor is made of metal wires. 5. The power supply clamping circuit according to item 3 of the scope of patent application, wherein the capacitor is formed by connecting a drain and a source of a NMOS transistor to a base. 6. The power supply clamping circuit according to item 1 of the patent application scope, wherein the integrated circuit further includes a second voltage source, the second voltage source is independent of the first voltage source and its value is equal to the first voltage The source values are equal, and the voltage generator includes: a resistor, one end of which is electrically connected to the second voltage source, and the other end of which is electrically connected to a third node; a third PMOS transistor, whose source is electrically connected At the third node, its gate is electrically connected to a fourth node, and its drain is electrically connected to the first node; and a third NMOS transistor, whose drain and gate are both electrically connected to the fourth node , Its source is grounded. 7. The power supply clamping circuit as described in item 6 of the scope of the patent application, wherein the resistor is made of metal wires. Page 22 584952 6. Scope of patent application 8. A power supply clamp circuit is used to prevent a first voltage source of an integrated circuit from causing an electrostatic discharge (ESD) to the integrated circuit. The circuit caused damage 'The power supply clamping circuit includes: a first PMOS transistor whose source is electrically connected to the first voltage source, whose gate is electrically connected to a first node, and whose drain is electrically connected to a − Ichiro, a first NMOS transistor, whose drain is electrically connected to the second node, its gate is electrically connected to the first node, and its source is grounded; a second NMOS transistor, whose drain is electrically connected to The gate of the first voltage source is electrically connected to the second node, and the source is grounded; ... a second voltage source is independent of the first voltage source and has a value equal to the value of the first voltage source; " A resistor, one end of which is electrically connected to the second voltage source, and the other end of which is electrically connected to a third node; a second PM0S transistor, whose source is electrically connected to the third node, and whose gate is electrically connected to a The fourth node, which The drain electrode is electrically connected to the first node; and a second NMOS transistor, whose pole and gate are both electrically connected to the fourth node of Guhai, and its source is grounded. 9 · As described in item 8 of the scope of patent application Power supply clamping circuit, wherein the drain of the second NMOS transistor is subjected to ρ + ion implantation treatment. ', 584952 6. Scope of patent application 10. The power supply clamping circuit described in item 8 of the scope of patent application, wherein the resistor is made of metal wires. Page 24 1