KR100251986B1 - Output driver and method for forming the same - Google Patents

Output driver and method for forming the same Download PDF

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KR100251986B1
KR100251986B1 KR1019970014881A KR19970014881A KR100251986B1 KR 100251986 B1 KR100251986 B1 KR 100251986B1 KR 1019970014881 A KR1019970014881 A KR 1019970014881A KR 19970014881 A KR19970014881 A KR 19970014881A KR 100251986 B1 KR100251986 B1 KR 100251986B1
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South Korea
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transistor
pull
forming
output driver
threshold voltage
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KR1019970014881A
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Korean (ko)
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KR19980077677A (en
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마숙락
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

PURPOSE: An output driver and a manufacturing method of the same are provided to realize the connection between output terminals regardless of the dimension of source voltage of connected devices without adding complicated devices. CONSTITUTION: The output driver comprises a pull-up transistor(PMOS), a pull-down transistor(NMOS) and an NMOS transistor(22). The NMOS transistor(22) is positioned between the pull up transistor and pull down transistor, and the threshold voltage of the NMOS transistor(22) is about 0. If the output of the NMOS transistor(22) is connected to an output of a microprocessor(21) having source voltage of 5V, the pull up transistor(PMOS) is turned off and the pull down transistor(NMOS) is turned on when input voltage is 3.3V.

Description

출력구동기 및 그 제조 방법{OUTPUT DRIVER AND METHOD FOR FORMING THE SAME}OUTPUT DRIVER AND METHOD FOR FORMING THE SAME}

본 발명은 일반적으로 반도체 장치 및 그 제조 방법에 관한 것으로 특히, 다른 전원 전압간의 접속시 사용되는 출력구동기 및 그 제조 방법에 관한 것이다. CMOS로 이루어진 출력구동기의 풀업(pull-up) 트랜지스터 PMOS는 입력 전압이 고전위일 때 오프(off)되고 저전위일 때 온(on) 되어야 한다. 그러나 도1에 도시한 CMOS로 이루어진 출력구동기에서 고전위 3.3 V가 인가된 출력구동기의 출력단을 5 V의 전원 전압을 갖는 마이크로 프로세서(11)의 출력단과 연결하였을 때 게이트-소스 전압 VGS가 음의 전압을 갖게 되어 PMOS에 전류가 흐르게 되는 단점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices and methods of manufacturing the same, and more particularly, to output drivers and methods of manufacturing the same, which are used in connection between different power supply voltages. The pull-up transistor PMOS of an output driver made of CMOS should be turned off when the input voltage is high and on when it is low. However, the gate-source voltage V GS is negative when the output terminal of the output driver to which the high potential 3.3 V is applied is connected to the output terminal of the microprocessor 11 having the power supply voltage of 5 V in the output driver including the CMOS shown in FIG. 1. It has a disadvantage that the current flows through the PMOS.

상기와 같은 문제점을 해결하기 위한 종래 기술은 출력구동기 출력단과 접속되는 장치 각각의 전원 전압을 고려하여 풀업 트랜지스터인 PMOS의 채널 특성을 최적화하기 위한 이온주입 공정을 실시하는 어려움이 있다.Conventional technology for solving the above problems has a difficulty in performing the ion implantation process for optimizing the channel characteristics of the pull-up transistor PMOS in consideration of the power supply voltage of each device connected to the output driver output terminal.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 복잡한 공정의 추가 없이, 접속되는 장치의 전원 전압의 크기에 관계하지 않고 출력단 간을 접속할 수 있는 출력구동기 및 그 제조 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide an output driver and a method of manufacturing the same that can be connected between the output terminals irrespective of the magnitude of the power supply voltage of the connected device, without the addition of a complicated process. .

도1은 종래의 CMOS 출력구동기.1 is a conventional CMOS output driver.

도2는 본 발명에 따른 CMOS 출력구동기.2 is a CMOS output driver according to the present invention.

도3A 내지 도3D는 본 발명에 따른 문턱전압이 0에 가까운 트랜지스터가 추가된 CMOS 출력구동기 제조 공정도.3A to 3D illustrate a CMOS output driver manufacturing process in which a transistor having a threshold voltage close to zero is added according to the present invention.

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

VCC: 인가전압 VGS: 게이트-소스 전압V CC : Applied Voltage V GS : Gate-Source Voltage

VSS: 접지전압 11, 21: 마이크로 프로세서V SS : Ground Voltage 11, 21: Microprocessor

31: P형 반도체 기판 32, 34: 포토레지스트 패턴31: P-type semiconductor substrate 32, 34: photoresist pattern

33: N웰 35: P웰33: N well 35: P well

36: 절연막 37: 게이트 전극36: insulating film 37: gate electrode

38: 드레인 39: 소스38: drain 39: source

40: 문턱전압이 0에 가까운 트랜지스터40: transistor with threshold voltage near zero

상기 목적을 달성하기 위한 본 발명은 풀업 트랜지스터와 풀다운 트랜지스터를 구비하는 출력구동기에 있어서, 상기 풀업 트랜지스터와 상기 출력구동기의 출력단 사이에 문턱전압이 0에 가까운 NMOS 트랜지스터를 더 구비하는 출력구동기를 제공한다.In order to achieve the above object, the present invention provides an output driver including a pull-up transistor and a pull-down transistor, the output driver further comprising an NMOS transistor having a threshold voltage close to zero between the pull-up transistor and the output terminal of the output driver. .

또한, 상기 목적을 달성하기 위한 본 발명은, 풀업 트랜지스터를 이루는 웰과 풀다운 트랜지스터를 이루는 웰이 형성된 반도체 기판 상에 전면이온주입 공정을 실시하여 상기 두 웰 사이에 존재하게 될 트랜지스터의 문턱전압이 0에 가까와지도록 하는 단계; 풀업 트랜지스터의 문턱전압과 풀다운 트랜지스터의 문턱전압을 조절하기 위한 이온주입 공정을 각기 실시하는 단계; 절연막을 형성하는 단계; 상기 각 트랜지스터의 게이트 전극을 형성하는 단계; 상기 각 트랜지스터의 소스 및 드레인을 형성하기 위한 이온주입 공정을 실시하는 단계; 및 소정의 층간 절연막 형성 공정 및 상기 각 트랜지스터간의 전기적 연결을 위한 금속 배선 형성 공정 단계를 포함하는 출력구동기 제조 방법을 제공한다.In addition, in order to achieve the above object, the present invention performs a front ion implantation process on a semiconductor substrate on which a well constituting a pull-up transistor and a well constituting a pull-down transistor is formed, whereby a threshold voltage of a transistor to be present between the two wells is 0. Bringing it closer to; Performing an ion implantation process for adjusting the threshold voltage of the pull-up transistor and the threshold voltage of the pull-down transistor, respectively; Forming an insulating film; Forming a gate electrode of each transistor; Performing an ion implantation process to form a source and a drain of each transistor; And a step of forming a predetermined interlayer insulating film and forming a metal wiring for electrical connection between the transistors.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 살펴본다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도2에 도시한 바와 같이 고전위 3.3 V, 저전위 0 V에서 동작하는 CMOS로 이루어지는 출력구동기에서 풀업 트랜지스터 PMOS와 출력단 사이에 문턱전압이 0에 가까운 NMOS(22)를 추가하고 그 출력단을 전원 전압이 5 V인 마이크로 프로세서(21)의 출력단과 접속한 경우, 입력 전압(입력1)이 3.3 V일 때 풀업 트랜지스터 PMOS는 오프되고 풀다운(pull-down) 트랜지스터 NMOS는 온이 되며 PMOS와 NMOS 사이에 추가된 NMOS(22)에 0보다 큰 입력 전압(입력2)을 인가하면 상기 NMOS는 언제나 온(on) 되어 있는 상태이므로 전압이 높은 마이크로 프로세서(21)의 접속으로 인하여 PMOS에 전류가 흐르는 문제점이 발생되지 않는다.As shown in Fig. 2, an NMOS 22 having a threshold voltage close to zero is added between a pull-up transistor PMOS and an output terminal in an output driver including a CMOS operating at a high potential of 3.3 V and a low potential 0 V, and the output terminal is connected to a power supply voltage. When connected to the output terminal of the 5 V microprocessor 21, when the input voltage (input 1) is 3.3 V, the pull-up transistor PMOS is turned off and the pull-down transistor NMOS is turned on and between the PMOS and the NMOS. When an input voltage greater than zero (input 2) is applied to the added NMOS 22, the NMOS is always on, so that a current flows in the PMOS due to the connection of the microprocessor 21 having a high voltage. It does not occur.

도3A 내지 도3D는 본 발명에 따른 문턱전압이 0에 가까운 트랜지스터가 포함된 출력구동기를 제조하는 공정을 나타내는 단면도이다.3A to 3D are cross-sectional views illustrating a process of manufacturing an output driver including a transistor having a threshold voltage close to zero according to the present invention.

먼저, 3A에 도시한 바와 같이 반도체 기판(31) 상에 형성된 제1 포토레지스트 패턴(32)을 마스크로 사용하여 n형 불순물 이온주입 공정을 실시하여 N웰을 형성한다.First, as shown in 3A, an N type impurity ion implantation process is performed using the first photoresist pattern 32 formed on the semiconductor substrate 31 as a mask to form an N well.

이어서, 도3B에 도시한 바와 같이 상기 제1 포토레지스트 패턴(32)을 제거하고, 상기 N웰(33)과 그에 인접한 문턱전압이 0인 NMOS를 형성할 영역에 제2 포토레지스트 패턴(34)을 형성하고, 상기 제2 포토레지스트 패턴(34)을 마스크로 사용하여 p형 불순물 이온주입 공정으로 P웰을 형성한다.Subsequently, as shown in FIG. 3B, the first photoresist pattern 32 is removed, and the second photoresist pattern 34 is formed in a region where the N well 33 and an NMOS having a threshold voltage adjacent thereto are formed. P wells are formed using a p-type impurity ion implantation process using the second photoresist pattern 34 as a mask.

다음으로, 도3C에 도시한 바와 같이 상기 제2 포토레지스트 패턴(34)을 제거하고, 상기 N웰과 P웰 사이에 위치하는 NMOS의 문턱전압이 0에 가깝도록 불순물을 전면이온주입(blanket implantation)하여 상기 문턱전압이 0에 가까운 NMOS의 채널을 형성한다.Next, as shown in FIG. 3C, the second photoresist pattern 34 is removed, and impurities are implanted into the blanket so that the threshold voltage of the NMOS located between the N well and the P well is close to zero. ) To form a channel of the NMOS whose threshold voltage is close to zero.

다음으로, 도3D에 도시한 바와 같이 통상의 트랜지스터 제조 방법으로 상기 N웰(33) 및 P웰(35) 각각에 채널을 형성하기 위한 이온주입 공정과 최적화된 문턱전압을 얻기 위한 이온주입 공정을 실시하고, 절연막(36)과 각 트랜지스터의 게이트(Gate) 전극(37)을 형성한 후, 각 트랜지스터의 소스(38) 및 드레인(39)을 형성하기 위한 이온주입 공정을 각각 실시하고, 풀업 트랜지스터의 소스단과 문턱전압이 0인 트랜지스터(40)의 드레인단을 연결하는 금속 배선(41) 및 문턱전압이 0인 트랜지스터(40)의 소스단과 풀다운 트랜지스터 소스단을 연결하는 금속 배선(42)을 형성한다.Next, as shown in FIG. 3D, an ion implantation process for forming a channel in each of the N well 33 and the P well 35 and an ion implantation process for obtaining an optimized threshold voltage are performed using a conventional transistor manufacturing method. After the insulating film 36 and the gate electrode 37 of each transistor are formed, an ion implantation process for forming the source 38 and the drain 39 of each transistor is performed, respectively, and the pull-up transistor is performed. A metal wiring 41 connecting the source terminal of the transistor 40 to the drain terminal of the transistor 40 having a threshold voltage of 0 and a metal wiring 42 connecting the source terminal of the transistor 40 having a threshold voltage of 0 and the pull-down transistor source terminal thereof to be formed. do.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 출력구동기의 풀업 트랜지스터 PMOS와 출력단 사이에 문턱전압이 0에 가까운 트랜지스터를 추가하여 PMOS의 동작이 원활하게 이루어지도록 하여, 출력구동기에 접속되는 회로의 전원 전압의 크기에 관계없이 상호 출력단을 접속할 수 있는 출력구동기를 얻을 수 있다. 또한 문턱전압이 0인 트랜지스터는 별도의 마스크 공정 없이 전면이온주입 공정만으로 형성할 수 있어 비교적 간단한 공정으로 상기 출력구동기를 제조할 수 있다.The present invention made as described above relates to the magnitude of the power supply voltage of the circuit connected to the output driver by adding a transistor close to zero between the pull-up transistor PMOS and the output terminal of the output driver to facilitate the operation of the PMOS. It is possible to obtain an output driver capable of connecting the mutual output stages without the need. In addition, since the transistor having a threshold voltage of 0 can be formed only by the front ion implantation process without a separate mask process, the output driver can be manufactured in a relatively simple process.

Claims (4)

풀업 트랜지스터와 풀다운 트랜지스터를 구비하는 출력구동기에 있어서,In an output driver having a pull-up transistor and a pull-down transistor, 상기 풀업 트랜지스터와 상기 출력구동기의 출력단 사이에 문턱전압이 0에 가까운 NMOS 트랜지스터를 더 구비하는 출력구동기.And an NMOS transistor having a threshold voltage close to zero between the pull-up transistor and an output terminal of the output driver. 제 1 항에 있어서,The method of claim 1, 상기 출력구동기의 출력단은 다른 회로의 출력단과 접속되는 것을 특징으로하는 출력구동기.And an output end of the output driver is connected to an output end of another circuit. 출력구동기 제조 방법에 있어서,In the output driver manufacturing method, 풀업 트랜지스터를 이루는 웰과 풀다운 트랜지스터를 이루는 웰이 형성된 반도체 기판 상에 전면이온주입 공정을 실시하여 상기 두 웰 사이에 존재하게 될 트랜지스터의 문턱전압이 0에 가까와지도록 하는 단계;Performing a front ion implantation process on a semiconductor substrate on which a well constituting a pull-up transistor and a well constituting a pull-down transistor are formed such that a threshold voltage of a transistor to be present between the two wells approaches zero; 풀업 트랜지스터의 문턱전압과 풀다운 트랜지스터의 문턱전압을 조절하기 위한 이온주입 공정을 각기 실시하는 단계;Performing an ion implantation process for adjusting the threshold voltage of the pull-up transistor and the threshold voltage of the pull-down transistor, respectively; 절연막을 형성하는 단계;Forming an insulating film; 상기 각 트랜지스터의 게이트 전극을 형성하는 단계;Forming a gate electrode of each transistor; 상기 각 트랜지스터의 소스 및 드레인을 형성하기 위한 이온주입 공정을 실시하는 단계; 및Performing an ion implantation process to form a source and a drain of each transistor; And 소정의 층간 절연막 형성 공정 및 상기 각 트랜지스터간의 전기적 연결을 위한 금속 배선 형성 공정 단계를 포함하는 출력구동기 제조 방법.A method of manufacturing an output driver comprising a step of forming a predetermined interlayer insulating film and a step of forming a metal wiring for electrical connection between each transistor. 제 3 항에 있어서,The method of claim 3, wherein 상기 금속 배선 형성 공정 단계는,The metal wiring forming process step, 상기 풀업 트랜지스터의 소스단과 상기 문턱전압이 0인 트랜지스터의 드레인단을 연결하는 금속 배선을 형성하는 단계; 및Forming a metal line connecting the source terminal of the pull-up transistor and the drain terminal of the transistor having a threshold voltage of 0; And 상기 문턱전압이 0인 트랜지스터의 소스단과 상기 풀다운 트랜지스터의 소스단을 연결하는 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 출력구동기 제조 방법.And forming a metal line connecting the source terminal of the transistor having the threshold voltage equal to zero and the source terminal of the pull-down transistor.
KR1019970014881A 1997-04-22 1997-04-22 Output driver and method for forming the same KR100251986B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920008757A (en) * 1990-10-29 1992-05-28 마이클 에이치.모리스 Apparatus for Minimizing Reverse Bias Breakdown of Emitter Base Junction of Output Transistor in Tri-state Dual CMOS Driver Circuit
KR960043524A (en) * 1995-05-23 1996-12-23 홍-치우 후 Output buffering device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920008757A (en) * 1990-10-29 1992-05-28 마이클 에이치.모리스 Apparatus for Minimizing Reverse Bias Breakdown of Emitter Base Junction of Output Transistor in Tri-state Dual CMOS Driver Circuit
KR960043524A (en) * 1995-05-23 1996-12-23 홍-치우 후 Output buffering device

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