CN114388492A - Electrostatic discharge protection circuit and semiconductor circuit - Google Patents

Abstract

The invention provides an electrostatic discharge protection circuit and a semiconductor circuit, which are used for a semiconductor element. The semiconductor device has a first drain/source electrode and a second drain/source electrode, and is surrounded by the deep well. The electrostatic discharge protection circuit comprises a control circuit and a discharge circuit. The control circuit is electrically connected between the first drain/source electrode and the power supply terminal, has a control terminal electrically connected to the deep well, and generates a control signal. The discharge circuit is electrically connected between the first drain/source electrode and a power supply terminal and is controlled by a control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the control circuit generates a control signal according to the potential state of the deep well and the potential state of the first drain/source electrode, and the discharge circuit provides a discharge path between the first drain/source electrode and the power source terminal according to the control signal. The electrostatic discharge protection circuit provided by the invention does not have a capacitor-resistor circuit adopted by the prior art, thereby occupying a smaller area.

Description

Electrostatic discharge protection circuit and semiconductor circuit

Technical Field

The present invention relates to semiconductor circuits, and more particularly to electrostatic discharge protection circuits.

Background

With the development of semiconductor technology of integrated circuits, the size of semiconductor devices has been reduced to the sub-micron level to improve the performance and operation speed of integrated circuits, but the reduction of the device size raises some reliability issues, particularly the maximum impact on the protection capability of the integrated circuits against Electrostatic Discharge (ESD). As the device size decreases due to advanced process technology, the ESD protection capability also decreases significantly, resulting in a significant decrease in the ESD tolerance of the device. Therefore, an esd protection circuit is required to protect the device from esd. However, the conventional esd protection circuit includes a capacitor-resistor circuit, which occupies a large area and is not suitable for the miniaturization of the integrated circuit.

Disclosure of Invention

An embodiment of the invention provides an electrostatic discharge protection circuit, which can be used for a semiconductor device. The semiconductor device has a first drain/source electrode and a second drain/source electrode, and is surrounded by a deep well. The ESD protection circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode of the semiconductor device and a power source terminal, and has a first control terminal. The first control end is electrically connected with the deep well, and the first control circuit generates a first control signal. The first discharge circuit is electrically connected between the first drain/source electrode and a power supply terminal and is controlled by a first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates a first control signal according to the potential state of the deep well and the potential state of the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

An embodiment of the invention provides a semiconductor circuit. The semiconductor circuit includes a semiconductor device, a first control circuit, and a first discharge circuit. The semiconductor device is formed in a well and has a first drain/source electrode and a second drain/source electrode. The well is surrounded by a deep well. The well has a first conductivity type and the deep well has a second conductivity type different from the first conductivity type. The ESD protection circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode and a power supply terminal and has a first control terminal. The first control end is electrically connected with the deep well, and the first control circuit generates a first control signal. The first discharge circuit is electrically connected between the first drain/source electrode and a power supply terminal and is controlled by a first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates a first control signal according to a potential state of the deep well and a potential state of the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power source terminal according to the first control signal.

Drawings

FIG. 1A shows a semiconductor circuit according to an embodiment of the invention.

Fig. 1B shows a semiconductor circuit according to another embodiment of the present invention.

Fig. 2A shows a cross-sectional view of a transistor according to an embodiment of the present invention.

Fig. 2B shows a cross-sectional view of a transistor according to another embodiment of the present invention.

Fig. 3 shows a semiconductor circuit according to another embodiment of the invention.

Reference numerals:

1: semiconductor circuit having a plurality of transistors

10: semiconductor device with a plurality of semiconductor chips

11: electrostatic discharge protection circuit

12. 13: diode with a high-voltage source

20: substrate

21: n-type deep well

22: p-type trap

23: n type doped region (drain region)

24: n type doped region (Source region)

25: n-type doped region

26: gate dielectric layer

27: gate layer

28: n-type doped region

110. 110': control circuit

111. 111': discharge circuit

112: reverser

113: control circuit

114: discharge circuit

115. 300, and (2) 300: reverser

CE20, CE 21: contact electrode

D: drain electrode

G: grid electrode

GND: ground voltage

L21: boundary of

N110, N111, N113, N114, N300: n-type transistor

ND10, ND 11: node point

P110, P113, P300, P301: p-type transistor

S: source electrode

S10, S10', S11: control signal

T10: power supply terminal

T11, T14: control terminal

T12, T15, T30: input terminal

T13, T16, T31: output end

VDD: high operating voltage

VSS: low operating voltage

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

FIG. 1A shows a semiconductor circuit according to an embodiment of the invention. Referring to fig. 1A, the semiconductor circuit 1 includes a semiconductor device 10, an esd protection circuit 11, and diodes 12-13. In the embodiment of fig. 1A, the semiconductor device 10 is an N-type transistor having a gate electrode G, a drain electrode D, and a source electrode S. Hereinafter, the embodiments will be described by taking a transistor as the semiconductor device 10. Fig. 2A shows a structural cross-sectional view of the transistor 10.

Referring to fig. 2A, the transistor 10 is formed on a substrate 20, wherein the conductivity type of the substrate 20 is P-type. An N-type deep well 21 is formed in the substrate 20, wherein L21 denotes a boundary between the N-type deep well 21 and the substrate 20. In the deep well 21, a P-type well 22 and an N-type doped region 25 are formed. Two N-type doped regions 23 and 24 are formed in the well 22, and a gate dielectric layer 26 is formed on the substrate 20 between the doped regions 23 and 24. In this embodiment, the N-type doped region 25 is formed in the deep well 21 at a position close to the N-type doped region 23. A gate layer 27 is formed on the gate dielectric layer 26, wherein the gate layer 27 is a metal layer or a polysilicon layer. Doped regions 23 and 24 and gate layer 27 form transistor 10. As shown in fig. 1A and 2A, the doped region 23 serves as a drain region of the transistor 10, and a contact electrode electrically connected to the doped region 23 serves as a drain electrode D. The doped region 24 serves as a source region of the transistor 10, and a contact electrode electrically connected to the doped region 24 serves as a source electrode S. A contact electrode electrically connected to the gate layer 27 serves as the gate electrode G. In the present embodiment, a contact electrode CE20 is electrically connected to doped region 25. When the semiconductor circuit 1 is in the normal operation mode, a high operation voltage VDD is supplied to the contact electrode CE 20; when the semiconductor circuit 1 is in the abnormal operation mode, the high operation voltage VDD is not supplied to the contact electrode CE20, i.e., the potential state of the contact electrode CE20 is floating. As can be seen from the cross-sectional view of fig. 2A, the transistor 10 is formed in the deep well 21, and in detail, the transistor 10 is surrounded by the deep well 21. Fig. 1A shows a boundary L21, which surrounds the transistor 10, thereby illustrating the arrangement relationship between the transistor 10 and the deep well 21 in fig. 2A.

Referring again to fig. 1A, the cathode of the diode 12 is electrically connected to the drain electrode D of the transistor 10, and the anode thereof is electrically connected to the power supply terminal T10. The cathode of the diode 13 is electrically connected to the source electrode S of the transistor 10, and the anode thereof is electrically connected to the power supply terminal T10. When the semiconductor circuit 1 is in the normal operation mode, a low operating voltage VSS or a ground voltage GND is supplied to the power terminal T10 (hereinafter, the low operating voltage VSS will be taken as an example to illustrate the embodiments of the present invention); when the semiconductor circuit 1 is in the abnormal operation mode, no voltage is supplied to the power source terminal T10, i.e., the potential state of the power source terminal T10 is floating.

Referring to fig. 1A and fig. 2A, the esd protection circuit 11 is electrically connected to the drain electrode D, and includes a control circuit 110 and a discharge circuit 111. The control circuit 110 has a control terminal T11 electrically connected to the contact electrode CE20 at the node ND 10. In this embodiment, the control circuit 110 includes an inverter 112. The inverter 112 has an input terminal T12 and an output terminal T13, and the input terminal T12 is electrically connected to the control terminal T11 of the control circuit 11. The inverter 112 includes a P-type transistor P110 and an N-type transistor N110. The transistor P110 has a gate electrically connected to the input terminal T12, a source electrically connected to the drain electrode D of the transistor 10, and a drain electrically connected to the output terminal T13. The transistor N110 has a gate electrically connected to the input terminal T12, a drain electrically connected to the output terminal T13, and a source electrically connected to the power source terminal T10. The discharge circuit 111 includes an N-type transistor N111. The transistor N111 has a gate electrically connected to the output terminal T13 of the inverter 112, a drain electrically connected to the drain electrode D of the transistor 10, and a source electrically connected to the power supply terminal T10. Based on the connection of the circuit architecture of the control circuit 110 and the transistor 10, the control circuit 110 generates the control signal S10 according to the potential state of the deep well 21 and based on the potential state of the drain electrode D or the potential state of the power source terminal T10. For a related description, please refer to the following.

When the semiconductor circuit 1 is in the abnormal operation mode, the high operation voltage VDD is not supplied to the contact electrode CE20, and no voltage is supplied to the power source terminal T10, i.e., the potential states of the contact electrode CE20 and the power source terminal T10 are floating. Since the input terminal T12 of the inverter 112 is electrically connected to the node ND10 through the control terminal T11 and the contact electrode CE20, the input terminal T12 is also in a floating state (floating), so that the transistor P110 is turned on and the transistor N110 is turned off. When an ESD event occurs on the drain electrode D, the potential of the drain electrode D is increased instantaneously. With the transistor P110 turned on, the output terminal T13 is at a high state, i.e., the control signal S10 has a high voltage level. The transistor N111 is turned on according to the control signal S10, such that a discharge path is formed between the drain electrode D and the power terminal T10. The electrostatic charge on the drain electrode D is conducted to the power terminal T10 through the discharge path, thereby protecting the circuit or device coupled to the transistor 10 from the electrostatic charge.

In this embodiment, when the semiconductor circuit 1 is in the abnormal operation mode and an electrostatic discharge event occurs on the drain electrode D, another discharge path is formed between the power source terminal T10 and the source electrode S due to the conduction of the transistor N111 and the connection structure of the diode 13 (the anode thereof is electrically connected to the power source terminal T10 and the cathode thereof is electrically connected to the source electrode S). Therefore, when an ESD event occurs on the drain electrode D, the electrostatic charge on the drain electrode D can be conducted to the source electrode S in addition to the power terminal T10.

When the semiconductor circuit 1 is in the normal operation mode, the high operating voltage VDD is supplied to the contact electrode CE20 and the low operating voltage VSS is supplied to the power source terminal T10, i.e., the contact electrode CE20 is in a high potential state and the power source terminal T10 is in a low potential state. In the normal operation mode, since the input terminal T12 of the inverter 112 is electrically connected to the node ND10 through the control terminal T11 and contacts the electrode CE20, the input terminal T12 is in a high state, so that the transistor N110 is turned on and the transistor P110 is turned off. The output terminal T13 is at a low state based on the low operating voltage VSS, i.e., the control signal S10 has a low voltage level. The transistor N111 is turned off according to the control signal S10 with a low voltage level. In the normal operation mode, the transistor N111 is turned off, so that the drain electrode D and the power terminal T10 have no discharge path, i.e., the discharge path is blocked.

In other embodiments, the esd protection circuit 11 is also electrically connected to the source electrode S. In this embodiment, as shown in fig. 2B, an N-type doped region 28 is further formed in the deep well 21, and a contact electrode CE21 is electrically connected to the doped region 28. When the semiconductor circuit 1 is in the normal operation mode, the high operation voltage VDD is supplied to the contact electrode CE 21; when the semiconductor circuit 1 is in the abnormal operation mode, the high operation voltage VDD is not supplied to the contact electrode CE21, i.e., the potential state of the contact electrode CE21 is floating. In this embodiment, the N-type doped region 28 is formed in the deep well 21 near the N-type doped region (source region) 24. Referring to fig. 1B, the esd protection circuit 11 further includes a control circuit 113 and a discharge circuit 114. The control circuit 113 has a control terminal T14 electrically connected to the contact electrode CE21 at the node ND 11. The control circuit 113 includes an inverter 115. The inverter 115 has an input terminal T15 and an output terminal T16, and the input terminal T15 is electrically connected to the control terminal T14 of the control circuit 113. The inverter 115 includes a P-type transistor P113 and an N-type transistor N113. The transistor P113 has a gate electrically connected to the input terminal T15, a source electrically connected to the source electrode S of the transistor 10, and a drain electrically connected to the output terminal T16. The transistor N113 has a gate electrically connected to the input terminal T15, a drain electrically connected to the output terminal T16, and a source electrically connected to the power source terminal T10. The discharge circuit 114 includes an N-type transistor N114. The transistor N114 has a gate electrically connected to the output terminal T16 of the inverter 115, a drain electrically connected to the source electrode S of the transistor 10, and a source electrically connected to the power supply terminal T10. Based on the connection of the circuit architecture of the control circuit 113 and the transistor 10, the control circuit 113 generates the control signal S11 according to the potential state of the deep well 21 and based on the potential state of the source electrode S or the potential state of the power source terminal T10. For a related description, please refer to the following.

When the semiconductor circuit 1 is in the abnormal operation mode, the high operation voltage VDD is not supplied to the contact electrode CE21, and no voltage is supplied to the power source terminal T10, i.e., the potential states of the contact electrode CE21 and the power source terminal T10 are floating. Since the input terminal T15 of the inverter 115 is electrically connected to the node ND11 through the control terminal T14 and contacts the electrode CE21, the input terminal T15 is also in a floating state, so that the transistor P113 is turned on and the transistor N113 is turned off. When an electrostatic discharge event occurs on the source electrode S, the potential of the source electrode S is instantaneously increased. With the transistor P113 turned on, the output terminal T16 is at a high state, i.e. the control signal S11 has a high voltage level. The transistor N114 is turned on according to the control signal S11, such that a discharge path is formed between the source electrode S and the power source terminal T10. The electrostatic charge on the source electrode S is conducted to the power terminal T10 through the discharge path, thereby protecting the circuit or device coupled to the transistor 10 from the electrostatic charge.

In this embodiment, when the semiconductor circuit 1 is in the abnormal operation mode and an electrostatic discharge event occurs on the source electrode S, another discharge path is formed between the power source terminal T10 and the drain electrode D due to the connection structure of the transistor N114 being turned on and the diode 12 (the anode thereof is electrically connected to the power source terminal T10 and the cathode thereof is electrically connected to the drain electrode D). Therefore, when an ESD event occurs on the source electrode S, the electrostatic charge on the source electrode S can be conducted to the drain electrode D in addition to the power terminal T10.

When the semiconductor circuit 1 is in the normal operation mode, the high operating voltage VDD is supplied to the contact electrode CE21 and the low operating voltage VSS is supplied to the power source terminal T10, i.e., the contact electrode CE21 is in a high potential state and the power source terminal T10 is in a low potential state. In the normal operation mode, since the input terminal T15 of the inverter 115 is electrically connected to the node ND11 through the control terminal T14 and the contact electrode CE21, the input terminal T15 is in a high potential state, so that the transistor N113 is turned on and the transistor P113 is turned off. The output terminal T16 is at a low state based on the low operating voltage VSS, i.e., the control signal S11 has a low voltage level. The transistor N114 is turned off according to the control signal S11 with a low voltage level. In the normal operation mode, the transistor N114 is turned off, so that the source electrode S and the power terminal T10 have no discharge path, i.e., the discharge path is blocked.

In other embodiments, the esd protection circuit electrically connected to the drain electrode D of the transistor 10 has other circuit architectures. Referring to fig. 1A and fig. 3, compared with fig. 1A, the control circuit 110' of the esd circuit 11 in fig. 3 further includes an inverter 300. The inverter 300 has an input terminal T30 and an output terminal T31, and the input terminal T30 is electrically connected to the output terminal T13 of the inverter 112. The inverter 300 includes a P-type transistor P300 and an N-type transistor N300. The transistor P300 has a gate electrically connected to the input terminal T30, a source electrically connected to the drain electrode D of the transistor 10, and a drain electrically connected to the output terminal T31. The transistor N300 has a gate electrically connected to the input terminal T30, a drain electrically connected to the output terminal T31, and a source electrically connected to the power source terminal T10. In addition, based on the architecture of the control circuit 110 ', the discharge circuit 111' of the electrostatic discharge circuit 11 in fig. 3 includes a P-type transistor P301 instead of the N-type transistor N111 in fig. 1A. Referring to fig. 3, the transistor P301 has a gate electrically connected to the output terminal T31 of the inverter 300, a source electrically connected to the drain electrode D of the transistor 10, and a drain electrically connected to the power source terminal T10.

Referring to the above description of FIG. 1A, in the abnormal operation mode, the high operation voltage VDD is not applied to the contact electrode CE20, and no voltage is applied to the power source terminal T10, i.e., the potential states of the contact electrode CE20 and the power source terminal T10 are floating. When an esd event occurs on the drain electrode D, the output terminal T13 of the inverter 112 is at a high state. According to the high state of the output terminal T13, the transistor N300 is turned on and the transistor P300 is turned off. With the transistor N300 turned on, the output terminal T31 is at a low voltage level based on the floating state of the power source terminal T10, i.e., the control signal S10' has a low voltage level. The transistor P301 is turned on according to the control signal S10' with the low voltage level, such that a discharge path is formed between the drain electrode D and the power source terminal T10. The electrostatic charge on the drain electrode D is conducted to the power terminal T10 through the discharge path, thereby protecting the circuit or device coupled to the transistor 10 from the electrostatic charge.

In this embodiment, when the semiconductor circuit 1 is in the abnormal operation mode and an electrostatic discharge event occurs on the drain electrode D, another discharge path is formed between the power source terminal T10 and the source electrode S due to the conduction of the transistor P301 and the connection structure of the diode 13 (the anode thereof is electrically connected to the power source terminal T10 and the cathode thereof is electrically connected to the source electrode S). Therefore, when an ESD event occurs on the drain electrode D, the electrostatic charge on the drain electrode D can be conducted to the source electrode S in addition to the power terminal T10.

Similarly, referring to the above description with respect to fig. 1A, when the semiconductor circuit 1 is in the normal operation mode, the high operating voltage VDD is supplied to the contact electrode CE20 and the low operating voltage VSS is supplied to the power source terminal T10, i.e., the contact electrode CE20 is in a high potential state and the power source terminal T10 is in a low potential state. In the normal operation mode, the output terminal T13 is at a low state. According to the low state of the output terminal T13, the transistor P300 is turned on and the transistor N300 is turned off. With the transistor P300 turned on, the output terminal T31 is at a high voltage level based on the potential of the drain electrode D when the transistor 10 is operating, i.e., the control signal S10' has a high voltage level. The transistor P301 is turned off according to the control signal S10' of the high voltage bit. In the normal operation mode, the transistor P301 is turned off, so that the drain electrode D and the power source terminal T10 have no discharge path, i.e., the discharge path is blocked.

According to the embodiments, the esd protection circuit of the present invention does not have a capacitor-resistor circuit as in the prior art, and thus occupies a smaller area.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (22)

1. An ESD protection circuit for a semiconductor device having a first drain/source electrode and a second drain/source electrode surrounded by a deep well, comprising:

a first control circuit electrically connected between the first drain/source electrode of the semiconductor element and a power supply terminal, and having a first control terminal electrically connected to the deep well, wherein the first control circuit generates a first control signal; and

a first discharge circuit electrically connected between the first drain/source electrode and the power source terminal and controlled by the first control signal;

when an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to a potential state of the deep well and a potential state of the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

2. The esd protection circuit of claim 1, wherein the first control circuit comprises:

a first inverter electrically connected between the first drain/source electrode and the power supply terminal and having a first input terminal and a first output terminal;

wherein, the first input end is electrically connected with the first control end; and

the first inverter selectively determines a voltage of the first output terminal based on the potential state of the first drain/source electrode or a potential state of the power terminal according to the potential state of the deep well, and the first control circuit generates the first control signal according to the voltage of the first output terminal.

3. The ESD protection circuit of claim 2, wherein the first inverter generates the first control signal based on the potential state of the first drain/source electrode to control the discharge circuit to provide the first discharge path when the ESD event occurs on the first drain/source electrode.

4. The ESD protection circuit of claim 3, wherein the ESD event occurs during a floating state of the potential state of the deep well.

5. The ESD protection circuit of claim 2, wherein the first inverter generates the first control signal based on the potential state of the power source terminal to control the discharge circuit to block the first discharge path when the semiconductor device is in a normal operation mode.

6. The ESD protection circuit of claim 5, wherein in the normal operation mode, the deep well receives an operating voltage.

7. The esd protection circuit of claim 2, wherein the first inverter comprises:

a first P-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first drain/source electrode, and a second electrode electrically connected to the first output terminal; and

a first N-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first output terminal, and a second electrode electrically connected to the power terminal.

8. The ESD protection circuit of claim 7, wherein the first discharge circuit comprises:

a second N-type transistor having a control electrode electrically connected to the first output terminal, a first electrode electrically connected to the first drain/source electrode, and a second electrode electrically connected to the power supply terminal.

9. The ESD protection circuit of claim 2, wherein the first control circuit further comprises:

a second inverter electrically connected to the first drain/source electrode and the power source terminal, and having a second input terminal and a second output terminal;

wherein, the second input end is electrically connected with the first output end; and

wherein the second inverter generates the first control signal selectively based on the potential state of the first drain/source electrode or the potential state of the power source terminal according to the voltage of the first output terminal.

10. The esd protection circuit of claim 1, further comprising:

a second control circuit electrically connected between the second drain/source electrode of the semiconductor element and the power supply terminal and having a second control terminal, wherein the second control terminal is electrically connected to the deep well and generates a second control signal; and

a second discharge circuit electrically connected between the second drain/source electrode and the power supply terminal and controlled by the second control signal;

wherein, when the ESD event occurs on the second drain/source electrode, the second control circuit generates the second control signal according to the potential state of the deep well and a potential state of the second drain/source electrode, and the second discharge circuit provides a second discharge path between the second drain/source electrode and the power source terminal according to the second control signal.

11. The esd protection circuit of claim 1, further comprising:

a diode having an anode terminal electrically connected to the power terminal and a cathode terminal electrically connected to the second drain/source electrode;

when the electrostatic discharge event occurs on the first drain/source electrode, a second discharge path is formed between the power terminal and the second drain/source electrode through the diode.

12. A semiconductor circuit, comprising:

a semiconductor device formed in a well and having a first drain/source electrode and a second drain/source electrode, wherein the well is surrounded by a deep well, the well has a first conductivity type, and the deep well has a second conductivity type different from the first conductivity type;

a first control circuit electrically connected between the first drain/source electrode and a power supply terminal and having a first control terminal, wherein the first control terminal is electrically connected to the deep well and generates a first control signal; and

a first discharge circuit electrically connected between the first drain/source electrode and the power source terminal and controlled by the first control signal;

when an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to a potential state of the deep well and a potential state of the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

13. The semiconductor circuit of claim 12, wherein the first control circuit comprises:

a first inverter electrically connected between the first drain/source electrode and the power supply terminal and having a first input terminal and a first output terminal;

wherein, the first input end is electrically connected with the first control end; and

the first inverter selectively determines a voltage of the first output terminal based on the potential state of the first drain/source electrode or a potential state of the power terminal according to the potential state of the deep well, and the first control circuit generates the first control signal according to the voltage of the first output terminal.

14. The semiconductor circuit of claim 13, wherein the first inverter generates the first control signal based on the potential state of the first drain/source electrode to control the discharge circuit to provide the first discharge path when the esd event occurs on the first drain/source electrode.

15. The semiconductor circuit of claim 14, wherein said esd event occurs during a floating state of said potential state of said deep well.

16. The semiconductor circuit according to claim 13, wherein the first inverter generates the first control signal based on the potential state of the power source terminal to control the discharge circuit to block the first discharge path when the semiconductor device is in a normal operation mode.

17. The semiconductor circuit of claim 16, wherein in said normal operating mode, said deep well receives an operating voltage.

18. The semiconductor circuit of claim 13, wherein the first inverter comprises:

a first P-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first drain/source electrode, and a second electrode electrically connected to the first output terminal; and

a first N-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first output terminal, and a second electrode electrically connected to the power terminal.

19. The semiconductor circuit of claim 18, wherein the first discharge circuit comprises:

a second N-type transistor having a control electrode electrically connected to the first output terminal, a first electrode electrically connected to the first drain/source electrode, and a second electrode electrically connected to the power supply terminal.

20. The semiconductor circuit of claim 13, wherein the first control circuit further comprises:

a second inverter electrically connected to the first drain/source electrode and the power source terminal, and having a second input terminal and a second output terminal;

wherein, the second input end is electrically connected with the first output end; and

wherein the second inverter generates the first control signal selectively based on the potential state of the first drain/source electrode or the potential state of the power source terminal according to the voltage of the first output terminal.

21. The semiconductor circuit of claim 12, further comprising:

a second control circuit electrically connected between the second drain/source electrode of the semiconductor element and the power supply terminal and having a second control terminal, wherein the second control terminal is electrically connected to the deep well and generates a second control signal; and

a second discharge circuit electrically connected between the second drain/source electrode and the power supply terminal and controlled by the second control signal;

wherein, when the ESD event occurs on the second drain/source electrode, the second control circuit generates the second control signal according to the potential state of the deep well and a potential state of the second drain/source electrode, and the second discharge circuit provides a second discharge path between the second drain/source electrode and the power source terminal according to the second control signal.

22. The semiconductor circuit of claim 12, further comprising:

a diode having an anode terminal electrically connected to the power terminal and a cathode terminal electrically connected to the second drain/source electrode;

when the electrostatic discharge event occurs on the first drain/source electrode, a second discharge path is formed between the power terminal and the second drain/source electrode through the diode.

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