TWI747510B - Electrostatic discharge protection circuits and semiconductor circuits - Google Patents

Abstract

An electrostatic discharge protection circuit for a semiconductor element is provided. The semiconductor element includes a first drain/source electrode and a second drain/source electrode and surrounded by a deep well region. The electrostatic discharge protection circuit includes a control circuit and a discharge circuit. The control circuit, which is electronically connected between the first drain/source electrode and a power terminal, includes a control terminal electronically connected to the deep well region and generates a control signal. The discharge circuit is electronically connected between the first first drain/source electrode and the power terminal and controlled by the control signal. In response to an electrostatic discharge event occurring on the first drain/source electrode, the control circuit generates the control signal according to a potential state of the deep well region and a potential state of the first drain/source electrode, and the discharge circuit provides a discharge path between the first drain/source electrode and the power terminal.

Description

Electrostatic discharge protection circuit and semiconductor circuit

The present invention relates to a semiconductor circuit, and more particularly to an electrostatic discharge protection circuit.

With the development of the semiconductor manufacturing process of integrated circuits, the size of semiconductor components has been reduced to the sub-micron stage to improve the performance and operation speed of integrated circuits. However, the reduction of component size has caused some reliability problems, especially The body circuit has the greatest impact on the protection capability of Electrostatic Discharge (ESD). When the size of the device is reduced due to advanced process technology, the protection against electrostatic discharge is also reduced a lot, resulting in a significant reduction in the ESD tolerance of the device. Therefore, an electrostatic discharge protection circuit is needed to protect the components from being damaged by electrostatic discharge. However, the conventional electrostatic discharge protection circuit includes a capacitor-resistor circuit, which occupies a large area, which is not conducive to the reduction of the size of the integrated circuit.

An embodiment of the present invention provides an electrostatic discharge protection circuit, which can be used in a semiconductor device. The semiconductor device has a first drain/source electrode and a second drain/source electrode, and is surrounded by a deep well region. The electrostatic discharge protection circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode of the semiconductor element and a power terminal, and has a first control terminal. The first control terminal is electrically connected to the deep well area, and the first control circuit generates a first control signal. The first discharge circuit is electrically connected between the first drain/source electrode and the power terminal, and is controlled by a first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates a first control signal according to the potential state of the deep well region and the potential state of the first drain/source electrode, and the first discharge circuit A first discharge path between the first drain/source electrode and the power terminal is provided according to the first control signal.

An embodiment of the present invention provides a semiconductor circuit. The semiconductor circuit includes a semiconductor element, a first control circuit, and a first discharge circuit. The semiconductor element is formed in a well region and has a first drain/source electrode and a second drain/source electrode. The well area is surrounded by a deep well area. The well region has a first conductivity type, and the deep well region has a second conductivity type different from the first conductivity type. The electrostatic discharge protection circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode and a power terminal, and has a first control terminal. The first control terminal is electrically connected to the deep well area, and the first control circuit generates a first control signal. The first discharge circuit is electrically connected between the first drain/source electrode and the power terminal, and is controlled by a first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates a first control signal according to a potential state of the deep well region and a potential state of the first drain/source electrode, and the first The discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited below in conjunction with the accompanying drawings, which will be described in detail as follows.

FIG. 1A shows a semiconductor circuit according to an embodiment of the present invention. Referring to FIG. 1A, the semiconductor circuit 1 includes a semiconductor element 10, an electrostatic discharge protection circuit 11, and diodes 12-13. In the embodiment shown in FIG. 1A, the semiconductor device 10 is an N-type transistor, which has a gate electrode G, a drain electrode D, and a source electrode S. In the following, 10 examples of a transistor as a semiconductor element will be used to describe each embodiment. FIG. 2A shows a cross-sectional view of the structure of the transistor 10.

Referring to FIG. 2A, the transistor 10 is formed on the substrate 20, wherein the conductivity type of the substrate 20 is P-type. An N-type deep well region 21 is formed in the base 20, where L21 represents the boundary between the N-type deep well region 21 and the base 20. In the deep well region 21, a P-type well region 22 and an N-type doped region 25 are formed. Two N-type doped regions 23 and 24 are formed in the well region 22, and a gate dielectric layer 26 is formed on the substrate 20 between the doped regions 23 and 24. In this embodiment, the position where the N-type doped region 25 is formed in the deep well region 21 is close to the N-type doped region 23. A gate layer 27 is formed on the gate dielectric layer 26, wherein the gate layer 27 is a metal layer or a polysilicon layer. The doped regions 23 and 24 and the gate layer 27 form the transistor 10. As shown in FIGS. 1A and 2A, the doped region 23 serves as the drain region of the transistor 10, and the contact electrode electrically connected to the doped region 23 serves as the drain electrode D. The doped region 24 serves as the source region of the transistor 10, and the contact electrode electrically connected to the doped region 24 serves as the source electrode S. The contact electrode electrically connected to the gate layer 27 serves as the gate electrode G. In the embodiment of the present invention, a contact electrode CE20 is electrically connected to the doped region 25. When the semiconductor circuit 1 is in the normal operating mode, a high operating voltage VDD is provided to the contact electrode CE20; when the semiconductor circuit 1 is in the abnormal operating mode, the high operating voltage VDD is not provided to the contact electrode CE20, that is, the potential state of the contact electrode CE20 It is floating. According to the cross-sectional view of FIG. 2A, it can be seen that the transistor 10 is formed in the deep well region 21. In detail, the transistor 10 is surrounded by the deep well region 21. Fig. 1A shows the boundary L21, which surrounds the transistor 10, so as to illustrate the arrangement relationship between the transistor 10 and the deep well region 21 in Fig. 2A.

Referring to FIG. 1A again, the cathode of the diode 12 is electrically connected to the drain electrode D of the transistor 10, and the anode is electrically connected to the power terminal T10. The cathode of the diode 13 is electrically connected to the source electrode S of the transistor 10, and its anode is electrically connected to the power terminal T10. When the semiconductor circuit 1 is in the normal operation mode, a low operation voltage VSS or a ground voltage GND is provided to the power supply terminal T10 (in the following, the low operation voltage VSS will be taken as an example to illustrate an embodiment of the present invention); When the circuit 1 is in an abnormal operation mode, no voltage is provided to the power terminal T10, that is, the potential state of the power terminal T10 is floating.

Referring to FIGS. 1A and 2A, the electrostatic discharge protection circuit 11 is electrically connected to the drain electrode D, and includes a control circuit 110 and a discharge circuit 111. The control circuit 110 has a control terminal T11 which is electrically connected to the contact electrode CE20 at the node ND10. In this embodiment, the control circuit 110 includes an inverter 112. The inverter 112 has an input terminal T12 and an output terminal T13, and the input terminal T12 is electrically connected to the control terminal T11 of the control circuit 11. The inverter 112 includes a P-type transistor P110 and an N-type transistor N110. P-type electricity The gate of the crystal P110 is electrically connected to the input terminal T12, its source is electrically connected to the drain electrode D of the transistor 10, and its drain is electrically connected to the output terminal T13. The gate of the N-type transistor N110 is electrically connected to the input terminal T12, its drain is electrically connected to the output terminal T13, and its source is electrically connected to the power terminal T10. The discharge circuit 111 includes an N-type transistor N111. The gate of the N-type transistor N111 is electrically connected to the output terminal T13 of the inverter 112, its drain is electrically connected to the drain electrode D of the transistor 10, and its source is electrically connected to the power terminal T10. Based on the connection between the circuit structure of the control circuit 110 and the transistor 10, the control circuit 110 generates the control signal S10 according to the potential state of the deep well region 21 and the potential state of the drain electrode D or the potential state of the power terminal T10. Please refer to the following text for related descriptions.

When the semiconductor circuit 1 is in an abnormal operation mode, the high operating voltage VDD is not provided to the contact electrode CE20, and no voltage is provided to the power terminal T10, that is, the potential states of the contact electrode CE20 and the power terminal T10 are both floating. Since the input terminal T12 of the inverter 112 is electrically connected to the contact electrode CE20 through the control terminal T11 and the node ND10, the input terminal T12 is also in a floating state, so that the P-type transistor P110 is turned on and the N-type transistor N110 is turned off. When an electrostatic discharge event occurs on the drain electrode D, the potential of the drain electrode D increases instantly. Through the turned-on P-type transistor P110, the output terminal T13 is in a high voltage state, that is, the control signal S10 has a high voltage level. The N-type transistor N111 is turned on according to the high voltage level control signal S10, so that there is a discharge path between the drain electrode D and the power terminal T10. The electrostatic charge on the drain electrode D is conducted to the power terminal T10 through the discharge path, thereby protecting the circuit or element coupled to the transistor 10 from the electrostatic charge.

In this embodiment, when the semiconductor circuit 1 is in an abnormal operation mode and an electrostatic discharge event occurs on the drain electrode D, since the N-type transistor N111 is turned on and the connection structure of the diode 13 (its anode is electrically connected) Power terminal T10, and its cathode electrical property The source electrode S) is connected, and another discharge path is formed between the power terminal T10 and the source electrode S. Therefore, when an electrostatic discharge event occurs on the drain electrode D, the electrostatic charge on the drain electrode D can be conducted to the source electrode S in addition to the power terminal T10.

When the semiconductor circuit 1 is in the normal operation mode, the high operating voltage VDD is provided to the contact electrode CE20 and the low operating voltage VSS is provided to the power terminal T10, that is, the contact electrode CE20 is in a high potential state, and the power terminal T10 is in a low potential state. In the normal operation mode, since the input terminal T12 of the inverter 112 is electrically connected to the contact electrode CE20 through the control terminal T11 and the node ND10, the input terminal T12 is in a high potential state, so that the N-type transistor N110 is turned on and the P-type transistor is turned on. P110 is closed. The output terminal T13 is at a low level based on the low operating voltage VSS, that is, the control signal S10 has a low voltage level. The N-type transistor N111 is turned off according to the control signal S10 of the low voltage level. In the normal operation mode, since the N-type transistor N111 is turned off, the drain electrode D and the power terminal T10 do not have a discharge path, that is, the aforementioned discharge path is blocked.

In other embodiments, the electrostatic discharge protection circuit 11 is also electrically connected to the source electrode S. In this embodiment, as shown in FIG. 2B, an N-type doped region 28 is further formed in the deep well region 21, and a contact electrode CE21 is electrically connected to the doped region 28. When the semiconductor circuit 1 is in the normal operation mode, the high operation voltage VDD is supplied to the contact electrode CE21; when the semiconductor circuit 1 is in the abnormal operation mode, the high operation voltage VDD is not supplied to the contact electrode CE21, that is, the potential state of the contact electrode CE21 is Floating. In this embodiment, the position where the N-type doped region 28 is formed in the deep well region 21 is close to the N-type doped region (source region) 24. Referring to FIG. 1B, the electrostatic discharge protection circuit 11 further includes a control circuit 113 and a discharge circuit 114. The control circuit 113 has a control terminal T14 which is electrically connected to the contact electrode CE21 at the node ND11. The control circuit 113 includes an inverter 115. The inverter 115 has an input terminal T15 and an output terminal T16, and the input terminal T15 is electrically connected to the control circuit 113's control terminal T14. The inverter 115 includes a P-type transistor P113 and an N-type transistor N113. The gate of the P-type transistor P113 is electrically connected to the input terminal T15, its source is electrically connected to the source electrode S of the transistor 10, and its drain is electrically connected to the output terminal T16. The gate of the N-type transistor N113 is electrically connected to the input terminal T15, its drain is electrically connected to the output terminal T16, and its source is electrically connected to the power terminal T10. The discharge circuit 114 includes an N-type transistor N114. The gate of the N-type transistor N114 is electrically connected to the output terminal T16 of the inverter 115, its drain is electrically connected to the source electrode S of the transistor 10, and its source is electrically connected to the power terminal T10. Based on the connection between the circuit structure of the control circuit 113 and the transistor 10, the control circuit 113 generates the control signal S11 based on the potential state of the deep well region 21 and the potential state of the source electrode S or the potential state of the power terminal T10. Please refer to the following text for related descriptions.

When the semiconductor circuit 1 is in an abnormal operation mode, the high operating voltage VDD is not provided to the contact electrode CE21, and no voltage is provided to the power terminal T10, that is, the potential states of the contact electrode CE21 and the power terminal T10 are both floating. Since the input terminal T15 of the inverter 115 is electrically connected to the contact electrode CE21 through the control terminal T14 and the node ND11, the input terminal T15 is also in a floating state, so that the P-type transistor P113 is turned on and the N-type transistor N113 is turned off. When an electrostatic discharge event occurs on the source electrode S, the potential of the source electrode S increases instantly. Through the turned-on P-type transistor P113, the output terminal T16 is in a high voltage state, that is, the control signal S11 has a high voltage level. The N-type transistor N114 is turned on according to the control signal S11 of the high voltage level, so that there is a discharge path between the source electrode S and the power terminal T10. The electrostatic charge on the source electrode S is conducted to the power terminal T10 through the discharge path, thereby protecting the circuit or element coupled to the transistor 10 from the electrostatic charge.

In this embodiment, when the semiconductor circuit 1 is in an abnormal operation mode and an electrostatic discharge event occurs on the source electrode S, since the N-type transistor N114 conducts The connection structure of the two-electrode body 12 (its anode is electrically connected to the power terminal T10, and its cathode is electrically connected to the drain electrode D), and another discharge path is formed between the power terminal T10 and the drain electrode D. Therefore, when an electrostatic discharge event occurs on the source electrode S, the electrostatic charge on the source electrode S can be conducted to the drain electrode D in addition to the power terminal T10.

When the semiconductor circuit 1 is in the normal operation mode, the high operating voltage VDD is provided to the contact electrode CE21 and the low operating voltage VSS is provided to the power terminal T10, that is, the contact electrode CE21 is in a high potential state, and the power terminal T10 is in a low potential state. In the normal operation mode, since the input terminal T15 of the inverter 115 is electrically connected to the contact electrode CE21 through the control terminal T14 and the node ND11, the input terminal T15 is in a high potential state, so that the N-type transistor N113 is turned on and the P-type transistor is turned on. P113 is closed. The output terminal T16 is at a low level based on the low operating voltage VSS, that is, the control signal S11 has a low voltage level. The N-type transistor N114 is turned off according to the control signal S11 of the low voltage level. In the normal operation mode, since the N-type transistor N114 is turned off, the source electrode S and the power terminal T10 do not have a discharge path, that is, the aforementioned discharge path is blocked.

In other embodiments, the electrostatic discharge protection circuit electrically connected to the drain electrode D of the transistor 10 has other circuit structures. Referring to FIGS. 1A and 3, compared with FIG. 1A, the control circuit 110' of the electrostatic discharge circuit 11 in FIG. 3 further includes an inverter 300. The inverter 300 has an input terminal T30 and an output terminal T31, and the input terminal T30 is electrically connected to the output terminal T13 of the inverter 112. The inverter 300 includes a P-type transistor P300 and an N-type transistor N300. The gate of the P-type transistor P300 is electrically connected to the input terminal T30, its source is electrically connected to the drain electrode D of the transistor 10, and its drain is electrically connected to the output terminal T31. The gate of the N-type transistor N300 is electrically connected to the input terminal T30, its drain is electrically connected to the output terminal T31, and its source is electrically connected to the power terminal T10. In addition, based on the structure of the control circuit 110', the discharge circuit 111' of the electrostatic discharge circuit 11 in Figure 3 includes Including the P-type transistor P301, which replaces the N-type transistor N111 in Figure 1A. Referring to Figure 3, the gate of the P-type transistor P301 is electrically connected to the output terminal T31 of the inverter 300, its source is electrically connected to the drain electrode D of the transistor 10, and its drain is electrically connected to the power terminal T10 .

Refer to the description of Figure 1A above, in the abnormal operation mode, the high operating voltage VDD is not provided to the contact electrode CE20, and no voltage is provided to the power supply terminal T10, that is, the potential states of the contact electrode CE20 and the power supply terminal T10 are both Floating. When an electrostatic discharge event occurs on the drain electrode D, the output terminal T13 of the inverter 112 is in a high potential state. According to the high potential state of the output terminal T13, the N-type transistor N300 is turned on, and the P-type transistor P300 is turned off. Through the turned-on N-type transistor N300, the output terminal T31 is at a low voltage level based on the floating state of the power terminal T10, that is, the control signal S10' has a low voltage level. The P-type transistor P301 is turned on according to the control signal S10' of the low voltage level, so that there is a discharge path between the drain electrode D and the power terminal T10. The electrostatic charge on the drain electrode D is conducted to the power terminal T10 through the discharge path, thereby protecting the circuit or element coupled to the transistor 10 from the electrostatic charge.

In this embodiment, when the semiconductor circuit 1 is in an abnormal operation mode and an electrostatic discharge event occurs on the drain electrode D, since the P-type transistor P301 is turned on and the connection structure of the diode 13 (the anode is electrically connected The power terminal T10, and its cathode is electrically connected to the source electrode S), and another discharge path is formed between the power terminal T10 and the source electrode S. Therefore, when an electrostatic discharge event occurs on the drain electrode D, the electrostatic charge on the drain electrode D can be conducted to the source electrode S in addition to the power terminal T10.

Similarly, referring to the previous description of Figure 1A, when the semiconductor circuit 1 is in the normal operation mode, the high operating voltage VDD is provided to the contact electrode CE20 and the low operating voltage VSS is provided to the power terminal T10, that is, the contact electrode CE20 is at a high potential. State, and the power terminal T10 is in a low potential state. In the normal operation mode, the output terminal T13 is in a low potential state. According to the low potential state of the output terminal T13, the P-type transistor P300 is turned on, and the N-type transistor N300 is turned off. Through the turned-on P-type transistor P300, the output terminal T31 is at a high voltage level based on the potential of the drain electrode D when the transistor 10 is operating, that is, the control signal S10' has a high voltage level. The P-type transistor P301 is turned off according to the control signal S10' of the high voltage level. In the normal operation mode, since the P-type transistor P301 is turned off, the drain electrode D and the power terminal T10 do not have a discharge path, that is, the aforementioned discharge path is blocked.

According to the above-mentioned embodiment, the electrostatic discharge protection circuit of this case does not have a capacitor-resistor circuit used in the prior art, and therefore occupies a smaller area.

Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone familiar with the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

1: Semiconductor circuit

10: Semiconductor components

11: Electrostatic discharge protection circuit

12, 13: Diode

20: Base

21: N-type deep well area

22: P-type well area

23: N-type doped region (drain region)

24: N-type doped region (source region)

25: N-type doped region

26: Gate dielectric layer

27: Gate layer

28: N-type doped region

110, 110’: Control circuit

111, 111’: Discharge circuit

112: Inverter

113: control circuit

114: Discharge circuit

115, 300: Inverter

CE20, CE21: contact electrode

D: Drain electrode

G: Gate electrode

GND: Ground voltage

L21: Border

N110, N111, N113, N114, N300: N-type transistor

ND10, ND11: Node

P110, P113, P300, P301: P-type transistor

S: source electrode

S10, S10', S11: control signal

T10: power terminal

T11, T14: control terminal

T12, T15, T30: input terminal

T13, T16, T31: output terminal

VDD: High operating voltage

VSS: Low operating voltage

FIG. 1A shows a semiconductor circuit according to an embodiment of the present invention. FIG. 1B shows a semiconductor circuit according to another embodiment of the present invention. FIG. 2A shows a cross-sectional view of the structure of a transistor according to an embodiment of the present invention. FIG. 2B shows a cross-sectional view of the structure of a transistor according to another embodiment of the present invention. Figure 3 shows a semiconductor circuit according to another embodiment of the present invention.

1: Semiconductor circuit

10: Semiconductor components

11: Electrostatic discharge protection circuit

12, 13: Diode

110: control circuit

111: Discharge circuit

112: Inverter

D: Drain electrode

G: Gate electrode

GND: Ground voltage

L21: Border

N110, N111: N-type transistor

ND10: Node

P110: P-type transistor

S: source electrode

S10: Control signal

T10: power terminal

T11: Control terminal

T12: input

T13: output

VSS: Low operating voltage

Claims (22)

An electrostatic discharge protection circuit for a semiconductor element, the semiconductor element having a first drain/source electrode and a second drain/source electrode, and surrounded by a deep well region, including: A first control circuit is electrically connected between the first drain/source electrode of the semiconductor element and a power terminal, and has a first control terminal, wherein the first control terminal is electrically connected to the deep well region , And the first control circuit generates a first control signal; and A first discharge circuit electrically connected between the first drain/source electrode and the power terminal and controlled by the first control signal; Wherein, when an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control circuit according to a potential state of the deep well region and a potential state of the first drain/source electrode A control signal, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal. For example, the electrostatic discharge protection circuit of claim 1, wherein the first control circuit includes: A first inverter electrically connected between the first drain/source electrode and the power terminal, and has a first input terminal and a first output terminal; Wherein, the first input terminal is electrically connected to the first control terminal; and Wherein, the first inverter determines a voltage of the first output terminal according to the potential state of the deep well region, selectively based on the potential state of the first drain/source electrode or a potential state of the power terminal, And the first control circuit generates the first control signal according to the voltage of the first output terminal. The electrostatic discharge protection circuit of claim 2, wherein, when the electrostatic discharge event occurs on the first drain/source electrode, the first inverter is based on the potential state of the first drain/source electrode The first control signal is generated to control the discharge circuit to provide the first discharge path. For example, the electrostatic discharge protection circuit of claim 3, wherein the electrostatic discharge event occurs during a period during which the potential state of the deep well region is a floating state. Such as the electrostatic discharge protection circuit of claim 2, wherein, when the semiconductor element is in a normal operation mode, the first inverter generates the first control signal based on the potential state of the power terminal to control the resistance of the discharge circuit Disconnect the first discharge path. Such as the electrostatic discharge protection circuit of claim 5, wherein, in the normal operation mode, the deep well area receives an operating voltage. The electrostatic discharge protection circuit of claim 2, wherein the first inverter includes: a first P-type transistor having a control electrode electrically connected to the first input terminal, and electrically connected to the first drain/source A first electrode of the pole electrode and a second electrode electrically connected to the first output terminal; and a first N-type transistor having a control electrode electrically connected to the first input terminal and electrically connected to the first output terminal A first electrode of the output terminal and a second electrode of the power terminal are electrically connected. The electrostatic discharge protection circuit of claim 7, wherein the first discharge circuit includes: a second N-type transistor having a control electrode electrically connected to the first output terminal, and electrically connected to the first drain/source electrode Of a first electrode, and electrically connected to the power terminal A second electrode. The electrostatic discharge protection circuit of claim 2, wherein the first control circuit further includes: a second inverter, electrically connected to the first drain/source electrode and the power terminal, and has a second input terminal And a second output terminal; wherein the second input terminal is electrically connected to the first output terminal; and wherein the second inverter is selectively based on the first output terminal according to the voltage of the first output terminal / The potential state of the source electrode or the potential state of the power terminal to generate the first control signal. For example, the electrostatic discharge protection circuit of claim 1, further comprising: a second control circuit, which is electrically connected between the second drain/source electrode of the semiconductor element and the power terminal, and has a second control terminal, Wherein, the second control terminal is electrically connected to the deep well region, and the second control circuit generates a second control signal; and a second discharge circuit is electrically connected to the second drain/source electrode and the power terminal And controlled by the second control signal; wherein, when the electrostatic discharge event occurs on the second drain/source electrode, the second control circuit is based on the potential state of the deep well region and the second drain /Source electrode is a potential state to generate the second control signal, and the second discharge circuit provides a second discharge between the second drain/source electrode and the power terminal according to the second control signal path. For example, the electrostatic discharge protection circuit of claim 1, further comprising: a diode having an anode terminal electrically connected to the power terminal and a cathode terminal electrically connected to the second drain/source electrode; wherein, it is used as the first When the electrostatic discharge event occurs on the drain/source electrode, a second discharge path is formed between the power terminal and the second drain/source electrode via the diode between. A semiconductor circuit includes: a semiconductor element formed in a well region and having a first drain/source electrode and a second drain/source electrode, wherein the well region is surrounded by a deep well region, and the well region Having a first conductivity type, and the deep well region has a second conductivity type different from the first conductivity type; a first control circuit electrically connected between the first drain/source electrode and a power terminal , And has a first control terminal, wherein the first control terminal is electrically connected to the deep well region, and the first control circuit generates a first control signal; and a first discharge circuit is electrically connected to the first drain / Between the source electrode and the power terminal and controlled by the first control signal; wherein, when an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit is based on the deep well region A potential state of the first drain/source electrode and a potential state of the first drain/source electrode to generate the first control signal, and the first discharge circuit provides the first control signal between the first drain/source electrode and the A first discharge path between the power terminals. The semiconductor circuit of claim 12, wherein the first control circuit includes: a first inverter electrically connected between the first drain/source electrode and the power terminal, and has a first input terminal and A first output terminal; wherein the first input terminal is electrically connected to the first control terminal; and wherein the first inverter is selectively based on the first drain/source according to the potential state of the deep well region The potential state of the pole electrode or a potential state of the power terminal determines a voltage of the first output terminal, and the first control circuit is based on the first output terminal Voltage to generate the first control signal. The semiconductor circuit of claim 13, wherein, when the electrostatic discharge event occurs on the first drain/source electrode, the first inverter generates the first drain/source electrode based on the potential state The first control signal is used to control the discharge circuit to provide the first discharge path. The semiconductor circuit of claim 14, wherein the electrostatic discharge event occurs during a period during which the potential state of the deep well region is a floating state (floating). The semiconductor circuit of claim 13, wherein, when the semiconductor element is in a normal operation mode, the first inverter generates the first control signal based on the potential state of the power terminal to control the discharge circuit to block the The first discharge path. Such as the semiconductor circuit of claim 16, wherein, in the normal operation mode, the deep well region receives an operating voltage. The semiconductor circuit of claim 13, wherein the first inverter includes: a first P-type transistor having a control electrode electrically connected to the first input terminal, and electrically connected to the first drain/source electrode A first electrode and a second electrode electrically connected to the first output terminal; and a first N-type transistor having a control electrode electrically connected to the first input terminal, and a control electrode electrically connected to the first output terminal A first electrode and a second electrode electrically connected to the power terminal. The semiconductor circuit of claim 18, wherein the first discharge circuit includes: a second N-type transistor having a control electrode electrically connected to the first output terminal, A first electrode electrically connected to the first drain/source electrode and a second electrode electrically connected to the power terminal. The semiconductor circuit of claim 13, wherein the first control circuit further includes: a second inverter electrically connected to the first drain/source electrode and the power terminal, and has a second input terminal and a Second output terminal; wherein, the second input terminal is electrically connected to the first output terminal; and wherein, the second inverter is selectively based on the first drain/source according to the voltage of the first output terminal The potential state of the pole electrode or the potential state of the power terminal generates the first control signal. For example, the semiconductor circuit of claim 12, further comprising: a second control circuit, which is electrically connected between the second drain/source electrode of the semiconductor element and the power terminal, and has a second control terminal, wherein, The second control terminal is electrically connected to the deep well region, and the second control circuit generates a second control signal; and a second discharge circuit is electrically connected between the second drain/source electrode and the power terminal, And controlled by the second control signal; wherein, when the electrostatic discharge event occurs on the second drain/source electrode, the second control circuit is based on the potential state of the deep well region and the second drain/source A potential state of the electrode electrode generates the second control signal, and the second discharge circuit provides a second discharge path between the second drain/source electrode and the power terminal according to the second control signal. For example, the semiconductor circuit of claim 12, further comprising: a diode having an anode terminal electrically connected to the power terminal and a cathode terminal electrically connected to the second drain/source electrode; Wherein, when the electrostatic discharge event occurs on the first drain/source electrode, a second discharge path is formed between the power terminal and the second drain/source electrode via the diode.

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