TW584922B - Method of manufacturing semiconductor package - Google Patents

Abstract

A method of manufacturing semiconductor package comprising a curing process by means of a clamping apparatus with a cavity used to accommodate a submold and at least one exhaust passage for connecting the submode to an external exhauster is provided. As a chip carrier that is attached a plurality of semiconductor dies puts into the clamping apparatus to perform curing process, air removed through the submold and the exhaust passage makes a negative environment of the cavity. The negative environment of the cavity in a manner that brings an attraction, allowing balancing the excessive thermal stress of the chip carrier during curing process. So as to avoid warpage of the chip carrier or delamination and making planarity of the carrier better is performed, and then the working quality of solder reflow and test to be enhanced.

Description

584922 V. Description of the Invention (1) [Field of Invention] The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package with a special 'Jig' applied to an on-chip operation (Attachment). [Background of the invention]: Ball grid array (BGA) semiconductor package (Ball Gri (i Array

(Semiconductor Package) is a packaging structure where most of the solder balls (solder Bal 1) are arranged in a matrix on the bottom surface of the substrate for the semiconductor chip to be electrically connected to an external printed circuit board (PCB). Lead-frame) semiconductor devices have denser I / O connect terminals and can accommodate semiconductor chips with more electronic circuits and electronic components, which is more suitable for high functionality and high processing speed. The demand for electronic products has become the mainstream of packaging in the future. However, in order to reduce the process cost, the ball grid array package manufacturing method generally used in the industry is made in batch type, which mainly includes the following steps: first prepare a matrix strip (Matrix Strips), which is defined in advance Draw out a number of substrate units for wafer loading; repeat the wafer loading operation 'adhere a plurality of semiconductor wafers to each substrate unit by an adhesive' and implement a baking process (curing) to stabilize each wafer It is fixed on the matrix substrate for its carrying;

Bonding) enables the semiconductor wafer to form an electrical connection with the substrate, and then a molding gel is used to completely cover the semiconductor wafer. Finally, the bottom of the substrate is planted and cut to form a plurality of ball grid array semiconductor packages. Pieces.

Page 5 584922 5. Description of the invention (2) However, after the semiconductor wafer of the above-mentioned manufacturing method is borrowed from an adhesive substrate, in order to prevent the wafer from talking about the matrix position in the subsequent process, a high temperature baking operation must be performed so that Adhesives can be used to stabilize the wafer to the surface of the substrate: ^ At high temperature, the substrate with multiple semiconductor wafers is placed in the j 1 fixture (Jig Fixture). It is held in order to be sent to the oven (〇ve ~ fixture. The fixture is a clamping ^ mold with an upper mold and an opposite lower mold and a mold cavity (M 〇 1 d C a ν ity) is recessed, so when誃 ,, Α, and " The lower part of the substrate is uniformly heated in the center of the substrate. '', Containing the only two-conductor wafer system-made of high-purity silicon material, its heat (Coefflclent of Thermal Expansion, CTE) The coefficient is 3 ppm / X), and the matrix substrate is mostly made of glass fiber, fr ~ ,,,, polyimide and epoxy resin (Epoxy), and its thermal expansion is The coefficients range from 18 to 50 ppm / t. 4 When the ancient materials are warmly baked, the substrate undergoes excessive thermal stress and often loses its planarity (Coplanarity), causing the package semi-finished product to warp (Wa'rpag ^, causing the wafer and substrate bonding layer to peel (Delaminati)) and even Unexpected phenomena such as die crack, which seriously jeopardizes the quality of the package. 0 In addition, the package is applied to high-end products such as digital cameras or laser printers. At times, it is often necessary to use a flexible substrate (Thin Substrate) or a thin substrate (Thin Substrate) with a moderate flexibility as a wafer carrier.

16124.ptd Page 6 584922 V. Description of the invention (3) ____ Rigidity is insufficient and has baking operation. If the substrate only relies on the peripheral part to provide 2 properties: the substrate is held in the center for wafer bonding All other parts are suspended in the second door, and the degree of the upper and lower molds is bound to be more serious. It is said that the U carrier cannot be seized: at 2 o’clock, the uniform coplanarity is often planted with C SeIf-Allgnfflent, errors, etc., and after entering the test stage, the testers (Conductors) will The plane formed by the end ==, the 7-point test contact cannot fully touch the test solder ball, resulting in a measurement from 2. 1;, the test results are reliable 3 'Traditional packaging semi-finished products With each batch of substrates carrying = different size and shape, as well as the material characteristics of the substrates, fc white must be replaced at the time when baking semi-finished products suitable for this Not only increase the complexity of the process, but also the same baking; species ^ production and production process under the framework of mass production without = = clever in the existing design [Summary of Invention]: heart and clothing ° The main purpose of the present invention is to provide a way to avoid baking -Curved or even delaminated during operation to prevent the manufacturing method of the crystal array semiconductor package and the new method applied to the manufacturing method ::, ball grid array Another object of the present invention is to provide a kind of reliability and reliability: Surface connection; Freshness; Ball grid = Semiconductor package manufacturing method and its application Another purpose of the present invention is to provide-only need to change the fixture;

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584922 A semiconductor-encapsulated ball grid array is mounted on a wafer, and at least half of the substrate is moved into a fixture, which communicates with the sub and a plurality of these exhausts, and orders the fixture to a negative pressure environment; each semiconductor is provided for molding. Finally, a single process is performed, that is, the manufacturing method, and the cavity space phase of the sub-mold is placed in the cavity of the sub-mold through the top surface. The vacuum is produced on the sub-mold. 5. Description of the invention (< It is applied to the system to achieve the above-mentioned method. It consists of a plurality of bases and a single baking for each substrate. The rule, in which, the exhaust air hole, $, and an external air through hole pass through this, and then a guide is applied. In order to provide the colloid for covering the majority of fresh balls with a ball grid array, the hole augmentation in the cavity space of the present invention directly starts the external row carrying the wafer and the exhaust gas leads to different types of semi-jig cost inside the jig. The novel treatment and other items include: prepare a board unit; use the upper element; then there is a substrate semiconductor wafer which is pumped by the sub-rule and the exhaust channel is connected to the exhaust channel of the exhaust device to carry out the welding process. Assume Substrate-bottom semiconductor packaging eliminates the traditional matrix-type substrate gas device that has a swap-through penetrating mold on the top surface, so that the mold path is ejected from the fixture to form a ball grid array with a negative-pressure conductor sealing member. The matrix substrate of the present invention An adhesive will divide the substrate replacement sub-mold and a flat second surface prop with a continuous second end portion to form a plurality of bonding wire units, and perform cutting on the bonding wire surfaces. Replace the jig sub-mold; due to the inversion of the cavity with the jig, the air passes outside; then, the environment, further, to simplify the assembly method and the pre-defined body chip bonding on the semiconductor package, implement the exhaust of the high-temperature mold. The first inner air of the through hole on the top surface is pumped to bake the cold body wafer. The electrical industry uses a packaging ball planting operation to obtain a plurality of molds on the jig. The air hole will increase suction to induce a suction.

16124.ptd Page 8 584922 V. Description of the invention (5) ^ When the substrate is fork-heated and warm-baked and excessive thermal stress is generated, the suction force i 2 of the top surface of the sub-mold is equal to the thermal stress, which can enable each semiconductor wafer and load The substrates are all attached to the top surface of the sub-mold. After the bake and cooling, the substrate and the package μ $ = white! I! Maintain a good flatness without warping, delamination or even crystal right J11. At the same time, the excellent flatness of the substrate can also allow all solder balls to be accurately misaligned by 4 M ^ β. Freshly connected to the corresponding substrate position can further improve the quality reliability of the ball-planting operation and test stage. Second G 俨 3: The above-mentioned sub-mold system-removable mechanism, & current batch and thickness changes or wafer size, thick pieces can be selected for sub-mold replacement. At the same time, it is equipped with a variety of tedious manufacturing processes that cost two days at a time, and there is no need to increase mass production according to the packaging target to: ;;:;: It can significantly shorten the time and cost of sealing clothes, and meet the needs of the market. [Detailed description of the invention] Now, the embodiment is used to illustrate the t A # Z ,,, and field of the semiconductor package. The ball grid array of the present invention is simplified and the second application is: a novel fixture of the manufacturing method. However, in the following contents, the "r-style" of the basin meeting shows the opening of the right part of the method of the present invention: "The number of components covered by the process of the international seal # process # related 70-piece relationship is bound to be even more complex. Lane, component layout, and element flow = Used to show the work of the V step body sealing method of each step of this embodiment 10 and right, as shown in Figure 1A, prepare a matrix type 4 4 with a front 104 And an opposite back surface 105, 2 plate 10, the substrate π secant 1 0 0 in the

584922 V. Description of the invention (6) ^ ~ A plurality of substrate units 10 are arranged on the front surface of the substrate 1 0 4 in advance. In this embodiment, a matrix formula with twelve substrate units is arranged in a 2 × 6 array. 10 substrates are explained. Each substrate unit i 〇 丨 is preset with a wafer bonding area 1 〇2 for providing wafer connection, and a conductive connection area for a plurality of conductive traces (not shown) is arranged on the outside. The conductive traces pass through most of the vias (not shown) inside the substrate 10 and are electrically connected to most of the bonding pads (not shown) on the back surface 105 of the substrate 10. The matrix substrate 10 suitable for this embodiment may be made of plastic materials such as epoxy resin, glass fiber, polyurethane resin or FR-4 resin, or ceramics, glass materials, etc. However, plastic substrates are inexpensive and good Processing and other advantages gradually occupy the mainstream market position. Thereafter, as shown in FIG. 1B, a plurality of semiconductor wafers i J each having a first surface 1 10 and a second surface 1 1 1 are prepared, and a thermal bonding is covered in each of the wafer adhesion regions 10 2. The adhesive 12 is used for each wafer. The second surface ^ is adhered to the matrix substrate 10, and then the matrix substrate 10 carrying the wafers (the semi-finished product 1 of the package) is moved into the package provided by the present invention. Bake in a jig (as shown in Figure 1C and Figure 13). As shown in FIG. 1C, the jig 13 is composed of an upper mold i30 and a lower mold 1 31 clamped to the upper mold 1 30. A mold for a child is provided in the lower mold 1 31. The mold cavity 14 and the plurality of wafers 11 are provided with a cavity 1 3 2 and at least one exhaust channel 1 μ that connects the sub mold 14 to an external exhaust device (not shown). Wherein, the sub-mold 14 is a replaceable device, which has a flat top surface 140 and a plurality of pumps which penetrate the sub-mold 14 top surface 1 40 and communicate with the cavity 1 32. The air vent hole 141 and the 5H exhaust passage 133 have two opposite ends, one of which is connected to

16124.ptd Page 10 584922 V. Description of the invention (7) The exhaust vent holes 1 4 1 are connected, and the other end is opened in the miniature valve 1 3 1 of the miniature valve 1 3 4 (M ini-Va 1 ve ) And an external exhaust device (not shown) such as a vacuum pump. After the substrate carrying most semiconductor wafers 丨 is placed in the jig 1 3 and the wafer 1 1 first surface 1 1 is flatly attached to the top surface of the sub-mold 1 40, it will be started. The exhaust device opens the micro valve 1 34, and the air in the cavity 132 is exhausted from the jig through the exhaust through hole ^ through the top surface ^ 40 and the exhaust channel 1 33! 3 outside and a negative pressure environment is formed in the cavity 1 32, which causes the sub-mold 14 to generate a reverse suction at the top surface 14 0, the sub-mold 丨 4 the top surface 1 4 0 suction is just enough to balance the substrate 丨〇 Excessiveness caused by high temperature baking

The thermal stress makes each wafer 1 丨 the first surface i 丨 〇 flat and fit on the top surface of the sub-mold yo 4 to avoid warping, delamination, and even wafer cracking of the packaged semi-finished product after baking. 1〇 What is it? The semi-finished packages of the previous and subsequent batches of the operation often have a surface of 4 and a quotient of ^^ h due to the difference in the substrate i = U or the type of semiconductor wafer 11 carried by it. The surface of 丄 4 is appropriately fitted, and the lower grip height h is repeated% 辂 + ^ 131 of the mold 鬲 鬲 H H must be adjusted according to the height of the semi-finished product and η. The present invention should be packaged in different types, and the seven molds 13 of the mold 14 can be fitted with a half-mouth mouth Λ ^ σ mouth, as shown in Figure 1 D, when the batch A is sealed

When baking products, say 4 Ding—the batch (such as Batch B) must be modified and set i, and the mold height h 'must be changed to a suitable mold 1 4 without the fixture. Unloading the complicated items can also greatly save the time required for warp roasting and shorten the mass production time. Pressure return to the outside = 气 3 装 =; = Exhaust device makes the inner force of the cavity 132 PT lock valve 1 3 4 This package is half

584922 V. Description of the invention (8) Product 1 is removed from the jig for wire bonding. As shown in the figure, the first surface 1 1 0 and the substrate 10 of each semiconductor wafer 11 are respectively welded with a plurality of conductive wires 15 such as gold wires, and the semiconductor wafers 11 and 1 are repeatedly subjected to a molding process. The lead wire 15 is completely covered with an encapsulating gel 16 and air-tightly isolated from the outside, and the ball-planting operation can be continued. As shown in Figure 1F, the matrix substrate 10 will not maintain a good flatness due to the charm caused by warm baking, and then automatically repositions a plurality of solder balls i 7 arranged in an array by automatic alignment. When most of the freshness on the back of the substrate 10 is 10 6 'Each fresh pad 10 6 can be soldered to the opposite hemp solder ball 1 7 to prevent it from being misaligned or inaccessible'. After entering the test phase, the bottom of each solder ball 7 can also form a plane ^ for each contact 180 in the testing machine 18 to accurately and conductively contact the solder ball 7 to be tested. Finally, the singulation step is implemented. Referring to FIG. 丨, the planting ball is completed into a matrix substrate with a 2 × 6 row and column configuration, and cut into 12 semiconductor packages (not shown) along a preset dividing line 100. That is, the manufacturing method of the ball grid array abundant conductor package of the present invention is completed. The above description is only an embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is the definition; the application below is called “Patent Offering” and any other technology or method that is the same as or equivalent to the scope of patent application described below will be deemed to be covered by this scope. π ~ worship

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584922 Schematic description [Schematic description]: Figures 1 A to 1 F are schematic diagrams of the manufacturing process of the ball grid array semiconductor package of the present invention. [Symbols of main components]: 1 Package semi-finished product 10 Matrix substrate 100 Dividing line 101 Substrate unit 102 Wafer bonding area 103 Wire connection area 104 Front surface of substrate 105 Back surface of substrate 106 Solder pad 11 Semiconductor wafer 110 First surface of wafer 111 Second surface of wafer 12 Thermal bonding adhesive 13 Fixture 130 Upper mold 131 Lower mold 132 Cavity 133 Exhaust channel 134 Void valve 14 Sub-mold 140 Sub-mold top surface 141 Exhaust through hole 15 Wire 16 Encapsulated gel 17 Solder ball 18 Test Machine 180 test contactΗ Cavity degree of lower mold h Package semi-finished product 1¾ degree h, sub mold degree

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Claims (1)

584922 6. Scope of patent application 1. A method for manufacturing a semiconductor package includes the following steps: A wafer carrier is prepared, which has a front surface and a back surface. A plurality of substrate units are defined on the front surface for bonding. The agent is applied to adhere a plurality of semiconductor wafers to each substrate unit; the wafer carrier is clamped in a jig, wherein the jig system has a sub-die and at least one communicating with the sub-die to an external exhaust device An exhaust channel for the air in the jig to pass through the sub-die and be eliminated by the exhaust channel when the wafer is baked, so that a negative pressure environment is formed in the jig; most of the first conductive elements are electrically connected to the semiconductor wafers To the a chip carrier; encapsulating the semiconductor wafer and most conductive elements with an encapsulating gel; 7 most of the second conductive elements are planted on the back of the wafer carrier; and applying the wafer carrier Singulation operation: forming a plurality of semiconductor packages. 2. The method for manufacturing a semiconductor package according to item 1 of the patent, wherein the package is a BaU Grid Array (BGA) semiconductor package. 3 ::::: The semiconductor package manufacturing method according to the first item, wherein the Japanese-Japanese wafer carrier is a matrix substrate. 4. The method for manufacturing a semiconductor package according to item 1, wherein the adhesive is a heat-bonding adhesive. 5. Such as the scope of patent application! Item of the method of manufacturing a semiconductor package, wherein the 584922 τ Please patent scope The fixture is composed of an upper mold and a lower mold, and the lower mold is not provided with a mold cavity for the sub mold and the wafers. Sigh, as in the method of manufacturing a semiconductor package in item 1 of the patent application, the sub-mold is a replaceable device to sub-molds of the appropriate height according to the different semiconductor packages. The method of manufacturing the semiconductor package according to item 1 of the patent application range includes a top surface of the mold and a plurality of exhaust holes through which the top surface passes through the top surface of the fixture. Sentence As in the method for manufacturing a semiconductor package according to item 1 or 7 of the scope of patent application, the bundle wafer carrier is clamped in the fixture in an inverted manner, so that the conductor wafer is flat on the top surface of the sub-mold. Early 7 each. For example, the method of manufacturing the semiconductor package of item 2 of the patent range 2 The exhaust channel has two opposite ends, and the device is equipped with ^^ T. One of the ends is connected to the other end of the Val ' It is opened in a miniature valve (Mini-in ^) and externally connected to the external exhaust device. The semiconductor package manufacturing method of this item is a gold wire. For example, the scope of the patent application No. 1 顼 I soil two conductive elements is a method of manufacturing solder ball semiconductor packages-a clamping device for baking, which includes:-can be used in the upper mold; for lower solid mold, the lower There is a sub-mold inside the mold, which is housed in the cavity; and 6. 8 · 1 · 12 584922 6. The scope of patent application is at least one exhaust channel, which is opened inside the lower mold to connect the sub-mold to an external exhaust device. The air in the cavity is discharged from the sub-mold through the exhaust channel to make the A negative pressure environment is formed in the cavity. 13. The clamping device according to item 12 of the patent application scope, wherein the clamping device is a jig. 14. For the clamping device of the scope of application for item 12, wherein the sub-mold is a replaceable device. 15. The clamping device according to item 12 of the patent application scope, wherein the sub-mold has a top surface and a plurality of air-venting through holes penetrating the top surface and communicating with the cavity. 16. For a clamping device with the scope of patent application No. 12 or 15, wherein the exhaust channel has two opposite ends, one of which is in communication with the exhaust through holes, and the other end is opened in a miniature valve ( Mini-Valve) and the external exhaust device. 17. The clamping device according to item 12 of the patent application, wherein the external exhaust device is a vacuum pump. 16124.ptd Page 16