TW565948B - Method for making a chemical semiconductor device - Google Patents

Method for making a chemical semiconductor device Download PDF

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Publication number
TW565948B
TW565948B TW91110605A TW91110605A TW565948B TW 565948 B TW565948 B TW 565948B TW 91110605 A TW91110605 A TW 91110605A TW 91110605 A TW91110605 A TW 91110605A TW 565948 B TW565948 B TW 565948B
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Taiwan
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electrode
pad
layer
pad electrode
source
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TW91110605A
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Chinese (zh)
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Tetsuro Asano
Mikito Sakakibara
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Sanyo Electric Co
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
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  • Wire Bonding (AREA)

Abstract

A method for making a chemical semiconductor device is provided to eliminate such drawbacks in conventional chemical semiconductor device that a silicon nitride layer, which is left in the device for the safety purpose through the final process step, tends to crack easily at the bonding process because of the hard substrate and silicon nitride layer. A heavily doped region is formed underneath the pad electrode and wiring layer or underneath a peripheral portion, and the silicon nitride layer underneath the pad electrode is removed. Because of heavily doped region, a predetermined isolation is assured even after removing the silicon nitride layer, so that the gold plating process for prevention of cracking can be eliminated. As the space between each pad and the wiring layer can be reduced, a manufacturing method realizing the chip-shrink can be provided.

Description

565948565948

第6頁 565948 _案號91110605_%年（？月β曰 修正_ 五、發明說明（2) 接於第一與第二控制端子Ctl-1、Ct 1-2上，並且各FET的 汲極（或源極）則連接於第一與第二輸出端子OUT卜OUT2。 施加於第一與第二控制端子C11 - 1、C11 - 2上的信號係屬於 互補信號，Η位準的信號所施加的F E T為0 N，而成為將施 加於輸入端子I Ν上的信號，得以傳達於其中任一者的輸出 端子。電阻ΪΠ、R 2之設置目的係對構成交流接地的控制端 子C11 - 1、C11 - 2之直流電位，經由閘極可防止高頻信號的 洩出。 將化合物半導體開關電路裝置的FET、銲墊及配線之 製造方法表示於第12圖至第20圖。 第12圖中，在基板1表面上形成通道層2。 換句話說，以約1 0 0A厚的穿透離子植入用氮化矽膜3 被覆整個基板1。其次，對預定之通道層2上面的光阻層4 施行選擇性開窗的微影處理。然後，將此光阻層4當作罩 幕，為選擇動作層，而對預定之通道層2，施行供應p _型雜 質的離子植入及供應η型雜質的離子植入。結果在未摻雜 的基板1上，便形成Ρ型區域5，與其上所形成的η型通道層 2 〇 第1 3圖中，在基板1表面上鄰接通道層2兩端而形成源 極區域6與汲極區域7。 去除前製程所使用的光阻層4，然後重新對預定之源 極區域6與汲極區域7上的光阻層8，施行選擇性開窗的微 影處理。接著，以此光阻層8為罩幕，對預定之源極區域6 與汲極區域7施行供應η型雜質的離子植入，而形成η型源Page 6 565948 _ Case No. 91110605_% year (? Month β said amendment_ V. Description of the invention (2) Connected to the first and second control terminals Ctl-1, Ct 1-2, and the drain of each FET ( (Or source) is connected to the first and second output terminals OUT and OUT2. The signals applied to the first and second control terminals C11-1, C11-2 are complementary signals, the signal of the high level is applied The FET is 0 N, and becomes the output terminal that transmits the signal applied to the input terminal I N. The resistors ΪΠ and R 2 are set for the control terminals C11-1 and C11 constituting the AC ground. -The DC potential of 2 can prevent the leakage of high-frequency signals through the gate. The manufacturing methods of the FET, pads, and wiring of the compound semiconductor switching circuit device are shown in Figs. 12 to 20. Fig. 12 shows A channel layer 2 is formed on the surface of the substrate 1. In other words, the entire substrate 1 is covered with a silicon nitride film 3 for penetration ion implantation with a thickness of about 100 A. Second, a photoresist layer 4 on a predetermined channel layer 2 is covered. Selective windowing lithography is performed. Then, using this photoresist layer 4 as a mask, The action layer is selected, and ion implantation to supply p_-type impurities and ion implantation to supply n-type impurities are performed on the predetermined channel layer 2. As a result, on the undoped substrate 1, a P-type region 5 is formed, instead of The n-type channel layer 2 formed on the substrate is shown in Fig. 13. On the surface of the substrate 1, the two ends of the channel layer 2 are adjacent to form a source region 6 and a drain region 7. The photoresist layer 4 used in the previous process is removed. Then, the photoresist layer 8 on the predetermined source region 6 and the drain region 7 is subjected to selective lithography. Then, using the photoresist layer 8 as a mask, the predetermined source region 6 is performed. An n-type impurity is implanted into the drain region 7 to form an n-type source

313692 pic 第7頁 565948 _案號91110605_和年彳月β曰__ 五、發明說明（3) 極區域6與汲極區域7。 第1 4圖所示係在源極區域6與汲極區域7上，附著上第 一層電極的歐姆金屬層10 ’並形成第一源極11及第一；及極 12° 對形成預定之第一源極1 1與第一汲極1 2的部分，施行 選擇性開窗的微影處理。然後將預定之第一源極11與第一 汲極1 2上的氮化矽膜3，利用CF 4電漿而去除之後，接著再 依序真空蒸鍍層積三層之構成歐姆金屬層1 0的 AnGe/Ni/Au。然後，在去除光阻層1 3之後，利用浮離 (1 i f t - 〇 f f )在源極區域6與汲極區域7上，殘留第一源極1 1 與第一汲極1 2。接著，利用合金化熱處理形成第一源極1 1 與源極區域6、及第一汲極1 2與汲極區域7的歐姆接合。 第1 5圖所示係對預定之閘極1 6部分施行選擇性開窗的 微影處理。 第1 6圖所示係將所露出的氮化矽膜3施行乾式蝕刻處 理之後，依序真空蒸鍍層積上三層之構成閘金屬層1 8的 Ti/Pt/Au。然後，去除光阻層14，並利用浮離（1 i f t-of f ) 形成接觸於通道層2上的閘長0 . 5 // m之閘極1 6。 第1 7圖所示係形成保護膜1 9之後，再形成第二源極與 沒極2 3，2 4、及配線層2 5。 形成閘極1 6之後，為保護閘極1 6週邊的通道層2，基 板1表面係被覆上由氮化矽膜所構成的保護膜1 9。在此保 護膜1 9上施行微影處理，俾對與第一源極與汲極1 1，1 2的 接觸部，及與閘極1 6的接觸部，施行選擇性的光阻開窗，313692 pic Page 7 565948 _Case No. 91110605_ and the year and month β __ V. Description of the invention (3) Pole region 6 and drain region 7. As shown in FIG. 14, the first electrode ohmic metal layer 10 ′ is attached to the source region 6 and the drain region 7 to form a first source electrode 11 and a first electrode; Portions of the first source electrode 11 and the first drain electrode 12 are subjected to selective lithography. Then, the predetermined silicon source film 3 on the first source electrode 11 and the first drain electrode 12 is removed using a CF 4 plasma, and then three layers of ohmic metal layers 10 are sequentially deposited by vacuum evaporation. AnGe / Ni / Au. Then, after the photoresist layer 13 is removed, the first source electrode 1 1 and the first drain electrode 12 remain on the source region 6 and the drain region 7 by floating (1 i f t-0 f f). Next, an ohmic junction between the first source electrode 1 1 and the source region 6 and the first drain electrode 12 and the drain region 7 is formed by an alloying heat treatment. Figure 15 shows the lithographic process of selectively windowing 16 parts of the predetermined gates. As shown in FIG. 16, after the exposed silicon nitride film 3 is subjected to dry etching treatment, three layers of Ti / Pt / Au constituting the gate metal layer 18 are vacuum-deposited in order. Then, the photoresist layer 14 is removed, and a gate electrode 16 with a gate length of 0.5 / m // m contacting the channel layer 2 is formed by floating (1 i f t-of f). After the protective film 19 is formed as shown in FIG. 17, a second source electrode and a non-electrode electrode 2 3, 2 4 and a wiring layer 25 are formed. After the gate electrode 16 is formed, to protect the channel layer 2 around the gate electrode 16, the surface of the substrate 1 is covered with a protective film 19 made of a silicon nitride film. A lithography process is performed on this protective film 19, and a selective photoresistance window is performed on the contact portion with the first source electrode and the drain electrode 11 and 12, and the contact portion with the gate electrode 16,

313692 ptc 第8頁 565948 ___ 案號 五、發明說明（4) 將此部份的保 層。 然後，形 對基板1整面j >及極1 2部分， 將其他部分利 鍍層積上第三 層。因為直接 極1 1、第一；:及 2 5。因為配線 此去除光阻層 源極2 3、第二 的配線部分採 部分的配線金 第18圖所 成電鍍用電極 為多層配 的層間絕緣膜 理，俾對與第 層2 5的接觸部 膜1 9施行乾式 然後，形 上構成電鍍用 與汲極23, Μ 修正 91110605 護膜1 9施行乾式蝕刻處理。然後，去除光阻 成第二源極及沒極2 3，2 4，以及配線層2 5。 【新施行微影處理，俾使第一源極1 1、第一 以及預定之配線層2 5上的保護膜1 9露出，而 用光阻層2 0復蓋。接著，整面上依序真空蒸 層電極之構成配線金屬層2 1的T i / P t / A u之三 以光阻層2 0為罩幕，因此形成接觸到第一源 極1 2的第二源極2 3、第二汲極2 4及配線層 金屬層2 1的其他部分附著於光阻層2 〇上，因 2 0並利用浮離去除其他部分，而僅殘留第二 汲極24及配線層25。另外，因為其中一部分 用此配線金屬層2 1而形成，因此當然此配 屬層21亦殘留著。 ' 示係形成層間絕緣膜用的氮化矽膜2 6，並 27。 、，夕 線化，基板1表面便利用由氮化矽膜所構 2 6被覆著。對層間絕緣膜2 6上施行微影户 二源極與汲極2 3, 2 4的接觸部分，以及'配& 分施行選擇性的光阻開窗，將此部分的保 蝕刻處理。然後再去除光阻層。 '、夜 成電鍵用電極27。整面上依;真空蒸鍍声 電極27的Ti/Pt/Au之三層。因為在第二&極 •及配線層2 5的既定部分上設置接觸孔，’因° 565948 _案號91110605 知年孑月>7曰 修正_ 五、發明說明（5) 此便接觸到電鍍用電極2 7。 第1 9圖所示係施行鍍金，並形成供第三源極及汲極 2 8 , 2 9與搭接線固接用的銲墊電極3卜 對基板1施行微影處理，俾使預定之第三源極2 8、第 三汲極2 9及預定之銲墊電極3 1部分的電鍍用電極2 7露出， 而其他部分則利用光阻層3 0覆蓋之後，再施行電解鍍金。 此時光阻層3 0形成罩幕，僅露出電鍍用電極2 7的部分附著 鍍金。即，形成供接觸到第二源極2 3、第二汲極2 4的第三 源極2 8及第三汲極2 9與搭接線固接用的銲墊電極3卜 第2 0圖所示係最後形成銲墊電極3 1，於其上面再壓接 搭接線4 0。 去除光阻層30之後，再去除整面上所露出之不要的電 鍍用電極2 7。除經施以鍍金之第三源極2 8、第三汲極2 9及 銲墊電極3 1以外的電鍍用電極均屬不要部分。若施行Ar電 漿的離子研磨的話，未被施以鍍金部分的電鍍用電極便將 被研削，而露出層間絕緣膜2 6。鍍金部分雖亦多少被削 除，但因為有2至3// m程度的厚度，因此不致造成問題。 另，因為其中一部分的配線部分採用此鍍金而形成，因此 當然此配線部分的電鍍用電極2 7與鍍金便將殘留。 化合物半導體開關電路裝置係在完成前製程之後，便 移往執行組裝的後製程。晶圓狀的半導體晶片施行晶割處 理，而分離出個別的半導體晶片，然後將此半導體晶片固 接於引線框架（未圖示）之後，利用搭接線4 0連接半導體晶 片的銲墊電極3 1與既定的引線框架（未圖示）。搭接線4 0係313692 ptc page 8 565948 ___ Case No. 5. Description of the invention (4) This part is for protection. Then, the entire surface of the substrate 1 j > and the electrode 12 are formed, and the other parts are plated with a third layer. Because the direct pole 1 1, the first;: and 2 5. Because the wiring removes the photoresist layer source 2 3, the second wiring part uses a portion of the wiring gold. The plating electrode formed in Figure 18 is a multi-layer interlayer insulating film, and the contact film with the first layer 2 5 1 9 dry process is performed. Then, the plating electrode and the drain electrode 23, 22 are modified to form the 91110605 protective film. 19 A dry process is performed. Then, the photoresist is removed to form the second source electrode and the non-electrode electrode 23, 24, and the wiring layer 25. [A new lithography process is performed to expose the protective film 19 on the first source electrode 11, the first and the predetermined wiring layer 25, and cover it with a photoresist layer 20. Next, the three layers of T i / P t / A u of the wiring metal layer 21 constituting the wiring metal layer 21 in order of vacuum evaporation are sequentially formed on the entire surface, and the photoresist layer 20 is used as a cover, so that a contact with the first source electrode 12 is formed. The second source electrode 2 3, the second drain electrode 24, and other parts of the wiring layer metal layer 21 are attached to the photoresist layer 20, and only the second drain electrode remains because 20 and other parts are removed by floating. 24 and the wiring layer 25. In addition, since a part of it is formed using this wiring metal layer 21, it goes without saying that this matching layer 21 also remains. 'Shows the formation of silicon nitride films for interlayer insulation films 26, and 27. As a result, the surface of the substrate 1 is conveniently covered with a silicon nitride film 2 6. The lithographic household two-source contact with the drain electrodes 23, 24 is performed on the interlayer insulating film 26, and the selective photoresist windowing is performed for the distribution, and the etching protection of this part is performed. Then remove the photoresist layer. '、 夜 成 Electric key electrode 27. Three layers of Ti / Pt / Au of the acoustic electrode 27 are vacuum-deposited on the entire surface. Because a contact hole is provided in a predetermined portion of the second & pole and the wiring layer 25, 'in ° 565948 _ case No. 91110605 year of the year > 7 said correction _ V. Description of the invention (5) Then contact Electroplating electrode 2 7. As shown in FIG. 19, gold plating is performed, and a pad electrode 3 for bonding the third source electrode and the drain electrode 28, 29 to the bonding wire is formed, and a lithography process is performed on the substrate 1, so that it is predetermined. After the third source electrode 28, the third drain electrode 29, and the predetermined pad electrode 31 are partially exposed, the electroplating electrode 27 is exposed, and the other parts are covered with the photoresist layer 30, and then electrolytic gold plating is performed. At this time, the photoresist layer 30 forms a mask, and only the portion where the electrode for plating 27 is exposed is adhered with gold plating. That is, the third source electrode 28 and the third drain electrode 29 which are in contact with the second source electrode 2 3, the second drain electrode 24, and the third drain electrode 29 are formed to be bonded to the bonding pad 3, FIG. 20 As shown, the pad electrode 31 is finally formed, and the bonding wire 40 is crimped thereon. After the photoresist layer 30 is removed, the unnecessary plating electrodes 27 exposed on the entire surface are removed. Electrodes for plating other than the third source electrode 28, the third drain electrode 29, and the pad electrode 31, which are plated with gold, are unnecessary portions. If ion milling of the Ar plasma is performed, the electrode for electroplating that has not been plated with gold is ground, and the interlayer insulating film 26 is exposed. Although the gold-plated part is somewhat cut off, it does not cause a problem because it has a thickness of about 2 to 3 // m. In addition, since some of the wiring portions are formed using this gold plating, it is a matter of course that the plating electrodes 27 and gold plating in this wiring portion will remain. The compound semiconductor switching circuit device is moved to the post-assembly process after the pre-process is completed. The wafer-shaped semiconductor wafer is subjected to a crystal cutting process to separate individual semiconductor wafers. After this semiconductor wafer is fixed to a lead frame (not shown), the pad electrodes 3 of the semiconductor wafer are connected by bonding wires 40. 1 with an established lead frame (not shown). Patch cord 4 0 series

313692 ptc 第10頁 565948 修正 —-^^1110605 五、發明說明（6) 木用金細線’並利用週知的球焊進行連接。然後，經移轉 模塑後再施行樹脂封裝。 【發明内容】 朴 GaAsf板係屬於半絕緣性，然而若在基板上直接設置 ♦接、、泉用鲜塾電極層的話，將仍然存在相鄰接之電極間的 2 乍用。譬如因為絕緣度較弱而產生靜電破壞，或 =^員仏號Λ漏導致絕緣惡化等特性上的諸。因此在 ^ /中，便在配線層或銲墊電極層下面被覆上氮 化矽膜。 ^ 但疋’因為氮化矽膜較堅硬，隨搭接時的壓力將在銲 分產♦ Sk jsii ^ 龜衣。為抑制此便在氮化矽膜上的搭接電極上 亍金的制~ & _ 宁朿，但疋鑛金步驟除增加製程數之外，亦增 加成本。 此外 GaAs基板 接之電極 論上的支 認為是絕 得知耐壓 阻障層， 到達阻障 象。因此 上的間隔 但是 ，在 而形 間便 持， 緣基 其實 隨％ 層相 ，銲 矩離 ，在 習知化合物半導體裝置中，當接觸半絕緣性 成銲墊或配線層之時，為確保絕緣因此相鄰 設置2 0 // m以上的間隔距離。此雖尚缺乏理 但就從截至目前為止的半絕緣性GaAs基板如 板，耐壓係認為是無限大。但是當實測時， 是有限的。因此在半絕緣性GaAs基板中延伸 應高頻信號的阻障層距離之變化，可判斷若 鄰接之電極的話，將產生高頻信號遺漏的現 墊電極層與配線層等電極便配置呈2 0 // m以 〇 上述化合物半導體裝置中，5個銲墊便佔據313692 ptc Page 10 565948 Amendment —- ^^ 1110605 V. Description of the invention (6) Gold wire for wood 'and connected by well-known ball welding. Then, resin molding is performed after transfer molding. [Summary of the Invention] The GaAsf board system is semi-insulating. However, if a fresh electrode layer is used directly on the substrate, there will still be two applications between adjacent electrodes. For example, due to the weak insulation, electrostatic damage occurs, or the characteristics of insulation deterioration such as ^ member ^ leakage. Therefore, in ^ /, a silicon nitride film is covered under the wiring layer or the pad electrode layer. ^ But 疋 ’Since the silicon nitride film is harder, the pressure during lapping will be used to produce the Sk jsii ^ Turtle clothing. In order to suppress this, the fabrication of gold on the lap electrodes on the silicon nitride film is & _ Ning 朿, but the step of gold mining in addition to increasing the number of processes also increases costs. In addition, the theory that the electrode is connected to the GaAs substrate is that the voltage-resistant barrier layer is definitely known and reaches the barrier image. Therefore, the gap is maintained between the shape and the shape. In fact, the edge base varies with the% layer phase and the welding moment is separated. In conventional compound semiconductor devices, when contacting semi-insulating pads or wiring layers, it is necessary to ensure insulation. Therefore, the separation distance above 2 0 // m is set adjacently. Although this is still unreasonable, from the semi-insulating GaAs substrates such as boards, the withstand voltage system is considered to be infinite. But when measured, it is limited. Therefore, in the semi-insulating GaAs substrate, the change in the distance of the barrier layer that should respond to high-frequency signals can be judged. If the adjacent electrodes are adjacent, the electrodes such as the existing electrode layer and the wiring layer that will miss high-frequency signals will be arranged at 2 0 // m is 0. In the above compound semiconductor device, 5 pads occupy

313692 ptc313692 ptc

第1]頁 565948 _案號91110605 '年孑月4曰 修正_ 五、發明說明（7) 半導體晶片近半部分，導致無法縮小晶片尺寸的較大原因 -— 〇 現今亦著眼於提昇矽半導體晶片的性能，並提高可在 高頻帶利用的可能性。在習知中，矽晶片係頗難利用於高 頻帶，且利用高價之化合物半導體晶片，但若提高矽半導 體的可利用性的話，當然晶圓價格較高的化合物半導體晶 片便將輸在價格競爭上。因此縮小晶片尺寸並壓抑成本乃 屬必然性，且晶片尺寸的縮小係不可避免的。 【解決課題之手段】 本發明有鑑於上述諸項情事而完成者，其特徵在於提 供一種藉由去除銲墊電極下面的氮化矽膜，並抑制受打線 接合時之壓力的影響，更於銲墊電極下設置高濃度區域， 又在當作配線用之閘金屬下方設置高濃度區域，而縮小相 鄰接之銲墊電極、配線電極的間隔距離，俾實現可縮小晶 片尺寸的銲墊構造，且不致增加製造配線電極構造的製程 數之化合物半導體裝置之製造方法。 換句話說，其特徵為具備：在基板表面上形成通道層 的步驟；鄰接上述通道層而形成源極與汲極區域，同時在 預定之銲墊區域下方與預定之配線層下方，形成高濃度區 域的步驟；在上述源極及汲極區域上，附著第一層電極的 歐姆金屬層並形成第一源極與第一汲極的步驟；在上述通 道層與上述高濃度區域上，附著第二層電極的閘金屬層， 並形成閘極、第一銲墊電極及配線層的步驟；在上述第一 源極、第一汲極及上述第一銲墊電極上，附著第三層電極Page 1] Page 565948 _ Case No. 91110605 Amendment on the 4th of the year _ V. Description of the invention (7) The large part of the semiconductor wafer, which can not reduce the size of the wafer-〇 Today also focuses on the promotion of silicon semiconductor wafers Performance, and increase the possibility of utilization in high frequency bands. In the past, silicon wafers are difficult to use in high frequency bands and use expensive compound semiconductor wafers. However, if the availability of silicon semiconductors is improved, of course, compound semiconductor wafers with higher wafer prices will lose price competition. on. Therefore, it is inevitable to reduce the size of the wafer and suppress the cost, and the reduction of the size of the wafer is inevitable. [Means for solving the problem] The present invention has been completed in view of the above-mentioned circumstances, and is characterized in that it provides a method for removing the silicon nitride film under the pad electrode and suppressing the influence of the pressure during wire bonding. A high-concentration area is provided under the pad electrode, and a high-concentration area is provided under the gate metal for wiring, so as to reduce the distance between adjacent pad electrodes and wiring electrodes, thereby achieving a pad structure that can reduce the size of the wafer. A method for manufacturing a compound semiconductor device without increasing the number of processes for manufacturing a wiring electrode structure. In other words, it is characterized by: a step of forming a channel layer on the surface of the substrate; forming a source and a drain region adjacent to the channel layer, and forming a high concentration under a predetermined pad area and under a predetermined wiring layer A region step; a step of attaching an ohmic metal layer of a first electrode and forming a first source and a first drain on the source and drain regions; and attaching a first on the channel layer and the high-concentration region A step of forming a gate metal layer of a two-layer electrode to form a gate electrode, a first pad electrode, and a wiring layer; and attaching a third layer electrode to the first source electrode, the first drain electrode, and the first pad electrode

313692 ptc 第12頁 565948 _案號 91110605_U 年 # 月 Θ 曰_iMi_ 五、發明說明（8) 的銲墊金屬層，並形成第二源極、第二汲極及第二銲墊電 極的步驟；以及在上述第二銲墊電極上壓接搭接線的步 驟。 【實施方式】 以下，參照第1圖至第1 0圖說明本發明之實施形態。 本發明係由下述步驟構成：在基板5 1表面上形成通道 層5 2的步驟；鄰接上述通道層5 2而形成源極與汲極區域 5 6，5 7，同時在預定之銲墊區域下方與預定之配線層下 方，形成高濃度區域6 0，6 1的步驟；在上述源極及汲極區 域5 6，5 7上，附著第一層電極的歐姆金屬層6 4並形成第一 源極與第一汲極6 5，6 6的步驟；在上述通道層5 2與上述高 濃度區域6 0，6 1上，附著第二層電極的閘金屬層6 8，並形 成閘極6 9、第一銲墊電極7 0及配線層6 2的步驟；在上述第 一源極與第一汲極6 5，6 6及上述第一銲墊電極7 0上，附著 第三層電極的銲墊金屬層7 4，並形成第二源極與第二汲極 7 5，7 6及第二銲墊電極7 7的步驟；以及在上述第二銲墊電 極7 7上壓接搭接線8 0的步驟。 本發明之第一步驟係如第1圖所示，在基板5 1表面上 形成通道層52。 換句話說，將由GaAs等所形成的化合物半導體基板5 1 整面上，利用厚度約1 0 0A至2 0 0A的穿透離子植入用氮化 矽膜5 3進行被覆。其次，對預定形成通道層5 2上的光阻層 5 4，施行選擇性開窗的微影處理。然後，以此光阻層5 4為 罩幕，為對預定之通道層5 2選擇動作層，因此施行供應p —313692 ptc page 12 565948 _ case number 91110605_U year # month Θ _ _iMi_ V. the step of the invention (8) of the pad metal layer, and forming a second source, a second drain and a second pad electrode; And a step of crimping and bonding wires on the second pad electrode. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to Figs. 1 to 10. The present invention is composed of the following steps: a step of forming a channel layer 52 on the surface of the substrate 51; forming a source and a drain region 5 6, 5 7 adjacent to the channel layer 52, and simultaneously in a predetermined pad region Steps of forming a high-concentration region 60, 61 below and below a predetermined wiring layer; on the above source and drain regions 5 6, 57, an ohmic metal layer 64 of a first electrode is attached and a first is formed Steps of source electrode and first drain electrode 65, 66; on the channel layer 52 and the high-concentration region 60, 61, a gate metal layer 68 of a second electrode is attached to form a gate electrode 6 9. Steps of the first pad electrode 70 and the wiring layer 62; On the first source electrode and the first drain electrode 65, 66, and the first pad electrode 70, the third layer electrode is attached. The step of forming a pad metal layer 74 and forming a second source electrode, a second drain electrode 75, 76, and a second pad electrode 77; and crimping and bonding wires on the second pad electrode 7 7 8 0 steps. The first step of the present invention is to form a channel layer 52 on the surface of the substrate 51 as shown in FIG. In other words, the entire surface of the compound semiconductor substrate 5 1 formed of GaAs or the like is covered with a silicon nitride film 53 for penetrating ion implantation with a thickness of about 100A to 200A. Next, the photoresist layer 54 which is to be formed on the channel layer 52 is subjected to a lithography process for selectively opening a window. Then, using this photoresist layer 54 as a mask, an action layer is selected for a predetermined channel layer 52, so supply p-

313692 ptc 第13頁 565948 _案號91110605 #年孑月日 修正_ 五、發明說明（9) 型雜質（24Mg+)的離子植入，以及供應η型雜質（29Si +)的離 子植入。 結果，在未摻雜之基板5 1上，便形成p型區域5 5、並 於其上形成η型通道層5 2。 本發明之第二步驟如第2圖所示，形成鄰接上述通道 層5 2而形成源極區域5 6與汲極區域5 7，同時在預定之銲墊 電極7 0下方與預定之配線層6 2的下方形成高濃度區域 60, 6 卜 本步驟係形成本發明之第一特徵的步驟，去除前步驟 所採用之光阻層5 4，並重新對預定形成源極區域5 6、汲極 區域5 7、預定之配線層6 2與銲墊電極區域7 0上的光阻層 5 8，施行選擇性開窗的微影處理。接著，以此光阻層5 8為 罩幕，對預定之源極區域5 6與汲極區域5 7、預定之配線層 6 2與銲墊電極7 0之下方的基板表面，施行供應η型雜質 (2 9 S i +)的離子植入。藉此便形成η型源極區域5 6與沒極區 域5 7，同時在預定之第一銲墊電極7 0與配線層6 2下方的基 板表面上形成高濃度區域6 0，6 1。此處較重要的是高濃度 區域6 0，6 1依較預定之墊極7 0與配線層6 2更突出的方式， 去除光阻層5 8。藉此在利用之後的步驟所形成的銲墊電極 7 0與配線層6 2下方，便形成大於該等區域的高濃度區域 60, 6 卜 若在G a A s基板上直接設置銲墊電極或配線層的話，隨 對應高頻信號的阻障層距離的變化，若到達鄰接阻障層的 電極或配線層的話，可判斷在此將產生高頻信號的浪漏。313692 ptc Page 13 565948 _Case No. 91110605 # 年 孑 月 日 Modify _ V. Description of the invention Ion implantation of (9) -type impurity (24Mg +), and ion implantation to supply n-type impurity (29Si +). As a result, on the undoped substrate 51, a p-type region 55 is formed, and an n-type channel layer 52 is formed thereon. In the second step of the present invention, as shown in FIG. 2, a source region 56 and a drain region 57 are formed adjacent to the above-mentioned channel layer 52, and a predetermined wiring layer 6 is formed below a predetermined pad electrode 70. A high-concentration region 60, 6 is formed under 2 This step is a step of forming the first feature of the present invention, removing the photoresist layer 5 4 used in the previous step, and re-forming the source region 5 6 and the drain region that are intended to be formed. 5 7. The predetermined wiring layer 62 and the photoresist layer 58 on the pad electrode area 70 are subjected to a lithographic process of selective windowing. Next, using the photoresist layer 58 as a mask, the substrate surface under the predetermined source region 56 and drain region 57, the predetermined wiring layer 62, and the pad electrode 70 are supplied with n-type Ion implantation of impurities (2 9 S i +). Thereby, n-type source regions 56 and non-electrode regions 57 are formed, and high-concentration regions 60, 61 are formed on the surface of the substrate below the predetermined first pad electrode 70 and wiring layer 62. What is more important here is that the high-concentration region 60, 61 is more prominent than the predetermined pad 70 and the wiring layer 62, and the photoresist layer 58 is removed. Thereby, under the pad electrode 70 and the wiring layer 62 formed in the subsequent steps, a high-concentration region 60, 6 larger than these regions is formed. If a pad electrode or a pad electrode is directly provided on the GaAs substrate, As for the wiring layer, as the distance of the barrier layer corresponding to the high-frequency signal changes, if it reaches the electrode or the wiring layer adjacent to the barrier layer, it can be judged that high-frequency signal leakage will occur here.

313692 pic 第]4頁 565948 -^办年方月< 曰 修正_ 五、發明說明（ίο) ' - 但疋，右在知墊電極7 〇與配線層6 2下方的基板5丨表面 上設置η型高濃度區域6G，61的話，與未摻雜有雜質的基板 5 1 (屬於半絶緣性，基板阻抗值1χ丨〇 Ώ 〇cm)表面不同，雜 質濃度將變高（離子種類29Sl+，濃度丨至5χ 1〇8cm_3)。藉 此因為配線層62與銲墊電極7〇與基板51被分離，且阻障層 並未延伸至銲墊電極70、配線層62上，因此相鄰接之銲墊 電極70、配線層62便可使相互間的間隔距離大幅接近而設 置。 具體而言，可推斷出若將間隔距離設計為m的話， 便可充分的確保20dBm以上的隔離（is〇lati〇n)。此外，即 便在電磁場模擬中，得知若設置4/i m程度之間隔距離的 話，在2· 4GHz下，即便40dBm程度亦可獲得隔離。 即’在銲墊電極70與配線層62下，藉由依更突出於該 等區域的方式設置高濃度區域6 0，6 1，即便將銲墊電極7 〇 與配線層62直接設置於GaAs基板上，因為可充分確保絕 緣’因此可免除習知為安全起見而所設置的氮化石夕膜。 若不需要氮化矽膜的話，因為在打線接合壓接時，不 再擔心氮化矽膜的龜裂，因此便可省卻習知所必要的梦金 步驟。鑛金製程因為屬於製程數較多且亦較耗成本的f i 驟，因此若可省略此步驟的話，對製造步驟二 削減上將產生極大的作用。 θ 再者，相鄰接之銲墊電極70或配線層62的間隔距離即 便靠近至4// m為止’亦可充分確保2〇dBm的隔離。嬖如挪 銲墊便佔據半導體晶片近半的化合物半導體裝置/，313692 pic page] 4 pages 565948-^ Office year Fangyue < said correction_ V. Description of the invention (ίο) '-But, right, on the surface of the substrate 5 丨 under the pad electrode 7 〇 and the wiring layer 6 2 If the η-type high-concentration region 6G, 61 is different from the surface of the substrate 5 1 (which is semi-insulating, and the substrate resistance is 1 × 丨 〇 〇cm) not doped with impurities, the impurity concentration will increase (ion type 29Sl +, concentration丨 to 5x108cm_3). This is because the wiring layer 62 is separated from the pad electrode 70 and the substrate 51, and the barrier layer does not extend to the pad electrode 70 and the wiring layer 62. Therefore, the adjacent pad electrode 70 and the wiring layer 62 are convenient. The distances between them can be set close to each other. Specifically, it can be inferred that if the separation distance is designed to be m, isolation of 20 dBm or more can be sufficiently ensured. In addition, even in the electromagnetic field simulation, it is learned that if a separation distance of about 4 / im is set, the isolation can be obtained even at about 40 dBm at 2.4 GHz. That is, under the pad electrode 70 and the wiring layer 62, a high-concentration region 60, 61 is provided so as to protrude more from these regions, even if the pad electrode 70 and the wiring layer 62 are directly provided on the GaAs substrate Because the insulation can be sufficiently ensured, the conventional nitride nitride film provided for safety is eliminated. If a silicon nitride film is not needed, it is possible to dispense with the dream gold step necessary for knowing because the silicon nitride film is no longer worried about cracking during wire bonding and crimping. The mining gold process is a f i step with a large number of processes and a relatively costly process. Therefore, if this step can be omitted, it will have a great effect on the reduction of the manufacturing step 2. θ Furthermore, even if the distance between the adjacent pad electrodes 70 or the wiring layer 62 is close to 4 // m ', the isolation of 20 dBm can be sufficiently ensured. For example, if a solder pad is used, compound semiconductor devices occupy almost half of the semiconductor wafer.

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565948 _案號9Π10605_%年纪月彳曰 修正_ 五、發明說明（11) 將晶片尺寸大幅縮小，並可實現低價格化的化合物半導體 裝置。 本發明之第三步驟如第3圖所示，在上述源極區域5 6 與汲極區域5 7上，附著第一層電極的歐姆金屬層6 4，並形 成第一源極6 5與第一沒極6 6。 首先，對形成預定之第一源極6 5與第一汲極6 6的部 分，施行選擇性開窗的微影處理。在預定之第一源極6 5與 第一沒極6 6上的氮化石夕膜5 3，利用C F 4電漿予以去除之後， 接著再依序真空蒸鍍層積三層之構成歐姆金屬層6 4的 AnGe/Ni/Au。然後，在去除光阻層6 3之後，利用浮離 (1 i f t - 〇 f f )在源極區域5 6與汲極區域5 7上，殘留已接觸之 第一源極6 5與第一汲極6 6。接著，利用合金化熱處理形成 第一源極6 5與源極區域5 6、及第一沒極6 6與沒極區域5 7的 歐姆接合。 本發明之第四步驟如第4圖至第6圖所示，在上述通道 層5 2與上述高濃度區域6 0，6 1上，附著第二層電極的閘金 屬層6 8，並形成閘極6 9、第一銲墊電極7 0及配線層6 2。 本步驟係本發明之第二特徵的步驟。就第一實施例而 言，首先，如第4圖所示，對預定之閘極6 9、銲墊電極7 0 及配線層6 2部分，施行選擇性開窗的微影處理。對從預定 之閘極6 9、銲墊電極7 0及配線層6 2部分中露出的氮化矽膜 5 3施行乾式蝕刻處理，而露出預定之閘極6 9部分的通道層 5 2，並使預定之配線層6 2與預定之銲墊電極7 0部分的基板 51露出。565948 _Case No. 9Π10605_% Years, Months and Months Amendment _ V. Description of the Invention (11) A compound semiconductor device that can significantly reduce the size of a wafer and realize a low price. As shown in FIG. 3, the third step of the present invention attaches an ohmic metal layer 6 4 of a first layer electrode to the source region 5 6 and the drain region 57, and forms a first source electrode 65 and a third electrode.一 无极 6 6. First, a lithographic process of selectively opening a window is performed on a portion forming a predetermined first source electrode 65 and a first drain electrode 66. After the nitride film 5 3 on the predetermined first source electrode 65 and the first non-electrode electrode 6 6 is removed by using a CF 4 plasma, three ohmic metal layers 6 are sequentially formed by vacuum evaporation. 4 AnGe / Ni / Au. Then, after the photoresist layer 63 is removed, the first source electrode 65 and the first drain electrode that have been in contact are left on the source region 56 and the drain region 57 by floating (1 ift-0ff). 6 6. Next, an ohmic junction between the first source electrode 65 and the source region 56 and the first non-electrode electrode 66 and the non-electrode region 57 is formed by an alloying heat treatment. The fourth step of the present invention is shown in FIGS. 4 to 6. On the channel layer 52 and the high-concentration region 60, 61, a gate metal layer 68 of a second electrode is adhered to form a gate. Electrode 69, first pad electrode 70 and wiring layer 62. This step is a step of the second feature of the present invention. In the first embodiment, first, as shown in FIG. 4, the lithographic process of selective windowing is performed on the predetermined gate electrode 69, the pad electrode 70, and the wiring layer 62. A dry etching process is performed on the silicon nitride film 5 3 exposed from the predetermined gate electrode 6 9, the pad electrode 70 and the wiring layer 62, and the channel layer 5 2 of the predetermined gate electrode 69 is exposed. The substrate 51 of the predetermined wiring layer 62 and the predetermined pad electrode 70 is exposed.

313692 ptc 第16頁 565948 _案號 Θ1110605 P 年校 η τή j _ 五、發明說明（12) 將預定之閘極6 9部分的開口部設定為0 · 5// in，便可形 成細微化的閘極6 9。此時如第二步驟中所說明，因為在習 知為確保絕緣而所需要的氮化石夕膜，藉由設置咼濃度區域 6 0，6 1而可去除，因此便不致產生隨搭接線壓接時的衝擊 而造成氮化矽膜與基板龜裂的現象。 在第5圖中，於通道層5 2與所露出的基板5 1上，附著 第二層電極的閘金屬層6 8，並形成閘極6 9、配線層β 2及第 一銲墊電極7 0。 換句話說，在基板5 1上依序真空蒸鍍層積構 電極之閘金屬層6 8的T i / P t / A u之三層。然後，去 L ^ 6 7，並利用浮離（1 i f t — 0 f f )形成接觸於通道層5除光阻層 0· 5// m之閘極69、第一銲墊電極70及配線層上的閘長 再者，就弟一貫施例而言，亦可如第β圖戶斤— 極6 9的其中一部分埋入通道層5 2中。此情况 不’將閘 蒸鍍層積上閘金屬層68的？1:/1^/?1：/^11之四展’依序真空 由浮離（lift-off )形成閘極69、第一銲墊電q 。然後，經 6 2之後，施行埋有p七的熱處理。藉此便如第^ 7 〇及配線層 極69便在與基板保持肖特基接合的狀態下，^圖所示，閘 運層5 2中。其中，此情況下的通道層5 2的深=分埋設於通 一步驟形成通道層5 2的情況時，則在考慮此X，當利用第 部分的前提下，依可獲得所需FET特性的方閘極6 9的埋入 可。 八形成深度便 通道層52表面（譬如從表面起5〇 〇A至 自然的產生阻障層，並存在結晶不均勻區 1 °〇〇A 域等， 程度）將 導致電流313692 ptc page 16 565948 _case number Θ1110605 P year school η τή j _ V. Description of the invention (12) Set the openings of the predetermined gates 6 and 9 to 0 · 5 // in to form a finer Gate 6 9. At this time, as explained in the second step, the conventional nitride film required for ensuring the insulation can be removed by setting a radon concentration region of 60, 61, so there is no need to generate a bonding line voltage. The silicon nitride film and the substrate are cracked due to the impact during the connection. In FIG. 5, on the channel layer 52 and the exposed substrate 51, a gate metal layer 68 of a second electrode is attached, and a gate electrode 69, a wiring layer β2, and a first pad electrode 7 are formed. 0. In other words, three layers of Ti / Pt / Au of the gate metal layer 68 of the laminated structure electrode are sequentially vacuum-evaporated on the substrate 51. Then, go to L ^ 6 7 and form a gate electrode 69, a first pad electrode 70, and a wiring layer in contact with the channel layer 5 and the photoresist layer 0 · 5 // m by floating (1 ift — 0 ff). In addition, as far as the brother ’s usual embodiment is concerned, a part of the gate can be buried in the channel layer 5 2 as in FIG. In this case, is n’t the gate vapor deposited on the gate metal layer 68? 1: / 1 ^ /? 1: / ^ 11 之 四 展 ’Sequential vacuum Forms the gate electrode 69 and the first pad electric q by lift-off. Then, after 6 2, a heat treatment in which p 7 is buried is performed. As a result, the gate layer 69 and the wiring layer electrode 69 are in a state in which the Schottky joint is held with the substrate, as shown in the figure, in the gate layer 52. Wherein, the depth of the channel layer 5 2 in this case = when the channel layer 5 2 is formed by being buried in one step, then considering this X, when using the premise of Part 1, the required FET characteristics can be obtained. Embedding of the square gate electrode 6 9 is possible. The surface of the channel layer 52 (for example, 500 Å from the surface to the natural generation of a barrier layer, and there is a 1 ° 〇〇A region of crystalline unevenness, etc.) will cause a current

313692 pt 565948 _案號91110605 心年#月曰 修正_ 五、發明說明（13) 不流通，而無法構成有效的通道。藉由將閘極6 9的其中一 部分埋設於通道領域5 2中，在閘極6 9正下方的電流流通部 分，便將從通道領域5 2表面下降。通道領域5 2因為依獲得 預先所需的FET特性之方式，考慮閘極6 9的埋設量而形成 深處，因此便可有效的應用為通道。具體而言，具有大幅 改善電流密度、通道電阻、高頻失真特性的優點。 不論何種情況，因為均可去除銲墊電極7 0與配線層6 2 下的氮化矽膜而不致產生龜裂。此外，習知亦必須防止靜 電破壞或為確保絕緣，但是藉由在銲墊電極7 0下方及配線 層6 2下方的基板5 1上設置高濃度區域6 0，6 1，便可抑制阻 障層的拓展，並可確保既定的絕緣。 如上述，若不需要氮化矽膜的話，因為便不再需要為 抑制其龜裂而所設置的鍍金步驟，因此可大幅削減成本， 並簡化製造步驟。 本發明之第五步驟係如第7圖與第8圖所示，在上述第 一源極6 5、第一汲極6 6、及上述第一銲墊電極7 0上，附著 第三層電極的銲墊金屬層7 4，並形成第二源極與第二汲極 7 5，7 6及第二銲墊電極7 7。 在第7圖中，於第一源極6 5、第一汲極6 6及第一銲墊 電極7 0上面的保護膜7 2上形成接觸孔。 在形成閘極6 9、配線層6 2及第一銲墊電極7 0之後，為 保護閘極6 9週邊的通道層5 2，則將基板5 1表面被覆上由氮 化矽膜所構成的保護膜7 2。在此保護膜7 2上施行微影處 理，俾對接觸到第一源極6 5、第一汲極6 6及第一銲墊電極313692 pt 565948 _Case No. 91110605 Xinnian # Month Revision_ V. Description of the invention (13) Circulation, which cannot constitute an effective channel. By burying a part of the gate electrode 6 9 in the channel area 52, the current flowing portion directly below the gate electrode 6 9 will descend from the surface of the channel area 52. The channel field 5 2 can be effectively used as a channel because it is formed in depth by taking into account the buried amount of the gate electrode 6 9 in order to obtain the required FET characteristics in advance. Specifically, it has the advantages of greatly improving current density, channel resistance, and high-frequency distortion characteristics. In any case, the silicon nitride film under the pad electrode 70 and the wiring layer 62 can be removed without cracking. In addition, it is necessary to prevent static electricity damage or to ensure insulation. However, by setting a high concentration area 60, 61 on the substrate 51 under the pad electrode 70 and the wiring layer 62, the barrier can be suppressed. The expansion of the layers can ensure a given insulation. As described above, if a silicon nitride film is not needed, a gold plating step for suppressing cracks is no longer required, so that costs can be significantly reduced and manufacturing steps can be simplified. A fifth step of the present invention is to attach a third layer of electrodes to the first source electrode 65, the first drain electrode 66, and the first pad electrode 70 as shown in FIGS. 7 and 8. And a second pad electrode 7 5, 7 6 and a second pad electrode 7 7 are formed. In FIG. 7, a contact hole is formed in the protective film 72 on the first source electrode 65, the first drain electrode 66, and the first pad electrode 70. After the gate electrode 6 9, the wiring layer 62, and the first pad electrode 70 are formed, in order to protect the channel layer 5 2 around the gate electrode 6 9, the surface of the substrate 51 is covered with a silicon nitride film. Protective film 7 2. A lithography process is performed on the protective film 72, and the pair contacts the first source electrode 65, the first drain electrode 66, and the first pad electrode.

313692 ptc. 第18頁 565948 _案號91110605 私年f月d日 修正_ 五、發明說明（14) 7 0的接觸部，施行選擇性的光阻層之開窗，將此部份的保 護膜7 2施行乾式蝕刻處理。然後，去除光阻層7卜 在第8圖中，於第一源極6 5、第一汲極6 6、及第一銲 墊電極7 0上附著第三層電極的銲墊金屬層7 4，並形成第二 源極7 5、第二汲極7 6及第二銲墊電極7 7。 對基板5 1整面重新塗布光阻層7 3並施行微影處理，並 對預定之第二源極7 5、第二汲極7 6及第二銲墊電極7 7上面 的光阻，施行選擇性開窗的微影處理。接著，依序真空蒸 鍍層積上第三層電極之構成銲墊金屬層74的Ti/Pt/Au之三 層，而形成接觸於第一源極6 5、第一汲極6 6及第一銲墊電 極7 0的第二源極7 5、第二汲極7 6及第二銲墊電極7 7。因為 銲墊金屬層7 4的其他部分附著於光阻層7 3上，因此去除光 阻層7 3並利用浮離僅殘留第二源極7 5、第二汲極7 6及第二 銲墊電極77，而將其他部分予以去除。另外，因為其中一 部分的配線部分採用此銲墊金屬層7 4而形成，因此當然此 配線部分的銲墊金屬層7 4亦殘留著。 本發明之第六步驟係如第9圖所示，在上述第二銲墊 電極7 7上壓接搭接線8 0。第9圖（a )所示係本發明之第一實 施形態的情況，而第9圖（b)則係本發明之第二實施形態的 情況。 在本步驟中，如前述，因為藉由高濃度區域60，61而 可去除第一銲墊電極7 0與第二銲墊電極7 7下方的氮化矽 膜，因此可防止打線接合壓接時產生龜裂現象。 化合物半導體開關電路裝置係在完成前製程之後，便313692 ptc. P.18 565948 _Case No. 91110605 Private year f month d amendment _ V. Description of the invention (14) The contact part of 70 is implemented with selective photoresist layer windowing, and the protective film for this part 7 2 Perform dry etching. Then, the photoresist layer 7 is removed. In FIG. 8, a pad metal layer 7 4 of a third electrode is attached to the first source electrode 65, the first drain electrode 6 6, and the first pad electrode 70. And form a second source electrode 75, a second drain electrode 76, and a second pad electrode 77. The entire surface of the substrate 51 is re-coated with a photoresist layer 7 3 and lithography is performed, and the photoresist on the predetermined second source electrode 7 5, the second drain electrode 7 6 and the second pad electrode 7 7 is applied. Selective windowing lithography. Next, three layers of Ti / Pt / Au constituting the pad metal layer 74 of the third electrode layer are sequentially vacuum-deposited to form a contact with the first source electrode 6 5, the first drain electrode 6 6, and the first electrode. The second source electrode 75, the second drain electrode 76, and the second pad electrode 77 of the pad electrode 70. Because the other parts of the pad metal layer 74 are attached to the photoresist layer 73, the photoresist layer 73 is removed and only the second source electrode 75, the second drain electrode 76, and the second pad are left by floating. Electrode 77, and other parts are removed. In addition, since a part of the wiring portion is formed using this pad metal layer 74, the pad metal layer 74 of this wiring portion is of course left. The sixth step of the present invention is shown in Fig. 9 where the bonding pads 80 are crimped onto the second pad electrodes 7 7. Fig. 9 (a) shows the case of the first embodiment of the present invention, and Fig. 9 (b) shows the case of the second embodiment of the present invention. In this step, as described above, since the silicon nitride film under the first pad electrode 70 and the second pad electrode 7 7 can be removed by the high-concentration regions 60 and 61, it is possible to prevent wire bonding during crimping. Cracking occurs. After the compound semiconductor switching circuit device is completed,

313692 ptc 第19頁 565948 _案號91110605 #年#月：^曰 修正_ 五、發明說明（15) 移往執行組裝的後製程。將晶圓狀的半導體晶片予以晶割 處理，而分離出個別的半導體晶片，然後將此半導體晶片 固接於引線框架（未圖示）之後，利用搭接線8 0連接半導體 晶片的弟 >一鲜塾電極7 7與既定之引線框架（未圖不）。格接 線8 0係採用金細線，並利用週知的球焊進行連接。然後， 經移轉模塑後再施行樹脂封裝。 此外，高濃度區域係如第1 0圖（a )、（ b )所示，亦可利 用微影處理而選擇性地對光阻施行開窗處理，而在設置於 預定之配線層6 2的周端部下方，以及預定之銲墊電極7 0的 周端部下方。即便此情況下，亦設計成較配線層6 2與銲墊 電極7 0之部分突出的狀態。 第1 0圖（c )中所示係高濃度區域6 0，6 1的配置例。高濃 度區域6 0，6 1亦可設計為包圍銲墊電極7 0與配線層6 2的方 式，亦可設計為如第1 0圖（c )所示。即，銲墊電極7 0 a係除 上邊之外，其餘三邊均設有高濃度區域6 0，而銲墊電極 70b則除GaAs基板的角落部分之外，沿不規則的五角形四 邊設置呈C字狀的高濃度區域6 0。未設置高濃度區域4 0的 部分均屬於面朝GaAs基板的周端之部分，即便阻障層擴 展，相鄰接之銲墊與配線間仍具有充分的間隔距離，不致 產生洩漏（leak)的問題。 再者，高濃度區域6 1係選擇性的設置於靠近銲墊電極 7 0 a、7 0 b側的配線層6 2下方。 該等配置例僅係其中一例，僅要具有可防止施加於銲 墊電極7 0上的高頻信號，透過基板5 1傳達給配線層6 2之作313692 ptc Page 19 565948 _Case No. 91110605 # 年 # 月 ： ^ 约 Correction_ V. Description of the invention (15) Moved to the post-assembly process. The wafer-shaped semiconductor wafer is subjected to a crystal cutting process to separate individual semiconductor wafers, and then the semiconductor wafer is fixed to a lead frame (not shown), and then connected to the semiconductor wafer by a bonding wire 80. > A fresh electrode 7 7 and a predetermined lead frame (not shown). The grid line 80 is made of thin gold wire and is connected by well-known ball welding. Then, resin molding is performed after transfer molding. In addition, as shown in Fig. 10 (a) and (b), the high-concentration area can be selectively windowed by photolithography using a photolithography process. Below the peripheral end portion, and below the peripheral end portion of the predetermined pad electrode 70. Even in this case, it is designed so as to protrude from portions of the wiring layer 62 and the pad electrode 70. The arrangement example of the high-concentration regions 60, 61 shown in FIG. 10 (c) is shown. The high-concentration regions 60 and 61 can also be designed to surround the pad electrodes 70 and the wiring layer 62, and can also be designed as shown in Fig. 10 (c). That is, the pad electrode 70a is provided with a high-concentration region 60 on the other three sides except the upper side, and the pad electrode 70b is arranged along the irregular pentagonal four sides except for the corner portion of the GaAs substrate. The font-shaped high-concentration area 60. The part where no high-concentration area 40 is provided is a part facing the peripheral end of the GaAs substrate. Even if the barrier layer is expanded, there is still a sufficient separation distance between the adjacent pads and the wiring, so that no leakage will occur. problem. In addition, the high-concentration region 61 is selectively disposed under the wiring layer 62 near the pad electrodes 70a and 70b. These arrangement examples are just one example, and only have to prevent the high-frequency signal applied to the pad electrode 70 from being transmitted to the wiring layer 62 through the substrate 51.

3]3692 ptc 第20頁 565948 _案號91110605_%年及月β 修正_ 五、發明說明（16) 用的話便可。另，在第1 0圖中雖省略，但亦可如本發明第 二實施形態，將閘極6 9埋入通道層5 2表面中。 【發明效果】 如以上所詳述，根據本發明可獲得以下的效果。 第一、措由在基板中設置向濃度區域’因為鲜塾電極 及配線層可與基板之間形成分離狀態，因此便可去除習知 為確保絕緣而所設置的氮化矽膜。若不需要氮化矽膜的 話，便可省略為防止搭接時氮化矽膜龜裂而所採行的鍍金 步驟。因為鍍金步驟的製程數較多，且成本亦較高，因此 若省略此步驟的話，便可達成低成本且流程簡化的化合物 半導體裝置之製造方法。 第二，藉由高濃度區域，銲墊電極及配線層便可與基 板分離，且可防止絕緣破壞與干涉，並可大幅縮小相鄰接 之間隔距離。具體而言，在確保20dBm隔絕的情況下，可 靠近配置至4// m，對晶片尺寸的縮小具有頗大的作用。 即，可製造低成本且高品質的化合物半導體裝置。 第三，閘金屬層係採用Pt/Ti/Au，藉由熱處理而將閘 極的其中部分埋設於通道區域中，閘極正下方的電流流通 部分，便可從通道區域表面處下降。通道表面屬於無法有 效當作通道的區域，因為藉由埋設閘極便可有效活用通 道，因此可大幅改善電流密度、通道電阻與高頻失真特 性。3] 3692 ptc Page 20 565948 _ Case No. 91110605_% year and month β amendment _ 5. Description of the invention (16) If you use it. Although not shown in Fig. 10, the gate electrode 69 may be buried in the surface of the channel layer 52 as in the second embodiment of the present invention. [Effects of the Invention] As described in detail above, according to the present invention, the following effects can be obtained. First, by providing a concentration region in the substrate ', since the osmium electrode and the wiring layer can be separated from the substrate, the conventional silicon nitride film provided to ensure insulation can be removed. If a silicon nitride film is not required, the gold plating step to prevent the silicon nitride film from cracking during bonding can be omitted. Because the number of gold plating steps is large and the cost is high, if this step is omitted, a method for manufacturing a compound semiconductor device with a low cost and a simplified process can be achieved. Second, the pad electrode and wiring layer can be separated from the substrate through the high-concentration area, which can prevent insulation damage and interference, and can greatly reduce the distance between adjacent connections. Specifically, it can be placed close to 4 // m with 20 dBm isolation, which has a significant effect on reducing the size of the wafer. That is, a low-cost and high-quality compound semiconductor device can be manufactured. Third, the gate metal layer is made of Pt / Ti / Au. Part of the gate is buried in the channel area by heat treatment, and the current flowing part directly below the gate can be dropped from the surface of the channel area. The channel surface is an area that cannot be effectively used as a channel. Because the channel can be effectively used by burying the gate, the current density, channel resistance, and high-frequency distortion characteristics can be greatly improved.

313692 ptc 第21頁 565948 _案號91110605 办年及月之7曰 修正_ 圖式簡單說明 [圖式簡單說明] 第1圖係用以說明本發明之剖視圖，為表示於第一步 驟中形成通道層5 2之狀態。 第2圖係用以說明本發明之剖視圖，為表示於第二步 驟中形成汲極區域5 7與高濃度區域6 0、6 1之狀態。 第3圖係用以說明本發明之剖視圖，為表示於第三步 驟中設置歐姆金屬層6 4，並且形成源極6 5與汲極6 6。 第4圖係用以說明本發明之剖視圖，為表示於第四步 驟中露出閘極6 9、銲墊電極7 0、配線層6 2之形成區域之狀 態。 第5圖係用以說明本發明之剖視圖，為表示設置閘金 屬層6 8，並且形成閘極6 9、配線層6 2與銲墊電極7 0之狀 態。 第6圖係用以說明本發明之剖視圖，為表示部分閘極 6 9埋入通道層5 2之狀態。 第7圖係用以說明本發明之剖視圖，為表示於保護膜 7 2中形成接觸孔之狀態。 第8圖係用以說明本發明之剖視圖，為表示於第五步 驟中形成第二源極7 5、第二汲極7 6與第二銲墊電極7 7之狀 態。 第9圖係用以說明本發明之剖視圖，為表示於第六步 驟中將搭接線8 0壓接於第二銲墊電極7 7上之狀態，而第9 圖（A)係本發明第一實施形態之狀況，第9圖（B)係本 發明第二實施形態之狀況。313692 ptc Page 21 565948 _ Case No. 91110605 Amendment of the 7th of the year and month _ Simple illustration of the drawing [Simplified illustration of the drawing] The first diagram is used to explain the cross-sectional view of the present invention, which shows that the channel is formed in the first step State of layer 52. Fig. 2 is a sectional view for explaining the present invention, and shows a state where the drain region 57 and the high-concentration regions 60 and 61 are formed in the second step. Fig. 3 is a cross-sectional view for explaining the present invention. It is shown that the ohmic metal layer 64 is provided in the third step, and the source 65 and the drain 66 are formed. Fig. 4 is a cross-sectional view for explaining the present invention, and shows the state where the formation regions of the gate electrode 69, the pad electrode 70, and the wiring layer 62 are exposed in the fourth step. Fig. 5 is a cross-sectional view for explaining the present invention, and shows a state in which a gate metal layer 68 is provided, and a gate electrode 69, a wiring layer 62, and a pad electrode 70 are formed. Fig. 6 is a cross-sectional view for explaining the present invention, and shows a state where a part of the gate electrode 69 is buried in the channel layer 52. Fig. 7 is a sectional view for explaining the present invention, and shows a state where a contact hole is formed in the protective film 72. Fig. 8 is a sectional view for explaining the present invention, and shows the state where the second source electrode 75, the second drain electrode 76, and the second pad electrode 77 are formed in the fifth step. FIG. 9 is a cross-sectional view for explaining the present invention, and shows a state in which the bonding wire 80 is crimped to the second pad electrode 77 in the sixth step, and FIG. 9 (A) is the first view of the present invention. FIG. 9 (B) shows a state of an embodiment, and shows a state of a second embodiment of the present invention.

313692 pic 第22頁 565948 _案號91110605 灸年汐月日 修正_ 圖式簡單說明 第1 0圖（A)係用以說明本發明之剖視圖，為表示施 行開窗之狀態；第1 0圖（B)係用以說明本發明之剖視 圖，為表示形成各電極與配線層之最終結構；第1 0圖（C )係用以說明本發明之俯視圖，為表示高濃度區域6 0、6 1 之配置例。 第1 1圖（A)係用以說明習知例之GaAs FET之剖視 圖，第1 1圖（B)係用以說明習知例之GaAs FET之電路 圖。 第1 2圖係用以說明習知例之剖視圖，為表示於基板1 表面形成通道層2之狀態。 第1 3圖係用以說明習知例之剖視圖，為表示形成源極 區域6與汲極區域7之狀態。 第1 4圖係用以說明習知例之剖視圖，為表示形成金屬 層1 0、源極1 1與沒極1 2之狀態。 第1 3圖係用以說明習知例之剖視圖，為表示施行開窗 之步驟。 第1 6圖係用以說明習知例之剖視圖，為表示形成閘極 1 6之狀態。 第1 7圖係用以說明習知例之剖視圖，為表示形成保護 膜1 9、源極2 3、汲極2 4與配線層2 5之狀態。 第1 8圖係用以說明習知例之剖視圖，為表示形成氮化 矽膜2 6與電鍍用電極2 7之狀態。 第1 9圖係用以說明習知例之剖視圖，為表示形成源極 2 8、汲極2 9與銲墊電極3 1之狀態。313692 pic Page 22 565948 _Case No. 91110605 Moxibustion Year Month and Day Modification _ Brief Description of Drawings Figure 10 (A) is a cross-sectional view for explaining the present invention, showing the state of window opening; Figure 10 ( B) is a cross-sectional view for explaining the present invention, showing the final structure of each electrode and wiring layer; FIG. 10 (C) is a top view for explaining the present invention, showing the high-concentration region 60, 6 1 Configuration example. FIG. 11 (A) is a cross-sectional view for explaining a conventional GaAs FET, and FIG. 11 (B) is a circuit diagram for explaining a conventional GaAs FET. 12 is a cross-sectional view for explaining a conventional example, and shows a state where the channel layer 2 is formed on the surface of the substrate 1. FIG. 13 is a cross-sectional view for explaining a conventional example, and shows a state where the source region 6 and the drain region 7 are formed. FIG. 14 is a cross-sectional view for explaining a conventional example, and shows a state where a metal layer 10, a source 11 and a non-electrode 12 are formed. Fig. 13 is a cross-sectional view for explaining a conventional example, and shows a procedure for opening a window. Fig. 16 is a sectional view for explaining a conventional example, and shows a state where the gate electrode 16 is formed. Fig. 17 is a cross-sectional view for explaining a conventional example, and shows a state where the protective film 19, the source electrode 2, the drain electrode 24, and the wiring layer 25 are formed. Fig. 18 is a sectional view for explaining a conventional example, and shows a state where a silicon nitride film 26 and an electrode 27 for plating are formed. FIG. 19 is a cross-sectional view for explaining a conventional example, and shows a state where a source electrode 28, a drain electrode 29, and a pad electrode 31 are formed.

313692 pic 第23頁 565948 _案號 91110605_f 1年蓼月曰_^_ 圖式簡單說明 第2 0圖係用以說明習知例之剖視圖，為表示壓接搭接 線4 0之狀態。 卜 3卜 51 基 板 2 N型通道層 3、 26^ 53 氮 化 矽 膜 4、 20、 8、1 3、 Η [、 3C 卜 54 ^ 58 、63、 67^ 7卜 73 光 阻 層 5 ^ 55 P- -型 區 域 6、 56 源 極區 域 7、 57 汲 極 區 域 10^ 64 歐 姆金 屬 層 1 1 > 65 第 一 源 極 12、 66 第 一汲 極 16^ 33 ^ 69 閘 極 17 第 一墊 極 18^ 68 閘 金 屬 層 19' 72 保 護膜 21 配 線 金 屬 層 23^ 24 第 二源 極 與 汲: 25〜 62 配 線 層 27 電 鍍 用 電 極 28' 29 第 三源 極 與 汲: 32 N型通道區域 34 源 極 35 汲 極 40 打 線接 合 52 通 道 層 60 ^ 61 高 濃 度 區 域 70 第 一鲜 墊 電 極 70a 、70b 銲 墊 電 極 74 銲 墊金 屬 層 75 第 二 源 極 76 第 — >及 極 77 第 二 銲 墊 電 極 80 搭 接線 Ct 1 -1 第 一 控 制 端 子 Ct 1 -2 第 二控 制 端 子 IN m 入 端 子 OUT1 第 一輸 出 端 子313692 pic Page 23 565948 _Case No. 91110605_f Brief description of the drawing in one year _ ^ _ Figure 20 is a cross-sectional view for explaining the conventional example, and shows the state of the crimped overlap line 40. Bu 3 bu 51 substrate 2 N-type channel layer 3, 26 ^ 53 silicon nitride film 4, 20, 8, 1 3, Η [, 3C bu 54 ^ 58, 63, 67 ^ 7 bu 73 photoresist layer 5 ^ 55 P-type region 6, 56 source region 7, 57 drain region 10 ^ 64 ohm metal layer 1 1 > 65 first source 12, 66 first drain 16 ^ 33 ^ 69 gate 17 first pad Electrode 18 ^ 68 gate metal layer 19 '72 protective film 21 wiring metal layer 23 ^ 24 second source and drain: 25 ~ 62 wiring layer 27 electrode for plating 28' 29 third source and drain: 32 N-type channel area 34 source 35 drain 40 wire bonding 52 channel layer 60 ^ 61 high concentration area 70 first pad electrode 70a, 70b pad electrode 74 pad metal layer 75 second source 76th — > and pole 77 second Pad electrode 80 Overlap Ct 1 -1 First control terminal Ct 1 -2 Second control terminal IN m Input terminal OUT1 First output Terminal

313692 ptc 第24頁 565948313692 ptc page 24 565948

333692 ptc 第25頁333692 ptc Page 25

Claims (1)

565948 _案號91110605 f2年！月4曰 修正_ 六、申請專利範圍 1. 一種化合物半導體裝置之製造方法，其特徵為具備： 在附著用以形成閘極之閘金屬層的步驟之前，於 預定之銲墊區域下方的半導體基板表面上，形成高濃 度區域的步驟； 在上述高濃度區域上附著該閘金屬層，並形成第 一銲墊電極的步驟； 在上述第一銲墊電極上附著銲墊金屬層，並形成 第二銲墊電極的步驟；以及 在上述第二銲墊電極上壓接搭接線的步驟。 2. —種化合物半導體裝置之製造方法，其特徵為具備： 在附著用以形成閘極之閘金屬層的步驟之前，於 預定之銲墊區域下方及預定之配線層下方之半導體基 板表面上，形成高濃度區域的步驟； 在上述高濃度區域上附著上述閘金屬層，並形成 第一銲墊電極與配線層的步驟； 在上述第一銲墊電極上附著銲墊金屬層，並形成 第二銲墊電極的步驟；以及 在上述第二銲墊電極上壓接搭接線的步驟。 3. —種化合物半導體裝置之製造方法，其特徵為具備： 在基板表面上形成通道層的步驟； 鄰接上述通道層而形成源極與汲極區域，同時在 預定之銲墊區域下方形成高濃度區域的步驟； 在上述源極及汲極區域上，附著第一層電極的歐 姆金屬層並形成第一源極與第一汲極的步驟；565948 _ case number 91110605 f2 years! March 4th revision_ VI. Patent application scope 1. A method for manufacturing a compound semiconductor device, comprising: a semiconductor substrate under a predetermined pad area before a step of forming a gate metal layer for a gate is attached; A step of forming a high-concentration area on the surface; a step of attaching the gate metal layer on the high-concentration area and forming a first pad electrode; attaching a pad metal layer on the first pad electrode and forming a second A step of bonding pad electrodes; and a step of crimping bonding wires on the second pad electrode. 2. A method for manufacturing a compound semiconductor device, comprising: before attaching a gate metal layer for forming a gate electrode, on a surface of a semiconductor substrate under a predetermined pad area and under a predetermined wiring layer, A step of forming a high-concentration region; a step of attaching the gate metal layer on the high-concentration region and forming a first pad electrode and a wiring layer; attaching a pad metal layer on the first pad electrode and forming a second A step of bonding pad electrodes; and a step of crimping bonding wires on the second pad electrode. 3. A method for manufacturing a compound semiconductor device, comprising: a step of forming a channel layer on a substrate surface; forming a source and a drain region adjacent to the channel layer, and forming a high concentration under a predetermined pad region; A region step; a step of attaching an ohmic metal layer of a first layer of electrodes on the source and drain regions to form a first source and a first drain; 313692 ptc 第26頁 565948 _案號91110605 灸年f月4曰 修正_ 六、申請專利範圍 在上述通道層與上述高濃度區域上附著第二層電 極的閘金屬層，並形成閘極與第一銲墊電極的步驟； 在上述第一源極、第一汲極及上述第一銲墊電極 上，附著第三層電極的銲墊金屬層，並形成第二源 極、第二汲極及第二銲墊電極的步驟；以及 在上述第二銲墊電極上壓接搭接線的步驟。 4. 一種化合物半導體裝置之製造方法，其特徵為具備： 在基板表面上形成通道層的步驟； 鄰接上述通道層而形成源極與汲極區域，同時在 預定之鲜墊區域下方與預定之配線層下方，形成高濃 度區域的步驟； 在上述源極及汲極區域上，附著第一層電極的歐 姆金屬層並形成第一源極與第一汲極的步驟； 在上述通道層與上述高濃度區域上，附著第二層 電極的閘金屬層，並形成閘極、第一銲墊電極及配線 層的步驟； 在上述第一源極、第一沒極及上述第一鲜塾電極 上，附著第三層電極的銲墊金屬層，並形成第二源 極、第二汲極及第二銲墊電極的步驟；以及 在上述第二銲墊電極上壓接搭接線的步驟。 5. 如申請專利範圍第1項或第3項之化合物半導體裝置之 製造方法，其特徵為上述高濃度區域係由上述銲墊電 極突出而設置。 6. 如申請專利範圍第2項或第4項之化合物半導體裝置之313692 ptc page 26 565948 _ case number 91110605 year of moxibustion f March 4 amendment _ six, the scope of the patent application for the above-mentioned channel layer and the above-mentioned high-concentration area attached to the second electrode of the gate metal layer, and form the gate and the first Steps of pad electrodes; a pad metal layer of a third layer electrode is attached to the first source electrode, the first drain electrode, and the first pad electrode, and a second source electrode, a second drain electrode, and a first pad electrode are formed; A step of two pad electrodes; and a step of crimping and bonding wires on the second pad electrode. 4. A method for manufacturing a compound semiconductor device, comprising: a step of forming a channel layer on a surface of a substrate; forming a source and a drain region adjacent to the channel layer; and simultaneously with a predetermined wiring under a predetermined pad area A step of forming a high-concentration region under the layer; a step of attaching an ohmic metal layer of a first layer of electrode on the source and drain regions to form a first source and a first drain; The step of attaching the gate metal layer of the second layer electrode to form the gate electrode, the first pad electrode, and the wiring layer on the concentration region; on the first source electrode, the first electrode, and the first fresh electrode, A step of attaching a pad metal layer of a third layer electrode to form a second source electrode, a second drain electrode, and a second pad electrode; and a step of crimping a bonding wire on the second pad electrode. 5. The method for manufacturing a compound semiconductor device according to item 1 or item 3 of the patent application scope, characterized in that the high-concentration region is provided by protruding the pad electrode. 6. If applying for a compound semiconductor device in the second or fourth scope of the patent application 313692 pic 第27頁 565948 _案號91110605 年次月>7曰 修正_ 六、申請專利範圍 製造方法，其特徵為上述高濃度區域係由上述銲墊電 極與上述配線層突出而設置。 7. 如申請專利範圍第1項或第3項之化合物半導體裝置之 製造方法，其特徵為上述高濃度區域係在上述銲墊電 極周端部的下方之其中一部分由上述銲墊電極突出而 設置。 8. 如申請專利範圍第2項或第4項之化合物半導體裝置之 製造方法，其特徵為上述高濃度區域係在上述銲墊電 極周端部與上述配線層周端部的下方之其中一部分由 上述銲墊電極與上述配線層突出而設置。 9. 如申請專利範圍第1項至第4項中任一項之化合物半導 體裝置之製造方法，其特徵為具備：上述閘金屬層的最 下層蒸鍍上構成P t的金屬多層膜之後，經熱處理而將 上述閘極的其中一部分埋入上述基板表面中的步驟。 1 0 .如申請專利範圍第1項至第4項中任一項之化合物半導 體裝置之製造方法，其特徵為上述高濃度區域係經由 離子植入而設置。 1 1.如申請專利範圍第3項或第4項之化合物半導體裝置之 製造方法，其特徵為上述通道區域係經由離子植入而 設置。313692 pic Page 27 565948 _Case No. 91110605 Month > 7th Amendment_ VI. Patent Application Scope The manufacturing method is characterized in that the above-mentioned high-concentration area is provided by protruding the pad electrode and the wiring layer. 7. The method for manufacturing a compound semiconductor device according to item 1 or item 3 of the patent application, wherein the high-concentration region is provided below the peripheral end portion of the pad electrode and a part of the pad electrode projects from the pad electrode. . 8. If the method of manufacturing a compound semiconductor device according to item 2 or item 4 of the patent application scope is characterized in that a part of the high-concentration region is below the peripheral end portion of the pad electrode and the peripheral end portion of the wiring layer, The pad electrode and the wiring layer are provided to protrude. 9. The method for manufacturing a compound semiconductor device according to any one of claims 1 to 4 of the scope of patent application, characterized in that the method comprises: depositing a metal multilayer film constituting Pt on the lowermost layer of the gate metal layer, A step of burying a part of the gate electrode in the surface of the substrate by heat treatment. 10. The method for manufacturing a compound semiconductor device according to any one of claims 1 to 4 of the scope of patent application, characterized in that the high-concentration region is provided by ion implantation. 1 1. The method for manufacturing a compound semiconductor device according to item 3 or 4 of the scope of patent application, wherein the above-mentioned channel region is provided by ion implantation. 313692 ptc 第28頁 56S04g. 修正 補充313692 ptc Page 28 56S04g. Correction Supplement 第4圖修正圖 69 62 70 68Figure 4 Correction 69 62 70 68 第5圖Figure 5 69 62 7069 62 70 565948565948 Π + η r 门十 1 p 1 1 2 第16圖修正圖Π + η r gate ten 1 p 1 1 2 Figure 16 Correction 第17圖修正圖Figure 17 Revision 第18圖Figure 18
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