JP2003007724A - Method of manufacturing compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a compound semiconductor device especially using a GaAs substrate which eliminates the drawback that a silicon nitride film is apt to break at bonding because of the hardness of a substrate and the film by removing the silicon nitride film formed beneath pad electrodes until the final step for safety. SOLUTION: According to the manufacturing method, high concentration regions are provided beneath pad electrodes and a wiring layer or beneath the peripheral edge and a silicon nitride film beneath the pad electrodes is removed. The high concentration regions ensure a specified isolation after removal of the nitride film, this allowing the break-preventing gold plating step to be omitted and the spacing between each pad and the wiring layer to be reduced to realize the chip shrinkage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for manufacturing a compound semiconductor device using a GaAs substrate.

[0002]

2. Description of the Related Art In mobile communication devices such as mobile phones, G
In many cases, microwaves in the Hz band are used, and switching elements for switching these high-frequency signals are often used in antenna switching circuits, transmission / reception switching circuits, and the like (for example, Japanese Patent Laid-Open No. 9-181642). issue). As its element, since it handles high frequencies, a field effect transistor (hereinafter referred to as FE) using gallium arsenide (GaAs) is used.
In most cases, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated is being developed.

FIG. 11A shows a sectional view of a GaAs FET. The surface portion of the undoped GaAs substrate 31 is doped with an n-type impurity to form an n-type channel region 32.
, The gate electrode 33 is formed on the surface of the channel region 32 in Schottky contact, and the source / drain electrodes 34, 35 in ohmic contact with the GaAs surface are arranged on both sides of the gate electrode 33. This transistor forms a depletion layer in the channel region 32 immediately below by the potential of the gate electrode 33, thereby controlling the channel current between the source electrode 34 and the drain electrode 35.

FIG. 11B shows a principle circuit diagram of a compound semiconductor switch circuit device called SPDT (Single Pole Double Throw) using a GaAs FET.

Sources (or drains) of the first and second FET1 and FET2 are connected to a common input terminal IN, and each F
The gates of ET1 and FET2 are connected to the first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2,
The drain (or source) of each FET is the first and second
Of the output terminals OUT1 and OUT2. The signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET applied with the H level signal is turned on to determine which signal is applied to the input terminal IN. It is designed to be transmitted to one of the output terminals. The resistors R1 and R2 are control terminals Ctl that are AC grounded.
It is arranged for the purpose of preventing a high frequency signal from leaking through the gate electrode with respect to the DC potential of -1, Ctl-2.

The F of such a compound semiconductor switch circuit device
A method of manufacturing the ET, the pad and the wiring is shown in FIGS.

In FIG. 12, the channel layer 2 is formed on the surface of the substrate 1.

That is, the entire surface of the substrate 1 is covered with a silicon nitride film 3 for through ion implantation having a thickness of about 100Å. Next, a photolithography process of selectively opening the resist layer 4 on the intended channel layer 2 is performed. afterwards,
Using this resist layer 4 as a mask, ion implantation of an impurity giving ap ⁻ type and ion implantation of an impurity giving an n type are performed in order to select an operation layer into a predetermined channel layer 2. As a result, the p ⁻ type region 5 and the n type channel layer 2 are formed on the non-doped substrate 1.

In FIG. 13, a source region 6 and a drain region 7 are formed on the surface of the substrate 1 adjacent to both ends of the channel layer 2.

The resist layer 4 used in the previous step is removed, and a photolithography process is performed to selectively open the resist layer 8 on the newly planned source region 6 and drain region 7. Then, using the resist layer 8 as a mask, ion implantation of impurities imparting n-type is performed to the planned source region 6 and drain region 7 to form the n ⁺ -type source region 6 and drain region 7.

In FIG. 14, the ohmic metal layer 10 as the first electrode is formed in the source region 6 and the drain region 7.
Attached to the first source electrode 11 and the first drain electrode 1
Form 2.

A photolithography process for selectively opening windows in portions where the first source electrode 11 and the first drain electrode 12 are to be formed is performed. Planned first source electrode 1
The silicon nitride film 3 on the first and first drain electrodes 12 is removed by CF ₄ plasma, and subsequently, three layers of AnGe / Ni / Au to be the ohmic metal layer 10 are sequentially vacuum-deposited and laminated. Then, the resist layer 13 is removed, and the first source electrode 11 and the first drain electrode 12 are formed on the source region 6 and the drain region 7 by lift-off.
Leave. Subsequently, an alloying heat treatment is performed to form ohmic contacts between the first source electrode 11 and the source region 6 and between the first drain electrode 12 and the drain region 7.

In FIG. 15, a photolithography process for selectively opening a predetermined gate electrode 16 portion is performed.

In FIG. 16, after the exposed nitride film 3 is dry-etched, Ti / Pt / Au to be the gate metal layer 18 is formed.
Are sequentially vacuum-deposited and laminated. After that, the resist layer 14 is removed and lift-off is performed to form a gate electrode 16 and a first pad electrode 17 having a gate length of 0.5 μm and contacting the channel layer 2.

In FIG. 17, after forming the passivation film 19, the second source and drain electrodes 23 and 24 and the wiring layer 25 are formed.

After forming the gate electrode 16, the surface of the substrate 1 is covered with a passivation film 19 made of a silicon nitride film in order to protect the channel layer 2 around the gate electrode 16. A photolithography process is performed on this passivation film 19, and a resist window is selectively opened in a contact portion with the first source and drain electrodes 11 and 12 and a contact portion with the gate electrode 16 to passivate the portion. The film 19 is dry-etched. After that, the resist layer is removed.

Then, the second source and drain electrodes 2
3, 24 and the wiring layer 25 are formed. A new photolithography process is performed on the entire surface of the substrate 1 to remove the first source electrode 1
First, the first drain electrode 12 portion and the passivation film 19 on the predetermined wiring layer 25 are exposed, and the others are covered with the resist layer 20. Then, three layers of Ti / Pt / Au, which will be the wiring metal layer 21 as the third electrode, are sequentially vacuum-deposited and laminated on the entire surface. Since the resist layer 20 is used as a mask as it is, the second source electrode 23 and the second drain electrode 24, which are in contact with the first source electrode 11 and the first drain electrode 12, and the wiring layer 25 are formed. Since the other part of the wiring metal layer 21 is attached on the resist layer 20, the resist layer 20 is removed and the second portion is lifted off.
Source electrode 23, second drain electrode 24, and wiring layer 2
Only 5 are left and the others are removed. Since a part of the wiring portion is formed by using this wiring metal layer 21, the wiring metal layer 21 of that wiring portion is naturally left.

In FIG. 18, a nitride film 26 for an interlayer insulating film is formed and a plating electrode 27 is formed.

The surface of the substrate 1 is covered with an interlayer insulating film 26 made of a silicon nitride film in order to realize multi-layer wiring. A photolithography process is performed on the interlayer insulating film 26 to selectively open a window of a resist with respect to the contact portion with the second source and drain electrodes 23 and 24 and the contact portion with the wiring electrode 25, and the passivation film 1 at that portion is opened.
9 is dry-etched. After that, the resist layer is removed.

After that, the plating electrode 27 is formed. Three layers of Ti / Pt / Au to be the plating electrodes 27 are sequentially vacuum-deposited and laminated on the entire surface. Since contact holes are provided in predetermined portions of the second source and drain electrodes 23, 24 and the wiring electrode 25, the plating electrode 27 makes contact.

In FIG. 19, gold plating is applied to form pad electrodes 31 for fixing the third source and drain electrodes 28 and 29 and bonding wires.

A photolithography process is performed on the substrate 1, and the planned third source electrode 28 and third drain electrode 29 are formed.
Then, the plating electrode 27 at the planned pad electrode 31 is exposed and the other part is covered with the resist layer 30, and then electrolytic gold plating is performed. At that time, the resist layer 30 serves as a mask, and gold plating adheres only to the exposed portion of the plating electrode 27. That is, the second source electrode 23 and the second drain electrode 2
A pad electrode 31 for fixing the bonding wire to the third source electrode 28 and the third drain electrode 29 which contact the electrode 4 is formed.

In FIG. 20, the pad electrode 31 is finally formed, and the bonding wire 40 is pressure-bonded thereon.

After removing the resist 30, the unnecessary plating electrode 27 exposed on the entire surface is removed. No plating electrodes other than the gold-plated third source electrode 28, third drain electrode 29, and pad electrode 31 are required. When ion milling with Ar plasma is performed, the plating electrode in the portion not plated with gold is scraped off to expose the interlayer insulating film 26. The gold-plated portion is also slightly scraped, but there is no problem because it has a thickness of about 2 to 3 μm. Since a part of the wiring portion is formed by using this gold plating, the plating electrode 27 and the gold plating of that wiring portion are naturally left.

When the compound semiconductor switch circuit device has completed the pre-process, it is moved to the post-process for assembling. The wafer-shaped semiconductor chip is diced into individual semiconductor chips, and the semiconductor chips are fixed to a frame (not shown). Then, a pad electrode 31 of the semiconductor chip and a predetermined lead (not shown) are bonded by a bonding wire 40. ) And connect. A thin gold wire is used as the bonding wire 40 and is connected by well-known ball bonding. afterwards,
Transfer molding is performed and a resin package is applied.

[0026]

Although the GaAs substrate is semi-insulating, when a pad electrode layer for wire bonding is directly provided on the substrate, electrical interaction between adjacent electrodes still exists. For example, since the insulation strength is weak, electrostatic breakdown occurs, high-frequency signals leak, and the isolation is deteriorated. Therefore, in the conventional manufacturing method, a nitride film is laid under the wiring layer and the pad electrode layer.

However, since the nitride film is hard, the pad portion is cracked by the pressure during bonding. In order to suppress this, the bonding electrode on the nitride film is treated by applying gold plating, but the gold plating process increases the number of processes and also increases the cost.

Further, in the conventional compound semiconductor device, when the pad and the wiring layer are formed in contact with the semi-insulating GaAs substrate, a separation distance of 20 μm or more is provided between the adjacent electrodes to ensure isolation. It was Although this theoretical backing is poor, it has been thought that the semi-insulating GaAs substrate has an infinite breakdown voltage from the idea that it is an insulating substrate. However, it was found that the breakdown voltage was finite when actually measured. For this reason, the depletion layer expands in the semi-insulating GaAs substrate, and due to the change in the depletion layer distance depending on the high frequency signal, when the depletion layer reaches the adjacent electrode, the high frequency signal may leak there. . Therefore, the electrodes such as the pad electrode layer and the wiring layer have a thickness of 20 μm.
The above-mentioned separation distance is provided.

However, in the above-described compound semiconductor device, the five pads occupy nearly half of the semiconductor chip, which is a major factor that the chip size cannot be reduced.

At present, the performance of silicon semiconductor chips is remarkably improved, and the possibility of use in the high frequency band is increasing. Conventionally, it was difficult to use silicon chips in the high frequency band, and expensive compound semiconductor chips were used, but if the possibility of using silicon semiconductors increases, naturally compound wafers with high wafer prices will lose in price competition. I will end up. For this reason, it is inevitable to shrink the chip size to reduce the cost, and it is inevitable to reduce the chip size.

[0031]

The present invention has been made in view of the above-mentioned various circumstances, and the nitride film under the pad electrode is removed to suppress the influence of the pressure at the time of wire bonding. By providing a high-concentration region under the electrode and a high-concentration region under the gate metal used as the wiring, the distance between adjacent pad electrodes and wiring electrodes can be reduced, and the chip size can be shrunk. A feature of the present invention is to provide a method for manufacturing a compound semiconductor device that realizes an electrode structure without increasing the number of steps.

That is, a step of forming a channel layer on the surface of the substrate, a step of forming source and drain regions in contact with the channel layer, and a step of simultaneously forming a high concentration region under a predetermined pad region and a predetermined wiring layer. And a step of depositing an ohmic metal layer as a first-layer electrode on the source and drain regions to form first source and first drain electrodes, and a second layer on the channel layer and the high-concentration region. A gate metal layer as an electrode for forming a gate electrode, a first pad electrode and a wiring layer, and as a third layer electrode on the first source and first drain electrodes and the first pad electrode. A pad metal layer to form second source and second drain electrodes and a second pad electrode, and a bonding wire on the second pad electrode. Characterized by comprising the step of wearing.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS.

According to the present invention, the channel layer 52 is formed on the surface of the substrate 51.
And forming source and drain regions 56 and 57 in contact with the channel layer 52, and simultaneously forming a high concentration region 60 under a planned pad region and a planned wiring layer.
61, and a step of forming a first source and drain electrode 65 by depositing an ohmic metal layer 64 as a first layer electrode on the source and drain regions 56 and 57.
66, and a gate metal layer 68 as a second-layer electrode is attached on the channel layer 52 and the high-concentration regions 60 and 61 to form a gate electrode 69, a first pad electrode 70, and a wiring layer 62. Forming step and the first
A pad metal layer 74 as a third electrode is deposited on the source / first drain electrodes 65, 66 and the first pad electrode 70 to form second source / second drain electrodes 75,
76 and the second pad electrode 77, and the second step
And a step of crimping the bonding wire 80 onto the pad electrode 77.

The first step of the present invention is as shown in FIG.
The purpose is to form the channel layer 52 on the surface of the substrate 51.

That is, the entire surface of the compound semiconductor substrate 51 made of GaAs or the like is covered with the through-ion implantation silicon nitride film 53 having a thickness of about 100 Å to 200 Å. Next, a photolithography process for selectively opening the resist layer 54 on the predetermined channel layer 52 is performed. Then, using this resist layer 54 as a mask, ion implantation of an impurity (24Mg ⁺ ) for giving a p-type and an impurity for giving an n-type for selecting an operation layer into a predetermined channel layer 52.
Ion implantation of (29Si ⁺ ) is performed.

As a result, p ⁻ is formed on the non-doped substrate 51.
The mold region 55 and the n-type channel layer 52 are formed thereon.

The second step of the present invention is as shown in FIG.
A source region 56 and a drain region 57 are formed in contact with the channel layer 52, and at the same time, high-concentration regions 60 and 61 are formed under a planned pad region 70 and a planned wiring layer 62.

This step is the first characteristic step of the present invention, in which the resist layer 54 used in the previous step is removed, and a new source region 56, a drain region 57, a predetermined wiring layer 62 and A photolithography process is performed to selectively open the resist layer 58 on the pad region 70.
Then, using the resist layer 58 as a mask, the planned source region 56 and drain region 57 and the planned wiring layer 62 are formed.
Then, ion implantation of an impurity (29Si ⁺ ) giving n-type is performed on the substrate surface below the pad electrode 70. This gives n ⁺
Forming a source region 56 and a drain region 57 of the mold,
At the same time, high-concentration regions 60 and 61 are formed on the surface of the substrate below the planned pad region 70 and wiring layer 62. What is important here is that the high-concentration regions 60 and 61 are the planned pad electrodes 7.
0 and the resist layer 5 so as to protrude from the wiring layer 62.
8 is to be removed. As a result, high-concentration regions 60 and 61, which are larger than those regions, are formed below the pad electrode 70 and the wiring layer 62 which will be formed in a later step.

When a pad electrode or a wiring layer is directly provided on a GaAs substrate, a high frequency signal may leak when the depletion layer reaches an adjacent electrode or wiring layer due to a change in the depletion layer distance according to a high frequency signal. Can be considered.

However, the pad electrode 70 and the wiring layer 62
If n + -type high-concentration regions 60 and 61 are provided on the surface of the lower substrate 51, the substrate 51 not doped with impurities
(Although it is semi-insulating, the substrate resistance is 1 × 10 ⁷ Ω ・ c
m) Unlike the surface, the impurity concentration is high (ionic species
29Si ⁺ with a concentration of 1-5 × 10 ⁸ cm ^-3 ). As a result, the wiring layer 62 and the pad electrode 70 are separated from the substrate 51, and the depletion layer for the pad electrode 70 and the wiring layer 62 does not extend. Therefore, the adjacent pad electrode 70 and the wiring layer 62 are greatly separated from each other. Can be provided later.

Specifically, if the separation distance is 4 μm,
It was determined to be sufficient to ensure an isolation of 20 dB or more. Also, in the electromagnetic field simulation, if a separation distance of about 4 μm is provided, 2.4 GHz
It has been found that the isolation of about 40 dB can be obtained.

That is, the pad electrode 70 and the wiring layer 62.
By providing the high-concentration regions 60 and 61 so as to protrude below these regions, even if the pad electrode 70 and the wiring layer 62 are directly provided on the GaAs substrate, sufficient isolation can be ensured, so that conventional safety is ensured. The nitride film provided for that purpose can be removed.

If the nitride film is unnecessary, it is not necessary to consider the fact that the nitride film is cracked when the bonding wire is pressure-bonded, so that the gold plating step which has been conventionally required can be omitted. Since the gold plating process has many processes and is costly, if this process can be omitted, it can greatly contribute to simplification of the manufacturing process and cost reduction.

Furthermore, even if the distance between the pad electrodes 70 or the wiring layers 62 adjacent to each other is reduced to 4 μm,
Sufficient to ensure isolation of dBm.
For example, in a compound semiconductor device in which five pads occupy nearly half of a semiconductor chip, it is possible to significantly shrink the chip size, and the cost of the compound semiconductor device can be reduced.

The third step of the present invention is as shown in FIG.
A first source electrode 65 and a first drain electrode 66 are formed by attaching an ohmic metal layer 64 as a first layer electrode to the source region 56 and the drain region 57.

First, a photolithography process for selectively opening windows in portions where the first source electrode 65 and the first drain electrode 66 are to be formed is performed. The planned silicon nitride film 53 on the first source electrode 65 and the first drain electrode 66 is removed by CF ₄ plasma, and then three layers of AnGe / Ni / Au to be the ohmic metal layer 64 are sequentially vacuum-deposited. Stack. Then, the resist layer 63 is removed, and the first source electrode 65 and the first drain electrode 66 contacting the source region 56 and the drain region 57 are left by lift-off. Then, the first source electrode 65 and the source region 5 are subjected to alloying heat treatment.
6, and an ohmic junction between the first drain electrode 66 and the drain region 57 is formed.

In the fourth step of the present invention, as shown in FIGS. 4 to 6, the channel layer 52 and the high concentration region 6 are formed.
A gate metal layer 68 as a second electrode on 0, 61
To form the gate electrode 69, the first pad electrode 70 and the wiring layer 62.

This step is the second characteristic step of the present invention. As a first embodiment, first, in FIG. 4, a photolithography process for selectively opening windows of the planned gate electrode 69, pad electrode 70 and wiring layer 62 is performed. The silicon nitride film 53 exposed from the planned gate electrode 69, the pad electrode 70, and the wiring layer 62 is dry-etched to expose the channel layer 52 at the planned gate electrode 69, and the planned wiring layer 62 and the planned pad. The substrate 51 of the electrode 70 portion is exposed.

The planned opening of the gate electrode 69 portion is 0.
The gate electrode 69 having a size of 5 μm can be formed. At this time, as described in the second step, the nitride film, which was conventionally required to secure the isolation, can be removed by providing the high concentration regions 60 and 61. By the impact of, the nitride film and the substrate are not cracked.

In FIG. 5, a gate metal layer 68 as an electrode of the second layer is attached to the channel layer 52 and the exposed substrate 51 to form a gate electrode 69, a wiring layer 62 and a first pad electrode 70.

That is, three layers of Ti / Pt / Au, which will be the gate metal layer 68 as the second electrode, are sequentially vacuum-deposited and laminated on the substrate 51. Then, the resist layer 67 is removed, and a gate electrode 69 having a gate length of 0.5 μm, which contacts the channel layer 52, a first pad electrode 70, and a wiring layer 62 are formed by lift-off.

As a second embodiment, a part of the gate electrode 69 may be embedded in the channel layer 52 as shown in FIG. In that case, Pt / is used as the gate metal layer 68.
Four layers of Ti / Pt / Au are sequentially vacuum-deposited and laminated.
After that, the gate electrode 69, the first pad electrode 70, and the wiring layer 62 are formed by lift-off, and then heat treatment for burying Pt is performed. As a result, as shown in FIG. 6, the gate electrode 69 is partially embedded in the channel layer 52 while maintaining the Schottky junction with the substrate. Here, the depth of the channel layer 52 in this case is formed so as to obtain a desired FET characteristic in consideration of the embedded portion of the gate electrode 69 when the channel layer 52 is formed in the first step. I'll do it.

The surface of the channel layer 52 (for example, 50 from the surface)
0 Å ~ 1000 Å), a natural depletion layer occurs,
Current does not flow because the crystal is in a non-uniform region, so it is not effective as a channel. By embedding a part of the gate electrode 69 in the channel region 52, the portion of the current flowing directly below the gate electrode 69 is lowered from the surface of the channel region 52. Since the channel region 52 is deeply formed in consideration of the embedded portion of the gate electrode 69 so that desired FET characteristics can be obtained in advance, it can be effectively used as a channel. Specifically, it has an advantage that the current density, channel resistance, and high frequency distortion characteristics are significantly improved.

In any case, since the nitride film under the pad electrode 70 and the wiring layer 62 can be removed, cracks will not occur. Further, conventionally, it was necessary to prevent electrostatic breakdown and ensure isolation, but the high concentration region 60 is formed on the substrate 51 under the pad electrode 70 and the wiring layer 62.
By providing 61, the expansion of the depletion layer can be suppressed and a predetermined isolation can be secured.

As described above, if the nitride film is unnecessary, the gold plating step provided for suppressing the cracking is unnecessary, so that the cost can be greatly reduced and the manufacturing process can be simplified.

In the fifth step of the present invention, as shown in FIGS. 7 and 8, a third layer electrode is formed on the first source electrode 65, the first drain electrode 66, and the first pad electrode 70. The pad metal layer 74 is deposited to form the second source and second drain electrodes 75 and 76 and the second pad electrode 77.

In FIG. 7, the first source electrode 65 and the first source electrode 65
Contact holes are formed in the passivation film 72 on the drain electrode 66 and the first pad electrode 70.

After forming the gate electrode 69, the wiring layer 62 and the first pad electrode 70, in order to protect the channel layer 52 around the gate electrode 69, the surface of the substrate 51 is covered with a passivation film 72 of a silicon nitride film. It
A photolithography process is performed on the passivation film 72 to selectively open a resist window for the contact portions with the first source electrode 65, the first drain electrode 66, and the first pad electrode 70, and The passivation film 72 is dry-etched. afterwards,
The resist layer 71 is removed.

In FIG. 8, the first source electrode 65 and the first source electrode 65
A pad metal layer 74 as a third layer electrode is attached on the drain electrode 66 and the first pad electrode 70, and the second source electrode 75, the second drain electrode 76, and the second pad electrode 77 are attached.
To form.

A new resist layer 73 is applied on the entire surface of the substrate 51, and a photolithography process is performed to perform a second
A photolithography process of selectively opening the resist on the source electrode 75, the second drain electrode 76, and the second pad electrode 77 is performed. Subsequently, three layers of Ti / Pt / Au, which will be the pad metal layer 74 as the third-layer electrode, are sequentially vacuum-deposited and laminated to form the first source electrode 65, the first source electrode 65, and the first source electrode 65.
A second source electrode 75 and a second drain electrode 76 that contact the drain electrode 66 and the first pad electrode 70.
Then, the second pad electrode 77 is formed. Pad metal layer 74
Since the other portions are attached on the resist layer 73, the resist layer 73 is removed and lift-off is performed to remove the second source electrode 75, the second drain electrode 76, and the second pad electrode 77.
Only the others are left and the others are removed. Since a part of the wiring portion is formed by using the pad metal layer 74, the pad metal layer 74 of the wiring portion is naturally left.

The sixth step of the present invention is as shown in FIG.
The bonding wire 80 is pressure-bonded onto the second pad electrode 77. FIG. 9A shows the case of the first embodiment of the present invention, and FIG. 9B shows the case of the second embodiment of the present invention.

In this step, as described above, the high concentration region 60,
61 by the first pad electrode 70 and the second pad electrode 7
Since the nitride film under 7 can be removed, cracking can be prevented when the bonding wire is pressure bonded.

When the compound semiconductor switch circuit device completes the pre-process, it is moved to the post-process for assembling. The wafer-shaped semiconductor chip is diced into individual semiconductor chips, and the semiconductor chips are fixed to a frame (not shown), and then the second pad electrodes 77 of the semiconductor chip and predetermined leads (see FIG. (Not shown)
And connect. A thin gold wire is used as the bonding wire 80 and is connected by a well-known ball bonding. After that, transfer molding is performed and a resin package is applied.

The high-concentration region is shown in FIGS. 10 (a) and 10 (b).
As shown in FIG. 7, a window may be selectively opened in the resist by a photolithography process, and the resist may be provided below the peripheral edge of the planned wiring layer 62 and below the peripheral edge of the planned pad electrode 70. Even in this case, the wiring layer 62 and the pad electrode 70 are provided so as to partially protrude from the wiring layer 62 and the pad electrode 70.

FIG. 10C shows an arrangement example of the high concentration regions 60 and 61. The high-concentration regions 60 and 61 are pad electrodes 70.
Although it may be provided so as to surround the periphery of the wiring layer 62,
It may be provided as shown in FIG. That is, the pad electrode 70a is provided with the high-concentration regions 60 along the three sides except the upper side, and the pad electrode 70b is formed in the C-shaped high concentration along the four sides of the irregular pentagon except the corner portions of the GaAs substrate. A region 60 is provided. All the portions not provided with the high concentration region 40 are the portions facing the peripheral edge of the GaAs substrate,
Even if the depletion layer expands, there is a sufficient separation distance from the adjacent pad or wiring, and the leak is not a problem.

The high-concentration region 61 has pad electrodes 70.
It is selectively provided under the wiring layer 62 on the side close to a and 70b.

These examples of arrangement are merely examples, and it is sufficient that they have a function of preventing the high-frequency signal applied to the pad electrode 70 from being transmitted to the wiring layer 62 via the substrate 51. still,
Although omitted in FIG. 10, the gate electrode 69 may be embedded in the surface of the channel layer 52 as in the second embodiment of the present invention.

[0069]

As described in detail above, according to the present invention, the following effects can be obtained.

First, due to the high concentration region provided on the substrate,
Since the pad electrode and the wiring layer can be separated from the substrate, the nitride film conventionally provided for ensuring sufficient isolation can be removed. If the nitride film is not necessary, the gold plating step, which is performed to prevent cracking of the nitride film during bonding, can be omitted. Since the gold plating step has many steps and is high in cost, if this step can be omitted, it is possible to realize a method for manufacturing a compound semiconductor device which is low in cost and has a simplified flow.

Second, the high-concentration region allows the pad electrode and the wiring layer to be separated from the substrate, which can prevent dielectric breakdown and interference, and can greatly reduce the distance between adjacent electrodes. Specifically, in the case of ensuring isolation of 20 dBm, it is possible to dispose them close to each other up to 4 μm, which can greatly contribute to the shrink of the chip size. That is, it is possible to manufacture a high-quality compound semiconductor device at low cost.

Third, the gate metal layer is Pt / Ti / Pt
By using / Au and burying a part of the gate electrode in the channel region by heat treatment, the portion where the current flows directly below the gate electrode can be lowered from the surface of the channel region. The channel surface is a region that is not effective as a channel, and the channel can be effectively used by embedding the gate electrode, so that the current density, the channel resistance, and the high frequency distortion characteristics are significantly improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

FIG. 7 is a sectional view for explaining the present invention.

FIG. 8 is a sectional view for explaining the present invention.

FIG. 9 is a cross-sectional view for explaining the present invention.

FIG. 10A is a sectional view for explaining the present invention,
It is a sectional view and (c) top view.

FIG. 11 is a sectional view (A) for explaining a conventional example;
(B) A circuit diagram.

FIG. 12 is a cross-sectional view for explaining a conventional example.

FIG. 13 is a cross-sectional view for explaining a conventional example.

FIG. 14 is a cross-sectional view for explaining a conventional example.

FIG. 15 is a cross-sectional view for explaining a conventional example.

FIG. 16 is a cross-sectional view for explaining a conventional example.

FIG. 17 is a cross-sectional view for explaining a conventional example.

FIG. 18 is a cross-sectional view for explaining a conventional example.

FIG. 19 is a sectional view for explaining a conventional example.

FIG. 20 is a cross-sectional view for explaining a conventional example.

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Claims (11)

[Claims] 1. A step of forming a high-concentration region on a surface of a semiconductor substrate below a predetermined pad region before a step of depositing a gate metal layer for forming a gate electrode; and a step of depositing the gate metal layer on the high-concentration region. Forming a first pad electrode, depositing a pad metal layer on the first pad electrode to form a second pad electrode, and crimping a bonding wire on the second pad electrode. A method for manufacturing a compound semiconductor device, comprising: 2. A step of forming a high-concentration region on a surface of a semiconductor substrate below a predetermined pad region and a predetermined wiring layer before a step of depositing a gate metal layer for forming a gate electrode, and on the high-concentration region. Depositing the gate metal layer to form a first pad electrode and a wiring layer, depositing a pad metal layer on the first pad electrode to form a second pad electrode, and the second pad electrode And a step of crimping a bonding wire thereon. 3. A step of forming a channel layer on the surface of a substrate, a step of forming a source and drain region in contact with the channel layer, and at the same time a high concentration region under a predetermined pad region, and the source and drain. Depositing an ohmic metal layer as a first-layer electrode on the region to form first source and first drain electrodes, and a gate metal as a second-layer electrode on the channel layer and the high-concentration region. Depositing a layer on the gate electrode and the first
Forming a pad electrode, and depositing a pad metal layer as a third layer electrode on the first source and first drain electrode and the first pad electrode to form a second source and second drain electrode and a second pad A method of manufacturing a compound semiconductor device, comprising: a step of forming an electrode; and a step of crimping a bonding wire on the second pad electrode. 4. A step of forming a channel layer on the surface of a substrate, and a step of forming a source and drain region in contact with the channel layer and simultaneously forming a high-concentration region under a predetermined pad region and a predetermined wiring layer. And a step of depositing an ohmic metal layer as a first-layer electrode on the source and drain regions to form first source and first drain electrodes, and a second layer on the channel layer and the high-concentration region. Depositing a gate metal layer as an electrode of the gate electrode and the first electrode
Forming a pad electrode and a wiring layer, and depositing a pad metal layer as a third electrode on the first source and first drain electrode and the first pad electrode, and forming a second source and second drain electrode And a step of forming a second pad electrode, and a step of press-bonding a bonding wire on the second pad electrode. 5. The method of manufacturing a compound semiconductor device according to claim 1, wherein the high-concentration region is provided so as to protrude from the pad electrode. 6. The method for manufacturing a compound semiconductor device according to claim 2, wherein the high-concentration region is provided so as to protrude from the pad electrode and the wiring layer. 7. The compound semiconductor device according to claim 1, wherein the high-concentration region is provided below the peripheral edge of the pad electrode so that a part of the high-concentration region extends beyond the pad electrode. Method. 8. The high-concentration region is provided under the pad electrode peripheral end portion and the wiring layer peripheral end portion, and a part thereof is provided so as to protrude from the pad electrode and the wiring layer. The method for manufacturing the compound semiconductor device according to claim 4. 9. The method according to claim 1, wherein the gate metal layer comprises a step of depositing a metal multi-layer film having a lowermost layer of Pt and then performing a heat treatment to fill a part of the gate electrode in the surface of the substrate. 5. The method for manufacturing a compound semiconductor device according to claim 4. 10. The method of manufacturing a compound semiconductor device according to claim 1, wherein the high concentration region is provided by ion implantation. 11. The method of manufacturing a compound semiconductor device according to claim 3, wherein the channel region is provided by ion implantation.