JP2002231732A - Method for fabricating compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a compound semiconductor device employing such a wiring structure as a wiring layer is provided directly on a substrate that separation of 20 μm or more is required for ensuring isolation because a depletion layer spreads from a neighboring pad, or the like. SOLUTION: A wiring structure for suppressing spread of a depletion layer is realized without increasing the number of fabrication steps of a method for fabricating a compound semiconductor device, by laying a pad oxide film 62 beneath a wiring layer 70 in the process for depositing an oxide film 61 on the surface of a source region 56 and a drain region 57 and on a predetermined wiring region 59 while leaving a resist layer 58 on a predetermined gate electrode 69.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for manufacturing a compound semiconductor device using a GaAs substrate.

[0002]

2. Description of the Related Art In mobile communication devices such as cellular phones, G
In many cases, microwaves in the Hz band are used, and switch elements for switching these high-frequency signals are often used in antenna switching circuits and transmission / reception switching circuits (for example, Japanese Patent Application Laid-Open No. Hei 9-181624). issue). As the element, a high-frequency field-effect transistor (hereinafter, FE) using gallium arsenide (GaAs) is used.
In many cases, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated has been developed.

FIG. 9A is a sectional view of a GaAs FET. An n-type impurity is doped into the surface portion of the non-doped GaAs substrate 31 to form an n-type channel region 32, and a gate electrode 33 in Schottky contact is arranged on the surface of the channel region 32. G
The source / drain electrodes 34 and 35 that are in ohmic contact with the aAs surface are arranged. In this transistor, a depletion layer is formed in the channel region 32 immediately below by the potential of the gate electrode 33, and thus a channel current between the source electrode 34 and the drain electrode 35 is controlled.

FIG. 9 (B) shows a basic circuit diagram of a compound semiconductor switch circuit device called a SPDT (Single Pole Double Throw) using a GaAs FET.

The sources (or drains) of the first and second FETs 1 and 2 are connected to a common input terminal IN, and each F
The gates of ET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2,
The drain (or source) of each FET is the first and second
Are connected to the output terminals OUT1 and OUT2. The signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which the H-level signal is applied turns ON, and the signal applied to the input terminal IN The signal is transmitted to one of the output terminals. The resistances R1 and R2 are connected to a control terminal Ctl which is AC grounded.
-1 and Ctl-2 are arranged for the purpose of preventing a high-frequency signal from leaking through the gate electrode with respect to the DC potential.

The compound semiconductor switch circuit device F
FIGS. 10 to 17 show a method of manufacturing the ET and the wiring layer.

In FIG. 10, a channel layer 2 is formed on the surface of a substrate 1.

That is, the entire surface of the substrate 1 is covered with a silicon nitride film 3 for through ion implantation having a thickness of about 100 °. Next, the surface of the substrate 1 is covered with a resist layer 4, and the resist layer 4 on the intended channel layer 2 is selectively removed by photoetching. After that, using the resist layer 4 as a mask, ion implantation of an impurity for giving a p ⁻ type and ion implantation of an impurity for giving an n type are performed in order to select an operation layer into a predetermined channel layer 2.

As a result, a p ^- type region 5 is formed on the non-doped substrate 1, and an n-type channel layer 2 is formed thereon.

In FIG. 11, a source region 6 and a drain region 7 are formed on the surface of a substrate 1 adjacent to both ends of a channel layer 2.

The resist layer 4 used in the previous step is removed, a new resist layer 8 is applied, and the resist layer 8 on the intended source region 6 and drain region 7 is selectively removed by photoetching. Subsequently, using the resist layer 8 as a mask, the intended source region 6 and drain region 7 are ion-implanted with an impurity for imparting n-type, thereby forming an n ⁺ -type source region 6 and drain region 7.

In FIG. 12, a resist layer 8 is left on a predetermined gate electrode 16 and a source region 6 and a drain region 7 are left.
An oxide film 9 is attached thereon.

Here, the resist layer 8 is thinned by O ² plasma to expose the silicon nitride film 3 on the surface of the source region 6 and the drain region 7 and on the channel layer 2 on the side of the source region 6 and the drain region 7. Silicon nitride film 3
To expose. Then, an ECR is formed on the entire surface of the silicon oxide film 9.
Attaches with equipment. Thereafter, the resist layer 8 is removed, and the oxide film 9 is left on the source region 6 and the drain region 7 and a part of the channel layer 2 by lift-off. Here, a predetermined gate electrode 16 is formed in a portion where the resist layer 8 exists on the channel layer 2.

In FIG. 13, a first source electrode 11 and a first drain electrode 12 are formed by attaching a first ohmic metal layer 10 to the source region 6 and the drain region 7.

A resist layer 13 is applied to the entire surface of the substrate 1, and the portions where the first source electrode 11 and the first drain electrode 12 are to be formed are selectively removed by photoetching. The silicon nitride film 3 and the oxide film 9 on the planned first source electrode 11 and first drain electrode 12 are removed by O ² plasma to form a contact hole, and a first ohmic metal layer 10 is formed on the entire surface. AnGe / Ni /
Three layers of Au are sequentially vacuum deposited and laminated. Thereafter, the resist layer 13 is removed, and the source region 6 is lifted off.
And the first source electrode 11 and the first drain electrode 12 that are in contact with each other on the drain region are left.

In FIG. 14, the intended gate electrode 16 and the intended wiring region 15 are exposed, and the other parts are covered with a resist layer 14.

A resist layer 14 is applied to the entire surface of the substrate 1, and the intended gate electrode 16 and the silicon nitride film 3 on the intended wiring region 15 are exposed by photoetching. Thereafter, the silicon nitride film 3 is dry-etched using the resist layer 14 as a mask to expose the planned gate electrode 16 and the channel layer 2 and the substrate 1 in the planned wiring region 15.

In FIG. 15, a second-layer gate metal layer 18 is attached to the channel layer 2 and the predetermined pad region 15 to form a gate electrode 16 and a wiring layer 17.

On the entire surface, three layers of Ti / Pt / Au to be the second-layer gate metal layer 18 are sequentially vacuum-deposited and laminated.
Since the resist layer 14 is used as a mask as it is, the gate electrode 16 and the wiring layer 17 that are in contact with the channel layer 2 and the substrate 1 are formed. Since the other part of the gate metal layer 18 is adhered on the resist layer 14, the resist layer 14 is removed to leave only the gate electrode 16 and the wiring layer 17 by lift-off, and the other parts are removed. Although the wiring layer 17 is in contact with the substrate 1, the substrate 1 is electrically insulated from other circuit elements including FETs and wiring because the substrate 1 is semi-insulating.

In FIG. 16, a contact hole is formed in the protective film 19 on the first source electrode 11 and the first drain electrode 12.

After forming the gate electrode 16 and the wiring layer 17, the surface of the substrate 1 is covered with a protective film 19 made of a silicon nitride film.
Covered. A resist layer 20 is applied on the protective film 19, and the protective film 19 on the first source electrode 11 and the first drain electrode 12 is selectively dry-etched by photoetching. After that, the resist layer 20 is removed.

In FIG. 17, a third pad metal layer 22 is deposited on the first source electrode 11 and the first drain electrode 12 to form a second source electrode 23 and a second drain electrode 2.
4 is formed.

A new resist layer 21 is applied to the entire surface of the substrate 1 and the first source electrode 11 is slightly larger than the contact hole.
Then, the first drain electrode 12 is exposed, and the other is covered with a resist layer 21. Subsequently, three layers of Ti / Pt / Au to be the third pad metal layer 22 are sequentially vacuum-deposited and laminated on the entire surface. Since the resist layer 21 is used as a mask as it is, the second source electrode 23 and the second source electrode 23 which contact the first source electrode 11 and the first drain electrode 12 are formed.
A drain electrode 24 is formed. Since the other portion of the pad metal layer 22 is attached on the resist layer 21, the resist layer 21 is removed and lift-off is performed to remove the second source electrode 23.
In addition, only the second drain electrode 24 is left, and the others are removed.

[0024]

In the conventional compound semiconductor device, the wiring layer 17 is formed directly on the substrate 1. However, if the wiring layer 17 is provided directly on the substrate 1, a 20 μm
Is required, which has the disadvantage of increasing the chip size.

[0025]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various circumstances, and has a wiring for securing isolation between a pad and a wiring layer by laying an oxide film under the wiring layer. A feature is to provide a method for manufacturing a compound semiconductor device that realizes a structure without increasing the number of steps.

That is, a step of forming a channel layer on the surface of the substrate, a step of forming source and drain regions in contact with the channel layer, and a step of leaving a resist layer on a predetermined gate electrode to form a surface of the source and drain regions. Depositing a pad oxide film on a predetermined wiring region, depositing a first ohmic metal layer on the source and drain regions to form first source and drain electrodes, and forming the channel layer Forming a gate electrode and a wiring layer by attaching a second layer of a gate metal layer on the pad oxide film and the substrate; and forming a gate electrode and a wiring layer on the first source and first drain electrodes and the first pad electrode. Attaching a third pad metal layer to form second source and second drain electrodes.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The present invention relates to the substrate 5
Forming a channel layer 52 on one surface, and forming source and drain regions 56 and 57 in contact with the channel layer 52.
Forming a resist layer, leaving a resist layer on the intended gate electrode 69, and attaching a pad oxide film 62 on the surface of the source and drain regions 56 and 57 and on the intended wiring region 59; Attaching a first ohmic metal layer 64 to 56, 57 to form first source and first drain electrodes 65, 66;
Depositing a second-layer gate metal layer 68 on the channel layer 52 and the pad oxide film 62 to form a gate electrode 69 and a wiring layer 70; and forming the first source and first drain electrodes 65 and 66. Forming a second source and second drain electrode 75 and 76 by attaching a third pad metal layer 74 thereon.

In the first step of the present invention, as shown in FIG.
The object is to form a channel layer 52 on the surface of the substrate 51.

That is, the entire surface of a compound semiconductor substrate 51 made of GaAs or the like is covered with a through ion implantation silicon nitride film 53 having a thickness of about 100 to 200 degrees. Next, the surface of the substrate 51 is covered with a resist layer 54, and the resist layer 5
4 is selectively removed. Thereafter, using this resist layer 54 as a mask, ion implantation of an impurity (24Mg ⁺ ) for giving a p-type and ion implantation of an impurity (29Si ⁺ ) for giving an n-type are performed to select an operation layer into a predetermined channel layer 52. .

As a result, the non-doped substrate 51 has p ⁻
A mold region 55 and an n-type channel layer 52 are formed thereon.

In the second step of the present invention, as shown in FIG.
The purpose is to form a source region 56 and a drain region 57 in contact with the channel layer 52.

The resist layer 54 used in the previous step is removed,
A new resist layer 58 is applied and a predetermined source region 56 is formed.
And the resist layer 58 on the drain region 57 is selectively removed by photoetching. Subsequently, using the resist layer 58 as a mask, ion implantation of an impurity (29Si ⁺ ) for imparting n-type to the intended source region 56 and drain region 57 is performed to form an n ⁺ -type source region 56 and a drain region 57.

[0033] The resist layer 58 of the portion adhering the pad oxide film 62 will in this step also removed simultaneously, n ⁺ -type source region 56 and with the drain region 57 of n ⁺ -type high-concentration diffusion layer 81 Is formed.

In the third step of the present invention, as shown in FIG.
An oxide film 61 is to be attached to the surface of the source region 56 and the drain region 57 and the peripheral end of the intended wiring region 59 while leaving the resist layer 58 on the intended gate electrode 69.

In this step, the resist layer 58 is thinned by O ² plasma to form a silicon nitride film 53 on the peripheral end surfaces of the source region 56, the drain region 57 and the wiring region 59.
And the silicon nitride film 53 on the channel layer 52 on the side of the source region 56 and the drain region 57 is also exposed.
Then, a silicon oxide film 61 is attached to the entire surface to a thickness of about 3000 ° by an ECR device. Thereafter, the resist layer 58 is removed, and the source region 56, the drain region 57, the peripheral end portions of the wiring region 59 and a part of the channel layer 5 are lifted off.
An oxide film 61 is left on 2. Here, a predetermined gate electrode 69 is formed on a portion of the channel layer 52 where the resist layer 58 exists.
Is formed.

This step is a characteristic step of the present invention.
A silicon oxide film 61 for forming the gate electrode 69 in a self-aligned manner is simultaneously attached on the wiring region 59 to form a pad oxide film 62. This silicon oxide film 61 is deposited in a reaction chamber of an ECR apparatus in a silane (Si) atmosphere in an N2 atmosphere.
Silicon oxide (SiO 2) formed by a plasma reaction from H ₄ ) and ammonia gas (NH ₃ ) is attached to the substrate 51 at room temperature in a bell jar. Therefore, there is an advantage that it can be attached to the substrate 51 without applying thermal stress, and the occurrence of cracks due to the difference in the coefficient of thermal expansion between the substrate 51 and the silicon nitride film 53 can be prevented.

In the fourth step of the present invention, as shown in FIG.
A first ohmic metal layer 64 is deposited on the source region 56 and the drain region 57 to form a first source electrode 65.
And forming the first drain electrode 66.

A resist layer 63 is applied to the entire surface of the substrate 51,
The portions where the first source electrode 65 and the first drain electrode 66 are to be formed are selectively removed by photoetching. The silicon nitride film 53 and the oxide film 61 on the planned first source electrode 65 and first drain electrode 66 are
^{(2) A} contact hole is formed by removing with a plasma, and AnGe / N to be the first ohmic metal layer 64 is formed on the entire surface.
Three layers of i / Au are sequentially vacuum deposited and laminated. afterwards,
The resist layer 63 is removed, and the first contact is formed on the source region 56 and the drain region 57 by lift-off.
The source electrode 65 and the first drain electrode 66 are left.

In the fifth step of the present invention, as shown in FIGS. 5 and 6, the channel layer 52 and the pad region 5 are formed.
9 is to form a gate electrode 69 and a first pad electrode 70 by depositing a second-layer gate metal layer 68.

In FIG. 5, the pad oxide film 62 and the substrate 5 at a portion to be the gate electrode 69 and the wiring region 59 are formed.
1 is exposed, and the other is covered with a resist layer 67. That is, a resist layer 67 is applied to the entire surface of the substrate 51, and the pad oxide film 62 and the substrate 51 at the portion to be the gate electrode 69 and the wiring region 59 are exposed by photoetching. Thereafter, the silicon nitride film 53 is dry-etched using the resist layer 67 as a mask to expose the channel layer 52 at the intended gate electrode 69 and the pad oxide film 62 and the substrate 51 at the portion to be the wiring region 59.

In FIG. 6, the second portion is formed on the pad oxide film 62 and the substrate 51 at portions which become the channel layer 52 and the wiring region 59.
A gate electrode layer 69 and a wiring layer 70 are formed by attaching a gate metal layer 68 as a layer.

That is, three layers of Ti / Pt / Au to be the second-layer gate metal layer 68 are sequentially vacuum-deposited and laminated on the entire surface of the substrate 51. Since the resist layer 67 is used as it is as a mask, the channel layer 52 and the wiring region 5
A gate electrode 69 and a wiring layer 70 are formed on the pad oxide film 62 and the substrate 51 in the portion to be 9. Since the other part of the gate metal layer 68 is deposited on the resist layer 67,
The resist layer 67 is removed, and only the gate electrode 69 and the wiring layer 70 are left by lift-off, and the others are removed.

In the sixth step of the present invention, a third pad metal layer is deposited on the first source electrode 65 and the first drain electrode 66 as shown in FIGS. And forming a second drain electrode.

In FIG. 7, the first source electrode 65 and the first
A contact hole is formed in the protective film 72 on the drain electrode 66.

After forming the gate electrode 69 and the wiring layer 70, the surface of the substrate 51 is covered with a protective film 7 made of a silicon nitride film.
2 coated. A resist layer 71 is applied on the protective film 72, and the protective film 72 on the first source electrode 65 and the first drain electrode 66 is selectively dry-etched by photoetching. After that, the resist layer 71 is removed.

In FIG. 8, the first source electrode 65 and the first
A third pad metal layer 74 is deposited on the drain electrode 66 to form a second source electrode 75 and a second drain electrode 76.
To form

A new resist layer 73 is applied to the entire surface of the substrate 51, and the first source electrode 6 is slightly larger than the contact hole.
5 and the first drain electrode 66 are exposed, and the other is covered with a resist layer 73. Subsequently, three layers of Ti / Pt / Au to be the third pad metal layer 74 are sequentially vacuum-deposited and laminated on the entire surface. Since the resist layer 73 is used as it is as a mask, a second source electrode 75 and a second drain electrode 76 which are in contact with the first source electrode 65 and the first drain electrode 66, and a second pad electrode 77 are formed. Since the other portion of the pad metal layer 74 is attached on the resist layer 73, the resist layer 73 is removed, and the second source electrode 75 and the second drain electrode 76 are lifted off.
Only the others are removed.

[0048]

As described in detail above, according to the present invention, the following effects can be obtained.

First, the pad oxide film 62 is formed according to the third embodiment of the present invention.
Since it is formed using the oxide film 61 adhered in the step, there is an advantage that it can be realized without increasing the number of steps.

Secondly, by selectively laying the pad oxide film 62 under the wiring layer 70, the pad oxide film 62 having a thickness of 20 μm required for the design for ensuring the isolation between the pad and the wiring layer is secured.
Has the advantage that the chip separation size can be reduced to about 5 μm and the chip size can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

FIG. 7 is a cross-sectional view for explaining the present invention.

FIG. 8 is a cross-sectional view for explaining the present invention.

9A is a cross-sectional view for explaining a conventional example, and FIG.
It is a circuit diagram.

FIG. 10 is a sectional view for explaining a conventional example.

FIG. 11 is a cross-sectional view for explaining a conventional example.

FIG. 12 is a cross-sectional view for explaining a conventional example.

FIG. 13 is a sectional view for explaining a conventional example.

FIG. 14 is a cross-sectional view for explaining a conventional example.

FIG. 15 is a cross-sectional view for explaining a conventional example.

FIG. 16 is a cross-sectional view for explaining a conventional example.

FIG. 17 is a cross-sectional view for explaining a conventional example.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tetsuro Asano 2-5-1-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. 4M104 AA05 BB11 BB15 CC01 CC05 DD02 DD08 DD16 DD17 DD34 DD68 EE05 EE14 EE17 FF13 FF17 FF18 FF22 GG12 HH20 5F102 FA00 GA01 GA17 GB01 GC01 GD01 GJ05 GS02 GT01 GT03 HA06 HA14 HA20 HB02 HB03 HB07 HC00 HC07 HC19

Claims (4)

[Claims] A step of depositing a pad oxide film under a wiring layer adjacent to a predetermined pad region before depositing a gate metal layer forming a gate electrode; and forming the gate metal layer on the pad oxide film. Forming a wiring layer by adhering a semiconductor device. A step of forming a channel layer on the surface of the substrate; a step of forming source and drain regions in contact with the channel layer; and a step of leaving a resist layer on a predetermined gate electrode to form a surface of the source and drain regions. Depositing a pad oxide film on a predetermined wiring region; depositing a first ohmic metal layer on the source and drain regions to form first source and first drain electrodes; Depositing a second gate metal layer on the pad oxide film and the substrate to form a gate electrode and a wiring layer; and forming a gate electrode and a wiring layer on the first source and drain electrodes and the first pad electrode. Attaching a third pad metal layer to form second source and second drain electrodes. . 3. The method for manufacturing a compound semiconductor device according to claim 1, wherein a silicon oxide film is used as said pad oxide film. 4. The method for manufacturing a compound semiconductor device according to claim 3, wherein the silicon oxide film is generated by plasma using an ECR device and is deposited at room temperature.