TW474018B - Semiconductor device for preventing process-induced charging damages - Google Patents

Abstract

The present invention discloses a semiconductor device for preventing process-induced charging damages. The semiconductor device comprises a semiconductor layer, at least one transistor, at least one parasitic capacitor, a first conductor and a second conductor. The transistor comprises at least a source, a drain, a channel, a gate oxide and a gate, and the parasitic capacitor comprises a conductive layer, a dummy conductive layer including the dummy pattern, a dielectric layer between the conductor layer and the dummy conductive layer, a first conductor connecting the gate of the transistor with the conductive layer, and a second conductor connecting the dummy conductive layer and the semiconductor layer. Further, the dummy conductive layer is also a floating layer which is floating on the semiconductor layer. At this time, the dielectric layer between the dummy conductive layer and the semiconductor layer replaces the second conductor.

Description

474018 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to the technology and engineering of semiconductor devices, and in particular to a technology related to protecting semiconductor devices from damage caused by accumulated charges caused by manufacturing processes. 5-2 Background of the Invention: The Antenna Effect or Floating Gate Effect is a phenomenon in which induced voltage is accumulated on a conducting wire during the process. This effect is particularly common in plasma-based processes, such as etching, deposition, and ion implantation, and can lead to damage to the gate oxide layer of components in the process. The charge accumulation and subsequent gate oxide damage caused by the manufacturing process cause the yield and reliability of sub-micron devices to be significantly reduced. The problem occurred during multiple steps in the process, but after the definition of the deposited conductor material (

Dei ine) The stage of wires, especially the definition of long wires, becomes more serious. When the device size is further reduced, the gate oxide layer is thinner to make it more vulnerable to damage, even if the operating voltage is reduced. The accumulation of electric charge on the wires in the process and the phenomenon of voltage rise cause voltage overstress and electric charge trapping

474018 V. Description of the Invention (2) (Tr app i ng) Gate oxide layer and breakdown (Br eakdown). Earlier, before that, in the integrated circuit manufacturing process, a simple η + / ρ or ρ + / η diode (Junc t i 〇 n D i 〇 d e) was used to protect the gate oxide layer from being damaged by the antenna effect. When the device size is further reduced, the gate oxide layer is very thin. At this time, the gate oxide layer is often damaged before the diode collapses. Therefore, the above-mentioned method of protecting the gate oxide layer from being damaged by the antenna effect with a diode will fail when the gate oxide layer is very thin, such as less than 100 angstroms. It is therefore necessary to provide another protection element that can protect the gate oxide ' even when the gate oxide is very thin, and can come in handy when the element size is further reduced.

The first diagram A depicts a conventional protection element 10, which is used to resolve the antenna effect caused by electric charges, while the first diagram B shows its equivalent circuit. The components in the figure can be manufactured by a variety of well-known process technologies, and specific process methods will not be described below. The protection element 10 includes a substrate 12 which is a semiconductor material, such as a silicon substrate implanted with p-type impurities. The semiconductor substrate 12 may also be other various semiconductor materials, such as gallium arsenide (GaAs), so that the principles of the present invention can still be implemented. Shown in the figure is a metal oxide semiconductor field effect transistor (M 0 S F E T) 1 4 and a protective device (C 0 m ρ ο n e n t

) 1 6 'This component is a η + / ρ or ρ + / η diode. The δ 蒦 element 10 includes a shallow trench isolation (Sh a 1 1 o w T rn c h Isolation) region 18a-18d, which can be formed by a conventional process. Between the shallow trench isolation regions 8a and 18b are source and drain electrodes 26a, 26b formed in a conventional manner, and a gate oxide layer 22 having a thickness of 4-20 nm. Polycrystalline

474018 V. Description of the invention (3) A silicon layer 24 is formed on the gate oxide layer 22 and implanted with impurities such as phosphorus ions. The dielectric layer 32 covers the shallow trench isolation regions 18a-18d of the polycrystalline silicon layer 24, and forms a contact window therein to form a channel extending from the upper surface of the dielectric layer 32 to the upper surface of the polycrystalline layer 24 and the channel. Extending from the upper surface of the dielectric layer 32 to a Moat region 36. The contact window is filled with a suitable metal conductor, such as an aluminum alloy or a copper alloy, to connect the circuit protection element 10 to the two non-adjacent layers (Leve 1), the diode 16 to the moat area 3, 6 N + impurities are usually implanted to form n + / p diodes. The diode 16 is connected to the gate oxide layer 2 2 by a metal wire 34, so that the diode 16 can preferentially leak the accumulated current of the gate oxide layer 2 2, thereby protecting the gate oxide layer 2 2 . However, in this way, each transistor 14 must be protected by a diode 16. The method of protecting the components described above is rather wasteful of the wafer area because these diodes take up a lot of area. For example, in some circuit designs, these diodes can take up 30% to 40% of the chip area. In addition, the wires required to connect these diodes also take up some area. Therefore, this traditional method wastes the area of the wafer, increases the cost and sacrifices the component density, and these diodes also cause problems of unnecessary leakage current or reverse bias. In view of this, there is an urgent need for a component that can protect the gate of the component and save chip area and cost.

474018 V. Description of the invention (4) 5-3 Purpose and summary of the invention: An object of the present invention is to provide a semiconductor device that prevents damage from accumulated electric charges caused by a manufacturing process. The parasitic capacitor is used as an energy pool to share the energy. Charge accumulation on the protection element. i Another object of the present invention is to provide a semiconductor element that prevents damage to the accumulated charge caused by the manufacturing process, and prevents the gate oxide layer of the protected element from accumulating an amount of charge, by directing most of the accumulated charge to a parasitic capacitor. Yet another object of the present invention is to provide a semiconductor device that prevents damage from accumulated charge caused by a manufacturing process, and at the same time saves chip area compared to conventional methods by connecting at least one protected component to a parasitic capacitor. Another object of the present invention is to offset the potential dish-shaped (D i s h i n g) effect of the chemical mechanical polishing (CMP), and a dummy conductor layer forming a dummy pattern is used as an electrode of the parasitic capacitor. . One package, few pieces, the layer element to the pole body, the body gate conductor crystal, a pseudo-semi-crystalline electricity and the kind of electricity this layer case. An integrated oxygen false profit and low-conductor pole is used to make the structure of the two gates, the first layer, the first layer, the first layer, the first layer, and the conductor of the body and the channel layer. The package includes no package, a device, a device, and a body electrode that can be used as a conductive power source for half a life.

474018 V. Description of the invention (5) The semi-conductor crystal conductive semi-connected with the first layer, the bulk conductive pseudo-intermediate connection and the monolithic body conduction-a pseudo-and-layered body conduction and the dielectric A gate guide is semi-floating on the dielectric, and a layer of the floating body is semi-semi-conductable with a layer of the body. At this time ο this conductor. The second layer of the second guide is detailed and clearly explained. It must be explained here that the process steps and structures described below do not include the complete process of integrated circuits. The present invention can be implemented by various integrated circuit process technologies, and only the process technologies required to understand the present invention are mentioned here. As will be described in detail below, the present invention is related to proposing a parasitic capacitor to replace the traditional diode to protect the gate oxide layer of the component from accumulated charge damage. For any capacitor ε A / t, where A = area of the capacitor C electrode, ε = capacitance coefficient of the dielectric material (Pe rm i 11 i v i t y), 1: = thickness of the dielectric material. With a larger capacitor electrode area, the parasitic capacitor of the present invention can share more charges than the protected element, thus preventing the gate oxide layer of the protected element from excessively accumulating charge and collapse during the process stage. In addition, the parasitic capacitor's metal pattern forming the dummy pattern can offset the potential D i s h i n g effect of the chemical mechanical polishing (CMP) process. Also, since the fake pattern is located

474018 V. Description of the invention (6) There is no plutonium in the integrated circuit. Therefore, the use of parasitic capacitors can not only improve the utilization efficiency of the chip area, but also reduce the dishing effect of the chemical process. Another aspect of the present invention is that because the capacitance of the device of the present invention is large ... parasitic capacitors can protect at least one component, so a circuit layout engineer can save a lot of chip area. … Figure A: Draw a protective element 40 to prevent damage from the accumulated charge in the 5-way bow. Figure 1B shows the equivalent protection circuit. The elements in the figure can be manufactured by a variety of known integrated circuit process technologies. Specific process methods will not be specifically described in the following discussion. The protection element 40 includes a substrate 52 '. The substrate may be made of a semiconductor material, such as a fabric? Shi Xi of Shelf Ion. The semiconductor substrate 52 may also be composed of other semiconductor materials such as gallium halide, so that the principles of the present invention can still be implemented. The structure shown in the figure '-a metal oxide semiconductor field effect transistor can also be considered-a metal oxide semiconductor capacitor is represented by the representative symbol 50. A trap tank & μ / ^ 丨 does not add a component (Component), that is, a parasitic capacitor, is represented by a representative symbol 60. The source and drain electrodes 64a and 64b are formed in the semiconductor substrate 52 in a conventional manner, and a channel 56 is formed between the source electrodes 64a and 64b, and the gate oxide layer 54 is formed on the channel 56. 'The intermediate electrode oxide layer 54 is formed by a thermal oxidation method and has a thickness of about 4 to about 20 nm. A gate 58 may be a polycrystalline silicon layer, and may be formed on the gate oxide layer 54 'in a conventional manner and implanted with dish ions to increase its conductivity. The gates 58 are connected to the bulk layers 7 4 b and 76 through a wire 6 8 a, and the two conductor layers 74b and 76 are located at different levels, respectively. These two conductor layers 74b and 76 will inevitably become antennas during the process.

Page 10 474018 V. Description of the invention (7), that is, the charge accumulation place caused by the manufacturing process. The parasitic capacitor 60 used to protect the metal oxide semiconductor field effect transistor 50 includes at least a conductor layer 7 4 a as an electrode and a dummy conductor layer 7 2 as another electrode and forms a dummy pattern. The conductor layer 7 4 a is connected to the gate electrode 5 8 through the wire 6 8 a, so the parasitic capacitor 60 can share the accumulated charge of the metal oxide semiconductor field effect transistor 50 whenever an antenna effect occurs. The conductor layer 7 4 a and the dummy conductor layer 7 2 may be copper, copper, and polycrystalline stone, and they may be different materials. In addition, the conductor layer 74a and the conductor layer 74b are formed together and are both part of the integrated circuit, but the dummy conductor layer 72 is not part of the integrated circuit. The dummy conductor layer 72 constituting the dummy pattern can be formed by a method of forming a conductive wire in a integrated circuit. In addition, it must be noted that the inter-metal dielectric layer (Inter-Metal Dielectric Layer) between the conductor layer 74a and the dummy conductor layer 72 is not shown. In addition, the parasitic capacitor 60 may also be a multilayer capacitor whose electrodes are polycrystalline silicon to metal, metal to metal, and polycrystalline silicon to polycrystalline silicon. At this time, the parasitic capacitor 60 can be regarded as an equivalent capacitor in which a plurality of capacitors are connected in series. In addition, in the integrated circuit, multiple parasitic capacitors 60 can also be connected to form multiple capacitors and equivalent capacitors connected in parallel. Referring to the second figure B, the metal oxide semiconductor field effect transistor 50 and the parasitic capacitor 60 can be Think of capacitors C 1 and C 2 in parallel, of which R 1 and R 2 are the equivalent resistance of wire 6 8a. Equivalent capacitance C, C = C! + C 25 where C i = ε Ai / ti ’C Corps ε Α2 / Ϊ2’

474018 V. Description of the invention (8) Area of A gate 588, area of A parasitic capacitor 60 electrode, ti = thickness of gate oxide layer 54, and average distance between 60 s parasitic capacitor electrode . If ti = taxi 2 and eight corpses 2Αι ’then 2 C !. If the accumulated charge is Q 'and the voltage is V, then Q = CV, and the charge accumulated in C must be 0.333Q, and the charge accumulated in C is 0.67Q. According to the above relationship, the parasitic capacitor 60 can be used to protect the metal oxide semiconductor field effect transistor 50 from the accumulated charge damage. In addition, due to the large capacitance value of the parasitic capacitor 60, a parasitic capacitor 60 can be connected in parallel with more than one metal oxide semiconductor field effect transistor 50, so that the circuit layout engineer can save a lot of chip area by this. The third diagram A depicts a protection element 4 0 ′ for preventing the accumulated charge from damaging, and the third diagram B shows an equivalent protection circuit thereof. A parasitic capacitor for protecting a metal oxide semiconductor field effect transistor 50 is represented by a symbol 70. The parasitic capacitor 70 includes at least a part of the conductor layer 7 4 a, the dummy conductor layer 72, and a semiconductor substrate 52 located below the dummy conductor layer 72. Different from the parasitic capacitor 60, the dummy conductor layer 72 of the parasitic capacitor 70 is floating (F1 〇ating), that is, the dummy conductor layer 72 and the semiconductor substrate 52 under the dummy conductor layer 72. This part constitutes another capacitor. The inner metal dielectric layer between the conductor layer 74a and the dummy conductor layer 72 and between the dummy conductor layer 72 and the semiconductor substrate 52 under the dummy conductor layer 72 is not shown. Also, as

Page 12 474018 V. Description of the invention (9) Same parasitic capacitor 60, parasitic capacitor 70 can also be a multilayer capacitor, and its electrodes are polycrystalline and metal-to-metal and polycrystalline and polycrystalline Xi. At this time, the parasitic capacitor 70 can be regarded as an equivalent capacitor in which a plurality of capacitors are connected in series. In addition, in the integrated circuit, a plurality of parasitic capacitors 70 may be connected to form an equivalent capacitor in parallel with a plurality of capacitors. Referring to FIG. 3B, the parasitic capacitor 70 can be regarded as an equivalent capacitor in which capacitors C and C 3 are connected in series and connected in parallel with the metal oxide semiconductor field effect transistor 50. The equivalent capacitance C, C = C! + (C 2C 3 / C 2+ C a) 5 Λ where C £ A 2/125 C ε A 3/135 A area of 7 4 a dead conductor layer, A dead leave The area of the conductor layer 72, the thickness of the gate oxide layer 54, and the average distance between the conductor layer 74a and the dummy conductor layer 72, and between the conductor layer 72 and the semiconductor substrate 52 The average distance. If t Yan 12 ′ t 13 and A 2 2 5 A 1 ′ A 3 A ′ B 1 C C 2 5 C at C 2 = C3. If the accumulated charge is Q and the voltage is V, then Q = CV, and the charge accumulated in Ci is 0.44Q, and the charge accumulated in C is 0.56Q. ® According to the above relationship, the parasitic capacitor 70 can be used to protect the metal oxide semiconductor field effect transistor 50 from the accumulated charge damage. In addition, since the capacitance value of the parasitic capacitor 70 is large, a parasitic capacitor 70 can be combined

Page 13 474018 V. Description of the invention (ίο) If more than one metal oxide semiconductor field effect transistor is connected, 50, so the circuit layout engineer can save a lot of chip area by this. The foregoing brief description of the invention and the following detailed description are examples only and are not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention.

Page 474018 Brief description of the diagram The first diagram A shows a cross-sectional view of a conventional protection element used to solve the antenna effect. The first diagram B shows the circuit of the traditional protection element in the first diagram A. The second diagram A shows Sectional view of the first protection element of the present invention; FIG. 2B shows a circuit showing the first protection element of the present invention; FIG. 3A shows a sectional view of the second protection element of the present invention; and third B The figure shows the circuit of the second protection element of the invention. Representative symbols of main parts: 1 0 protection element 12 substrate 1 4 metal oxide semiconductor field effect transistor 1 6 protection component 1 8 a to 1 8 d shallow trench isolation area 2 2 gate oxide layer 2 4 polycrystalline silicon layer 2 6 a source 2 6 b drain 3 2 dielectric layer

Page 15474018 Brief description of the drawing 3 4 Metal wires 3 6 Ditching area 4 0 Protective element 4 0 'Protect element 5 0 Metal oxide semiconductor field effect transistor 5 2 Substrate 5 4 Gate oxide layer 5 6 channel Zone 5 8 Gate 6 0 Parasitic capacitor 6 4 a Source 6 4 b Drain 6 8 a Wire 7 2 Fake conductor layer 7 4 a Conductor layer 74b Conductor layer 76 Conductor layer

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Claims (1)

474018 VI. The scope of the application for patents Leads to the damage charge accumulation of the lead of the element. · Cheng Han's package includes Fan Shaofang to \ Utul "Two types of element 1 element 1 inner layer guide should be included in the polar source 1. Including the body crystal, the conductivity of the bulk crystal is less than one to haihai = mouth = mouth connected to K K: the inner gate of the overlying gate and half of the gate should be covered with a layer, the inner oxygen layer polar body The gate is half, the pole is the drain, the drain is the same as the pole, the source package is as small as the device capacity, and the upper layer body is half of the positioner, and the capacity is reduced; the electrical layer is reduced to less oxygen to the gate body. The guide of the mediator and the pseudo layer The guide of the body and the guide prosthesis The figure is adjacent to the layer to form a layer, the body conductor falsely guides the one and the layer and the body; the guide half of the body and the guide This layer is connected to the body pole gate false Haihai = mouth = mouth successively connected body guide one or two second and fourth fanli special education " mouth shape 1 丨 η such as 2 is the body crystal electric components Elementary body The electric effect field body conduction semi-physical oxygen is a gold element element body conduction half of the item IX Fan Li specially asked the body crystal electric field treatment semi-physical oxygen half of the metal element Shen Shen 嫂 As a 3 for the body crystal, the A layer Please refer to the section IX of Fan Lizhuan for the part of the body guide. Please apply for copper as a 4 For the guide for the IX fanfare of the body for the part of the body guide, please apply for 5 Page 17 474018 VI. The scope of patent application is one layer. 6. If the semiconductor device according to item 1 of the patent application scope, wherein the conductor layer is a polycrystalline stone layer. 7. For the semiconductor device according to item 1 of the application, wherein the dummy conductor layer is a copper layer. 8. In the case of the semiconductor device according to item 1, the dummy conductor layer is a cover layer. 9. For the semiconductor device according to item 1 of the application, wherein the dummy conductor layer is a polycrystalline silicon layer. 1 0. A semiconductor element to prevent damage from accumulated charge, the semiconductor element includes at least: a semiconductor layer; at least a transistor, the transistor includes a source in the semiconductor layer, a drain in the semiconductor layer, A channel connects the source and the drain in the semiconductor layer, a gate oxide layer covers the channel and a gate covers the gate oxide layer; at least one capacitor is located above the semiconductor layer, and the capacitor includes at least one copper Layer, a dummy conductor layer forming a dummy pattern, and a dielectric layer interposed between the copper layer and the dummy conductor layer and next to the copper layer and the dummy conductor layer; Page 18 474018 6. Scope of patent application A first conductor layer connects the gate and the copper layer; and a second conductor layer connects the dummy conductor layer and the semiconductor layer. 1 1. The semiconductor device according to item 10 of the application, wherein the transistor is an n-type metal oxide semiconductor field effect transistor. Part of the body lead half of the guide ο guide 1X half of the seventh Γ-Τ Wuwei seven Fan Li specially invited to be one of the • 1 2 body oxygen gold type P body crystal * ^ g the effect field body crystal electric The body guide is supposed to be Fan Li, the IX body guide of the body. The special layer asks you to apply for you. It is the first half of the 3 1-I layer guide that should be included in the guide. Special layer Please apply for aluminum. If it is. Layer 4 1 Body 15 · If the semiconductor device in the scope of patent application No. 10, the dummy conductor layer is a polycrystalline silicon layer. 16. A semiconductor element that prevents damage from accumulated charge, the semiconductor element includes at least: a semiconductor layer; at least one transistor, the transistor includes a source originating in the semiconductor layer, and one electrode not in the semiconductor layer, A channel connects the source and the anode in the semiconductor layer, a gate oxide layer covers the channel, and a gate covers the channel. Page 19474018 VI. Patent application gate oxide layer; at least one capacitor is located above the semiconductor layer, the capacitor includes at least a part of the semiconductor layer, a dummy pattern is formed and is located on the part of the semiconductor layer An upper fake conductor layer, a conductor layer above the fake conductor layer, and two between the conductor layer and the fake conductor layer, and between the fake conductor layer and the semiconductor layer, and respectively next to the conductor layer A dielectric layer with the dummy conductor layer, the dummy conductor layer and the semiconductor layer; and a conductor connecting the gate and the conductor layer. 1 7. The semiconductor device according to item 16 of the application, wherein the transistor is an n-type metal oxide semiconductor field effect transistor. 1 8. The semiconductor device according to item 16 of the application, wherein the transistor is a p-type metal oxide semiconductor field effect transistor. 19. The semiconductor device according to item 16 of the patent application scope, wherein the conductor layer is a copper layer. 20. The semiconductor device according to item 16 of the patent application, wherein the conductor layer is a layer. 2 1. The semiconductor device according to item 16 of the application, wherein the conductor layer is a polycrystalline stone layer. Page 20 474018 6. Scope of patent application 2 2. For the semiconductor device with the scope of patent application No. 16 in which the dummy conductor layer is a copper layer. 2 3. The semiconductor device according to item 16 of the scope of patent application, wherein the dummy conductor layer is an intaglio layer. 24. The semiconductor device according to item 16 of the patent application, wherein the dummy conductor layer is a polycrystalline silicon layer.