TW561579B - Method for forming thickness of composite gate dielectric layer - Google Patents

Abstract

A method for forming the thickness of a composite gate dielectric layer comprises: providing a wafer having at least a first region and a second region thereon; forming a first silicon oxide layer on the first region and the second region; removing a first silicon oxide layer on the second region; implanting nitrogen-containing ions on the surface of the first silicon oxide layer for preventing the penetration of oxygen atoms; and forming a second silicon oxide layer on the second region.

Description

56l579 V. Description of the invention (1) ----- Field of the invention: The present invention relates to a gate dielectric layer of a semiconductor process, in particular to a method for manufacturing a composite gate dielectric layer thickness. BACKGROUND OF THE INVENTION ·· Heart of mind Recently, the semiconductor industry has developed very prosperously. In order to obtain high-energy integrated circuits and increase the mounting density of wafers, the size of semiconductor elements has been continuously reduced in the ultra-large integrated circuit (ULS I) technology. Integrated electrical package, forming millions of components in a specific area on a wafer and used to

< The electrical connection structure of these tl pieces, so as to be able to perform the specific functions required. Increasing the density of electronic components has suddenly become a trend. By reducing the size of the components, the integration density of semiconductor integrated circuits can be increased. (After reducing the size of electronic TL components, integrated circuits continue to appear in the manufacturing process = many new challenges. For example, the reduction in the size of dynamic random memory (DRAM) cells has resulted in a reduction in storage capacitance and caused The missing is. The metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the typical components. The above-mentioned π device has been widely used in semiconductor technology. However, with the trend of the integrated circuit, the MOSFET is being manufactured. It also encountered many problems, for example, typical problems such as the hot carrier effect have been overcome by the development of a slightly doped drain structure. In addition, the typical metal-oxygen half-field transistors have mostly replaced bipolars Application of transistor in high frequency, such as personal mobile phone or personal communication service wireless communication amplifier 561579 at GHz. 5. Description of the invention (2) (personal communication service wireless communication amplifier; PCS). The main reason is that MOSFETs have more bipolar components than Better linearity, that is, it has less non-linear transfer character than bipolar. The process of using a composite gate dielectric layer thickness in logic components for the operation of different components, so the above process is also very important. Under the trend of shrinking, it is necessary to use a high dielectric constant dielectric layer as the gate. The dielectric layer makes the process more complicated. United States Patent No. 6,110, 84 2 discloses a process for forming a composite gate oxide layer, and the invention name is n Method of forming multiple gate oxide thicknesses using high density plasma nitridation ". In this method, the emitter uses a high-density plasma to reduce the thickness of the oxide layer to make a composite gate dielectric layer. Another U.S. patent discloses a method for forming a composite gate dielectric layer. See U.S. Patent 6,093,65 On the 9th, the applicant is TeXas Instruments Incorporated, and the invention name is n Selective area halogen doping to achieve dual gate oxide thickness on a wafer ". The above-mentioned previous case used implanted dental elements such as fluorine or gas (halogen species such as fluorine or chlorine) after a specific area, and then perform the oxidation process so that Ions and undoped regions of simultaneously forming oxide layers of different thickness.

Page 556179 V. Description of the invention (3) Figures 1 to 3 show a traditional method for manufacturing the thickness of the composite gate dielectric layer. First, the regions 100, 2 0 on the wafer 2 are formed by an oxidation process. A thicker first oxide layer 4. Next, the first oxide layer 4 on the area 200 is removed, and then a second oxidation process is performed to control the oxidation time or other parameters to form a thinner second oxide layer 6. After the first oxide layer 4 is removed, the surface of the wafer composed of silicon will be exposed, so that a water-repellent silicon surface and a hydrophilic oxide will also coexist, so it is not easy to use hydrofluoric acid to clean the surface of the wafer, and It will cause the loss of the first oxide layer 4 and easily cause the leakage current. In addition, it is difficult to control the thickness of the oxide layer to be formed on the area 100 in the manufacturing process. Based on the trend of component shrinking, the process of composite gate dielectric layer thickness is becoming more and more important. Therefore, the present invention proposes a process of composite gate dielectric layer thickness with different solutions. Object and Summary of the Invention The object of the present invention is a method for forming a composite gate dielectric layer. Utilizing the characteristics of the nitride film layer, it is attached to the first silicon oxide layer on the first region to prevent the first silicon oxide layer from being oxidized in the subsequent oxidation process, providing easy control of the gate dielectric layer thickness and preventing the oxide layer. Ways to churn. The present invention mainly forms gate dielectric layers of different thicknesses in different regions in the same process, so as to be required for different operating conditions. Mentioned gate

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V. Description of the invention (4) The electric layer is also a composite layer structure. The composite gate dielectric dance method of the present invention includes providing a wafer including at least a first region and a first region, and then forming a first silicon oxide layer on the first region and a region. The first oxide stone located on the second region is removed, and then nitrogen-containing ions are implanted on the surface of the first silicon oxide layer, the layer, and the penetration of oxygen atoms. Finally, a second silicon oxide layer is formed on top = prevent. Another embodiment of suspending a region includes providing a wafer and a first region of the second region, a nitride layer, and a nitride layer. After removing the second deposited second nitrogen layer, the nitride can be put on to oxidize the surface of the second region. After the first oxidation, the silicon nitride layer on the second region is finally removed and then the leakage current layer is reduced in the second step and the second surface is formed by the first oxygen process, which can further form the silicon layer. The second oxidized stone layer is based on the area. Another silicon oxide layer is used to reduce the leakage. The upper layer is formed on the upper silicon nitride region. The upper layer is on the top and the first surface is used for the embodiment. . At least the first layer of the second silicon oxide described above replaces the first layer of the second silicon oxide in order to be above the second area and the above-mentioned oxygen-oxidized vaporization layer and area. After the layer, the second region field can be oxidized and the second region surface can be transported. The silicon nitride layer is described in detail in the invention. Selectively oxidize "m = square" as a gate dielectric layer of different thickness to provide no need?

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5. Description of the invention (5) The method of the invention will be described below. First, referring to FIG. 4, a semiconductor material is provided as a substrate or a wafer 12. For example, a single crystal silicon with a crystal orientation of <10 〇> can be used as the wafer of the embodiment of the present invention. The artisan knows that 'GaAs or Ge can also be used as the substrate or wafer. The wafer 12 is divided into at least a first region 100 and a second region 2000, and is used to fabricate different components thereon. Subsequently, isolation regions such as shallow trench isolation regions or field oxidation regions are first fabricated on the wafer 2 using known techniques. Next, the transistor fabrication is performed, which includes the steps of forming a gate dielectric layer on the μcircle 20. Based on the trend of integrated processes, gate dielectric layers of different thicknesses need to be fabricated simultaneously.

Embodiment 1: First, a thick oxide layer 14 is formed on different regions 100 and 2000 on the wafer 12. The silicon dioxide layer 14 is generally formed by a thermal oxidation process at a process temperature of approximately Between 70 0 and 1100 ° C, of course, general techniques such as air vapor deposition using TE 0 S as a reactant can also form a dioxide layer. After drying, a photoresist pattern is formed by a lithography process to expose the 200 in the second area, and then the silicon dioxide layer 14 formed thereon is removed to expose a round surface. Generally, a hydrofluoric acid solution or a Boe solution can be used to remove the silicon dioxide layer 14 as shown in FIG. 5. — The surface of the above results is nitrided. For example, using a remote control plasma (nitrogen ion implantation), the first oxide layer 1 on the third region 100 can be described. The surface, and the second zone

561579 V. Description of the invention (6) The surface of a circle. Referring to FIG. 6, the thermal oxidation process is used to grow the thin oxygen cutting material f. Based on the first oxide layer of the first region 1QG, the thin nitrogen-containing ion surface 16 ′ composition may be Si xOyNz, so it can prevent oxygen atoms from penetrating. This prevents the first silicon oxide layer 14 from growing again. The second oxide layer 18 can be formed on the second region 200, and the growth thickness of the second silicon oxide layer 18 can be controlled by the oxidation time. The above-mentioned nitrogen-containing surface formed on the first oxide layer 14 can prevent oxygen atoms from penetrating and thus can easily control the thickness of the oxide layer without causing the oxide layer on the first region 100 to be lost. Furthermore, this method can use hydrofluoric acid for surface cleaning, and the gate dielectric layer containing nitrogen doping has the characteristics of reducing leakage current prevention. Second Embodiment: Referring to FIG. 7, a first silicon oxide layer 20 is first formed on a first region 100 and a second region 200 on a wafer 12, and the first silicon oxide layer 20 is thermally oxidized. Law formation. Next, a silicon nitride layer 22 is deposited thereon. Generally, the nitride nitride layer 26 can be formed by using Low Pressure Chemical Vapor Deposition (LPCVD) or plasma enhanced chemical gas. Phase deposition (Plasma Enhance Chemical Vapor Deposition; PECVD) or high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition; HDPCVD). The reaction gas can be SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N20.

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After that, the silicon nitride layer 22 and the first emulsified silicon layer 20 formed on the second region 200 and the first emulsified silicon layer 20 are sequentially stripped. Nitriding power can be removed with hot phosphorous liquid. Oxidized stone material can be &amp;# β /

XU BeiJU uses lice acid solution or B solution to remove, as shown in Figure 8 :. Then, referring to FIG. 9, the second time is performed: The process' further forms the first emulsified stone layer 24 on the surface of the second region 20 (), and the first region has a plant nitrogen cut layer 22 as a barrier, so the oxygen atoms The thickness of the inability to penetrate the first-emulsified silicon layer 20 is not affected. Therefore, the thickness of the oxide layer can be easily controlled. This embodiment similarly has the first embodiment and the third embodiment. Referring to FIG. 10, this embodiment is derived from the silicon nitride layer 22 on the upper region 200 and the first example eliminates the first problem. After the hemp 9 ^ "and the siliconized layer 20, a first siliconized layer 28 can be deposited on the second surface 200 silicon layer 24, which can be further used to replace the first silicon layer. The reason why the chemical vapor deposition method is used = the second gasification layer 28 is formed on the first region 100. Sayue &quot; the second silicon nitride layer 28 is also in between, and the first region can be controlled individually The time layer of the film layer and the gate dielectric on the first area 2000 or the fourth embodiment are described in the fourth embodiment. Referring to FIG. The silicon nitride layer 22 and the silicon layer 20 can be oxidized 561579 on the surface of the second region 200 after the fifth layer 5. The invention is described in (8) The second silicon oxide layer 32 is fabricated on the surface of the second region 2000. Continued, Further depositing a second silicon nitride layer 34 on the surface of the second region 200 and on the first region 100 can further reduce the leakage current. Similarly, the first The silicon dinitride layer 34 is also deposited by chemical vapor deposition. Generally, the dielectric constant of silicon nitride is about 8 and the dielectric constant of silicon oxide is about 4. The composite gate dielectric layer using this method has Good anti-leakage characteristics. In summary, the present invention can provide a simplified process, better dielectric layer characteristics and other effects, can also prevent the loss of the oxide layer and solve the problem of hydrophilic and water repellent surface characteristics. The preferred embodiment is explained above, and those skilled in the art can make some modifications without departing from the spirit of the present invention. The scope of patent protection depends on the scope of the attached patent application and its equivalent fields. .

Page 11 561579 Brief description of the drawings The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figure 1 is a cross-sectional view of the first silicon oxide layer formed in the conventional technology. FIG. 2 is a cross-sectional view of a conventional technique in which a first silicon oxide layer formed on a second region is removed. FIG. 3 is a cross-sectional view of forming a second silicon oxide layer in the conventional technique. FIG. 4 is a cross-sectional view showing the formation of a first silicon oxide layer according to the present invention.

FIG. 5 is a cross-sectional view of a semiconductor wafer performing nitrogen ion implantation according to the present invention. FIG. 6 is a cross-sectional view of a semiconductor wafer in which a second silicon oxide layer is formed according to the present invention. FIG. 7 is a cross-sectional view of a semiconductor crystal forming a first silicon oxide and a silicon nitride according to the present invention. FIG. 8 is a cross-sectional view of a semiconductor wafer in which the first silicon oxide and silicon nitride formed on the second substrate are removed according to the present invention. FIG. 9 is a cross-sectional view of a semiconductor wafer forming a second silicon oxide layer according to the present invention. Fig. 10 is a sectional view of a third embodiment of the present invention. Fig. 11 is a sectional view of a fourth embodiment of the present invention.

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Claims (1)

561579 VI. Application for patent scope f, A method for forming a thickness of a composite gate dielectric layer, comprising: providing a wafer including at least a first region and a second region; forming a first silicon oxide layer on the first region And on the second region; removing the first silicon oxide layer on the second region; implanting nitrogen-containing ions on the surface of the first silicon oxide layer to prevent penetration of oxygen atoms; and forming a second region A silicon oxide layer is on the second region. 2. The method for forming the thickness of the composite gate dielectric layer according to item 1 of the application, wherein the first silicon oxide layer is formed by a thermal oxidation method. 3. The method for forming the thickness of the composite gate dielectric layer according to item 1 of the scope of patent application, wherein the second silicon oxide layer is formed by a thermal oxidation method. 4. The method for forming the thickness of the composite gate dielectric layer according to item 1 of the patent application range, wherein the nitrogen-containing ion implantation mentioned above uses a remotely controlled plasma to introduce nitrogen ion implantation. 5. The method for forming the thickness of the composite gate dielectric layer according to item 1 of the application, wherein the first silicon oxide layer is removed by using a hydrofluoric acid solution. 6. The method for forming the thickness of the composite gate dielectric layer according to item 1 of the application, wherein the first silicon oxide layer is removed by using a BOE solution. 561579 VI. Scope of patent application 7. —A method for forming the thickness of the composite gate dielectric layer, comprising: providing a wafer including at least a first region and a second region; forming a first silicon oxide layer on the first Forming a silicon nitride layer on the first silicon oxide layer; removing the first silicon oxide layer and the silicon nitride layer on the second area; and forming a second silicon oxide layer Above the second area. 8. The method for forming the thickness of the composite gate dielectric layer according to item 7 of the application, wherein the first silicon oxide layer is formed by a thermal oxidation method. 9. The method for forming the thickness of the composite gate dielectric layer according to item 7 of the application, wherein the second silicon oxide layer is formed by a thermal oxidation method. 10. The method for forming the thickness of the composite gate dielectric layer according to item 7 of the scope of the patent application, wherein the first silicon oxide layer is removed by using a hydrofluoric acid solution. 11. The method for forming the thickness of the composite dielectric layer according to item 7 of the patent application, wherein the first silicon oxide layer is removed by using a BOE solution. 12. The method for forming the thickness of the composite gate dielectric layer according to item 7 of the application, wherein the silicon nitride layer is removed by using a hot phosphoric acid solution. 561579 VI. Application Patent Scope 1 3. —A method for forming the thickness of the composite gate dielectric layer, including: providing a wafer including at least a first region and a second region; forming a first silicon oxide layer on the first A region and the second region; forming a first silicon nitride layer on the first silicon oxide layer; removing the first silicon oxide layer and the first silicon nitride layer on the second region; and forming The second silicon nitride layer is on the second region and is formed on the first silicon nitride layer on the first region. 14. The method for forming the thickness of the composite gate dielectric layer according to item 13 of the scope of the patent application, wherein the first silicon oxide layer is formed by a thermal oxidation method. 1 5. The method for forming the thickness of the composite gate dielectric layer according to item 13 of the scope of patent application, wherein the first silicon oxide layer is removed by using a hydrofluoric acid solution. 16. The method for forming the thickness of the composite gate dielectric layer according to item 13 of the patent application scope, wherein the first silicon oxide layer is removed by using a BOE solution. 1 7. The method for forming the thickness of the composite gate dielectric layer according to item 13 of the scope of patent application, wherein the first silicon nitride layer is removed by using a hot phosphoric acid solution. 18. If the thickness of the composite gate dielectric layer is formed as described in the scope of application for item 13 561579 VI. Patent application method, wherein the above-mentioned first silicon nitride layer is formed by a chemical vapor deposition method. 19. The method for forming the thickness of the composite gate dielectric layer according to item 13 of the scope of patent application, wherein the second silicon nitride layer is formed by a chemical vapor deposition method. 2 0. A method for forming a thickness of a composite gate dielectric layer, comprising: providing a wafer including at least a first region and a second region; forming a first silicon oxide layer on the first region and the second region Over the area; forming a first nitride layer on the first oxide layer; removing the first silicon oxide layer and the first silicon nitride layer on the second area; forming a second silicon oxide layer on Over the second region; forming a second silicon nitride layer on the second silicon oxide layer; and forming a second silicon nitride layer on the first region. 2 1. The method for forming the thickness of the composite gate dielectric layer according to item 20 of the patent application range, wherein the first silicon oxide layer is formed by a thermal oxidation method. 2 2. The method for forming the thickness of the composite gate dielectric layer according to item 20 of the patent application, wherein the second silicon oxide layer is formed by a thermal oxidation method. Page 16 561579 6. Scope of patent application 23. The method for forming the thickness of the composite gate dielectric layer according to item 20 of the patent application scope, wherein the first silicon oxide layer is removed by using a hydrofluoric acid solution. 2 4. The method for forming the thickness of the composite gate dielectric layer according to item 20 of the patent application scope, wherein the first silicon oxide layer is removed by using a BOE solution. 25. The method for forming the thickness of the composite gate dielectric layer according to item 20 of the patent application scope, wherein the first silicon nitride layer is removed by using a hot phosphoric acid solution. 26. The method for forming the thickness of the composite gate dielectric layer according to item 20 of the patent application scope, wherein the first silicon nitride layer is formed by a chemical vapor deposition method. 2 7. The method for forming the thickness of the composite gate dielectric layer according to item 20 of the patent application scope, wherein the second silicon nitride layer is formed by chemical vapor deposition Page 17