TW560024B - Semiconductor package and substrate thereof - Google Patents

Semiconductor package and substrate thereof Download PDF

Info

Publication number
TW560024B
TW560024B TW091116215A TW91116215A TW560024B TW 560024 B TW560024 B TW 560024B TW 091116215 A TW091116215 A TW 091116215A TW 91116215 A TW91116215 A TW 91116215A TW 560024 B TW560024 B TW 560024B
Authority
TW
Taiwan
Prior art keywords
substrate
groove
layer
patent application
scope
Prior art date
Application number
TW091116215A
Other languages
Chinese (zh)
Inventor
Chi-Tsung Chiu
Ted Wang
Samuel Wu
Jenny Chen
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW091116215A priority Critical patent/TW560024B/en
Priority to US10/394,347 priority patent/US6770979B2/en
Application granted granted Critical
Publication of TW560024B publication Critical patent/TW560024B/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package is characterized by having at least one cavity defined in a substrate and at least one buffer pad disposed in the at least one cavity. The semiconductor package further includes a semiconductor chip disposed on the substrate, at least one conductive trace connecting to the buffer pad and at least one bonding wire electrically connecting the semiconductor chip to the buffer pad. The buffer pad has a thickness larger than the thickness of the conductive trace.

Description

560024 一 91116215_i 月日_i±i.___ 五、發明說明（1) 【發明領域】 本發明係有關於一種半導體封裝構造及其使用之封裝基 板，特別有關於一種針對消除或改善信號反射而設計之半 導體封裝構造及其使用之封裝基板。 【先前技術】 在今日成長快速的電子產品世界中，高速電路是一個主 要的發展趨勢。然而發展高速電路所要解決的主要課題之 一便是如何保持信號的完整性（S i g n a 1 i n t e g r i t y )，使 訊號在抵達線路的另一端時，仍然能保持正確的波形。如 果信號的完整性無法保持，就可能造成電路的誤動作，例 如使系統輸出不正確的數據、電路工作不正常甚至完全不 工作，這類的問題可以讓一個產品在市場上完全無=^ 存。電路中有許多雜訊的來源，而信號的反射（3 reflection)則是其中之一。 所謂的信 如銅線）傳 一端，還被 確的信號在 原來之正確 時，便會發 種現象的影 造成信號 接線路）之 )，另一個 號反射是指 送時，有部 反射回其來 不同的位置 仏5虎的波形 生信息誤判 響也越嚴重 反射有兩個 間阻抗不匹 則是連接線 ，§ 一個信號被沿著一個介質（例 分信號不但沒有被傳送到介質的另 自的方向。反射的信號會對原來正 發生建設性或破壞性干涉，而改變 ’因此當接收到此一不正確之信號 而且當#號傳遞速度越快時，這 〇 主因，一是相互連接之介質（即連 配（impedance miss matching 路性質非線性改變（non linear560024 一 91116215_i 月 日 _i ± i .___ 5. Description of the Invention (1) [Field of the Invention] The present invention relates to a semiconductor package structure and a packaging substrate used therefor, and more particularly to a design for eliminating or improving signal reflection Semiconductor package structure and the package substrate used by the same. [Previous technology] In today's fast-growing electronics world, high-speed circuits are a major development trend. However, one of the main issues to be solved in the development of high-speed circuits is how to maintain signal integrity (S i g n a 1 i n t e g r t y) so that the signal can still maintain the correct waveform when it reaches the other end of the line. If the integrity of the signal cannot be maintained, it may cause malfunction of the circuit, such as making the system output incorrect data, the circuit is not working properly or even not working at all. Such problems can make a product completely non-existent in the market. There are many sources of noise in the circuit, and signal reflection (3 reflection) is one of them. The so-called letter such as copper wire) is transmitted at one end, and when the signal is confirmed to be correct, it will cause a phenomenon to affect the signal connection line.))), The other number reflection refers to the part that is reflected back to From different locations, the mismatch of the waveform information of the 5 tigers is also more serious. The two impedances that are not matched are the connecting lines. § A signal is transmitted along a medium (for example, the signal is not transmitted to the other The reflected signal will interfere constructively or destructively with the original, and change 'so when the incorrect signal is received and the faster the # number is transmitted, the main reason is that one is connected to the other Medium (ie, linearity of impedance miss matching)

560024 月 曰 案號9111防15 五、發明說明（2) change )。所謂「非線性改變 半導舻曰H w4 具體的說，以一習用之 金缓暮人其i 、胃+ & 田日日片傳迗出之電流信號從 法睡Η妯道士 u τ — ^ 置置方向的電流量往往無 居％間被導成水平流向，因而造成 (discontinuity )，且在此不連續點合貝右 反射。本發明因此提供能克服或改盖^曰有相虽大的仏唬 半導體封裝構造。 或文。則述信號反射問題的 【發明概要】 古目的係提供一種半導體封裝構造，其使用之封 ί ί ΐ 2服或改善在晶片與基板上的線路打線連接之 接墊處、，因非線性改變而造成之信號反射問題。 為了達成上述及其他之目的，本發明提供一種半導體封 裝，造L其主要包含一基板包含複數個導電線路，一半導 月豆日日片。又於边基板之上表面以及複數個導線將該半導體晶 片與基板的導電線路電性連接。本發明之特徵在於該基板 具有至少一凹槽設在基板與從半導體晶片延伸出來的導線 連接處。該至少一凹槽内設有與基板上的導電線路連接之 緩衝墊’且該緩衝墊具有一厚度大於導電線路之厚度。因 此’從sa片經導線以垂直方向傳送到基板之導電線路的電 流信號’能在該加厚之緩衝墊内被引導成水平傳遞，藉此 有助於克服或至少改善信號反射的現象。 該基板上之凹槽的深度約為基板厚度的約1 / 3到約丨/ 5之 間’缓衝蟄的尽度則大致與該凹槽之深度相同。緩衝塾與 基板上的導電線路係由大致相同材料製成，一般係選擇導560024 month said case number 9111 defense 15 V. Description of the invention (2) change). The so-called "non-linear change semiconductor" H w4 specifically, the current signal transmitted by i, stomach + & Tian Ri-ri film from a conventional gold slow twilight from the Taoist priest u τ — ^ The amount of current in the placement direction is often led into a horizontal flow direction, resulting in (discontinuity), and at this discontinuity point right reflection. The present invention therefore provides a solution that can overcome or change the cover. [Abstract of the Invention] The ancient purpose is to provide a semiconductor package structure, which is used to seal 2 or improve pads for wiring connections between a chip and a substrate. In order to achieve the above-mentioned and other objectives, the present invention provides a semiconductor package, which mainly includes a substrate including a plurality of conductive lines, and half of the moon-day-sun-day plate. The semiconductor wafer is electrically connected to the conductive line of the substrate on the upper surface of the side substrate and a plurality of wires. The invention is characterized in that the substrate has at least one groove provided in the substrate The connection point of the wires extending from the semiconductor wafer. A buffer pad connected to the conductive line on the substrate is provided in the at least one groove, and the buffer pad has a thickness greater than the thickness of the conductive line. The current signal transmitted to the conductive line of the substrate in the vertical direction can be guided to be transmitted horizontally in the thickened cushion, thereby helping to overcome or at least improve the phenomenon of signal reflection. The depth of the groove on the substrate is about The thickness of the buffer 蛰 is about the same as the depth of the groove between about 1/3 to about 丨 / 5 of the thickness of the substrate. The buffer 塾 and the conductive lines on the substrate are made of approximately the same material, and generally Select Guide

00523. ptc 第7頁 560024 月 曰 修正 案號 91116215 五、發明說明（3) 電性良好的銅。一般而言，登 體晶片與基板上的導電線路之導;；f作為電性連接半導 有好的連接，該緩衝墊另勺人一、 為了使金線與銅線路 層在該鎳層之上。另外，嗲二=層形成於其上以及一金 於其下表面’該導電線路；J屬塾形成 該f屬墊，再經由該金屬墊利用錫球=性連接於 的方法。 則述+導體晶片封裝之基板 第：=法：利用習用之基板加工成適 板其包含之步驟將敘述於下。首先，接 *月之基 數個導電線路的基板以及一防r声 "上已具有複 著，以機械鑽孔戋雷射饈丨望:二so er mask )。接 槽。再選摆I道鑽孔專方式在基板中形成至少一凹 再=擇性地以導電性材料（與 凹 半導體晶片。一緩衝塾用以打線連接於該 -凹样.板之整個上表面，僅露出該至少 層導電材料於該基板之上表 尤積- 基板上除去·五上衣面，接者，將忒第一遮蔽層從 該防銲層裸露二遮蔽層於ΐ基板上表面所有從 然後，藉電㉟（η 1路上，僅裸露出該至少—凹槽； 槽；最後，=erropiating)以該導電材料填滿該凹 在除去今笛亥苐二遮蔽層而完成該填滿步驟。另外， 二第—遮蔽層之前，可形成一鎳層於該緩衝墊 以及形成一金層於鎳層上。 ^上， i 00523.ptc 第8頁 56002400523. ptc page 7 560024 month said amendment number 91116215 V. Description of the invention (3) Copper with good electrical properties. Generally speaking, the conductor of the die chip and the conductive circuit on the substrate; f has a good connection as an electrical connection semiconductor, the cushion pad is another one, in order to make the gold wire and copper circuit layer in the nickel layer on. In addition, a second layer is formed thereon and a gold layer is formed on the lower surface of the conductive line; the method of forming the f-generating pad by J is a method of forming a f-pad, and then using the metal pad to connect to the pad via the metal pad. The substrate of + conductor chip package is described as follows: = Method: The conventional substrate is used to process into a suitable board. The steps involved are described below. First of all, there are already several copies of the substrate of a few conductive lines connected to * Yuezhi, and an anti-r sound. "Mechanical drilling (laser) (look: two so er mask). Slot. Then select a drilling method to form at least one recess in the substrate. Selectively use a conductive material (and a concave semiconductor wafer. A buffer is used to wire the -concave sample. The entire upper surface of the board, only Exposing the at least one layer of conductive material on the substrate. The surface is removed. Five tops are removed from the substrate. Then, the first shielding layer is exposed from the solder mask layer. The two shielding layers are exposed from the upper surface of the substrate. Borrowing electricity (On the η 1 road, only at least the groove is exposed; the groove; finally, = erropiating) fills the recess with the conductive material and removes the two shielding layers of the current dioxin to complete the filling step. In addition, Second-Before the masking layer, a nickel layer can be formed on the cushion pad and a gold layer can be formed on the nickel layer. ^ On, i 00523.ptc page 8 560024

ΛΜ 9ine?.iR 五、發明說明（4) 根據本發明之另一插主谐1 包含下列步驟。首先，以：=片J裝基板製造方法，其 至少-凹槽於-彳電声」械鑽孔或雷射鑽孔等方式形成 層。然後，形成一金屬層‘：：5:數個通孔貫穿該介電 該至少一凹槽及該通孔内呷7 Μ二f層之整個表面（包含 層在該介電層上形成一預先π〜選擇性蝕刻該金屬 電線路設於該介電層上=5:=路佈局包含複數個導 係覆蓋於該至少一凹槽上。二:至^、一導電線路之—端 (相同於前述之金屬層之材料）ί滿ί = = 材料 =，該選擇性填滿步驟係先將一防鮮層塗佈二介ς it。表面以及該導電線路上，僅裸露出該至少-凹 :道=糟由電鍍以該導電材料填滿該凹㉟。接著，除去 邊”線路預先設定部分（例如手指或錫球鋒塾區域)1 之防ί于層，然後利用電鍍同時形成一鎳層於該介電層上 面自該遮蔽層裸露出之導電線路預先設定部分以及二緩衝 墊上；以及形成一金層於鎳層上。 【發明說明】 第1圖圖示根據本發明一實施例之半導體封裝構造丨〇。 該半導體封裝構造10主要包含一基板丨00、一半導體晶片 1 〇 2設在基板1 〇 〇之上表面1 〇 4。本發明之特徵在於該基板 具有一個凹槽108 (不限於一個，複數個亦可）界定二其 中’且該凹槽108中設有一緩衝墊（buffer pad ) 1 1〇與基 板100之上表面1〇4的導電線路112連接，其中該緩衝墊11〇ΛΜ 9ine? .IR 5. Description of the Invention (4) Another main harmonic 1 according to the present invention includes the following steps. First, a layer is formed by: = a method of manufacturing a J-mount substrate, which at least -recesses- 彳 electroacoustic "mechanical drilling or laser drilling. Then, a metal layer is formed :: 5: a plurality of through holes penetrating the entire surface of the dielectric, the at least one groove, and the 7 M 2 f layer (the layer includes a pre-formed layer on the dielectric layer) π ~ selectively etch the metal electrical line on the dielectric layer = 5: = The circuit layout includes a plurality of conductors covering the at least one groove. 2: to ^, the end of a conductive line (same as The material of the aforementioned metal layer) = full = = material =, the selective filling step is to first coat a fresh-proof layer with two media. It only exposes the at least -concave on the surface and the conductive line: Track = fill the recess with the conductive material by electroplating. Then, remove the edge protection layer (such as the finger or the area of the tin ball) 1 from the edge, and then use electroplating to form a nickel layer at the same time. The conductive layer exposed on the dielectric layer from the shielding layer is provided with a predetermined portion and two buffer pads; and a gold layer is formed on the nickel layer. [Explanation of the Invention] FIG. 1 illustrates a semiconductor package according to an embodiment of the present invention. Structure 丨 〇. The semiconductor package structure 10 mainly includes a substrate丨 00, a semiconductor wafer 1 002 is provided on the substrate 1 OO above the surface 104. The present invention is characterized in that the substrate has a groove 108 (not limited to one, a plurality of can also) define two of them, and the A buffer pad 1 1 10 is provided in the groove 108 and is connected to the conductive line 112 on the upper surface 10 of the substrate 100, wherein the buffer pad 11

五、發明說明（5) 八有厚度大於泫導電線路Π 2的厚度。另外有複數條導 線11 4 ( 一般係為金線）將該晶片i 〇2電性連接於該緩衝墊 110以及π亥基板1〇〇之其他接塾（c〇ntact pacj)〗3〇。 該基板1 00上之凹槽1 08的深度係設計為基板1〇〇厚度的 約1/3到約1/5之間。緩衝墊11〇的厚度則大致與該凹槽1〇8 之深度相同，使得該緩衝墊11〇之厚度大於該導電線路ιΐ2 的厚度。緩衝墊110與基板上的導電線路n2大致由相同材 料製成’ -般係選擇導電性良好的銅。因此，為了 質之導線1!4與銅材質的緩衝墊11〇有好的連接，緩衝塾 110另包含一錄層（未示於圖中）形成於其上以及一金層 (未示於圖中）在該鎳層之上。 基板100另具有複數個通孔116貫穿 ;有”層118藉此將上表面之導電線路112電性連接至下 :面之V電線路120以及作為錫球銲墊之 塾122上設有錫球124用以與外界電性連接屬塾 金屬 為了保護基板1 0 0上的繞敗德已，、，77 路受潮濕等因素影響，該基板1⑽ 防止基板MG内部線 裸露出與晶片電性連接的二墊UQ、面具有一防銲層Μ僅 122。另外，該半導Λ Λ 、緩衝墊110以及金屬墊 且封Α構造10還包含— 片1 02以及基板上導電線路i i 2 3封膠體1 28將日日 以防止水氣、灰塵或是二=連接的部分包覆起來， 本發明另提供兩種製造半導體a α、對八仏成之破壞。 特別疋製过具有刖述緩衝墊之基板的 主要步驟將參照第2a-2g圖描述於下。法。第一種方法之 述X下百先，提供一個利 560024 Λ_3 曰 一案號 91116215 五、發明制⑹ 爾-- 用習知技術製造完成之基板，如第2a圖所示，該基板2〇() 已具有複數個通孔1 1 6、預先設定之電路佈局（包含基板 上表面104之導電線路112、基板下表面1〇6之導電線二12〇 以及作為錫球銲墊之金屬墊122 )以及防銲層126。 下一步，如第2b圖所示，以機械鑽孔或雷射鑽孔等方式 在基板20 0上表面1〇4預先設定之處，形成至少一凹槽 1 〇 8 ’其中該凹槽1 〇 8的深度約為基板2 〇 〇厚度的1 / 3到 1/5。根據本發明一實施例，當基板1〇〇的厚度為丨⑽ 時’凹槽1 0 8的深度可設計為2 0 // m。 再選擇性地以導電性材料（與導電線路相同材料，例如 銅2填滿該凹槽108以形成至少一緩衝墊丨丨〇用以打線連接 於違半導體晶片1 〇 2。根據本發明之一實施例，該選擇性 填滿步驟係先形成一遮蔽層2〇2於基板2〇〇的整個表面或至 少基板20 0的上半部表面上，具體的說即是將該遮蔽層2〇2 A成於基板2 0 0表面之防銲層1 2 6和裸露於防銲層1 2 β之外 的其他部分上，僅裸露出基板2〇〇上的凹槽ι〇8部分（如第 2 c圖所示）。根據本發明一實施例，該遮蔽層2 〇 2可利用 一膠帶直接貼附於基板2 〇 〇上而形成。 參見第2d圖，再以無電電鍍（electr〇丨ess pUting) 的方式於基板200的遮蔽層202以及凹槽i〇8内部的表面上 ，上一層與導電線路相同材料之金屬層2〇4。具體的說， 热電電鍍係將基板200之上半部之遮蔽層2〇2表面以及凹槽 =8内部之表面與欲作為鍍核（nuc]Leus plating)之物 貝（例如纪）接觸’然後再與無電極電鍍溶液（例如在本V. Description of the invention (5) The thickness is larger than the thickness of the 泫 conductive line Π 2. In addition, there are a plurality of wires 11 4 (generally gold wires) which electrically connect the chip i 〇2 to the buffer pad 110 and other connections (cntact pacj) 30 of the π substrate 100. The depth of the groove 108 on the substrate 100 is designed to be between about 1/3 and about 1/5 of the thickness of the substrate 100. The thickness of the cushion pad 110 is substantially the same as the depth of the groove 108, so that the thickness of the cushion pad 110 is greater than the thickness of the conductive line ι2. The cushion pad 110 and the conductive line n2 on the substrate are made of substantially the same material. Generally, copper having good conductivity is selected. Therefore, in order to have a good connection between the quality wires 1! 4 and the copper-made cushion pad 110, the buffer 塾 110 further includes a recording layer (not shown) formed on it and a gold layer (not shown in the figure). Middle) on the nickel layer. The substrate 100 further has a plurality of through holes 116 penetrating therethrough; there is a "layer 118" thereby electrically connecting the upper conductive circuit 112 to the lower: the V electrical circuit 120 on the upper surface and the solder ball 122 provided with solder balls 124 is used to electrically connect with the outside world. It is a metal. In order to protect the winding circuit on the substrate 100, the 77th channel is affected by humidity and other factors. The substrate 1⑽ prevents the internal wires of the substrate MG from being exposed and electrically connected to the chip. The two pads UQ and the mask have a solder mask M of only 122. In addition, the semiconducting Λ Λ, the buffer pad 110 and the metal pad and the seal A structure 10 also include — a piece 102 and a conductive line on the substrate ii 2 3 sealing gel 1 28 Wrapped daily to prevent moisture, dust, or two connected parts. The present invention also provides two kinds of semiconductor a α, which destroys the Bachengcheng. The substrate with the above-mentioned buffer pad is specially fabricated. The main steps will be described below with reference to Figures 2a-2g. Method. The description of the first method X Xiabaixian, provide a benefit 560024 Λ_3 Case No. 91116215 V. Inventing the system-Manufacturing using conventional technology The completed substrate, as shown in Figure 2a, the substrate 20 () has There are a plurality of through holes 1 1 6. Pre-set circuit layout (including the conductive line 112 on the upper surface of the substrate 104, the conductive line 2 120 on the lower surface of the substrate 10 and the metal pad 122 as a solder ball pad), and The solder layer 126. Next, as shown in FIG. 2b, mechanical drilling or laser drilling is used to form at least one groove 10 on the upper surface of the substrate 20 in advance. The depth of the groove 108 is about 1/3 to 1/5 of the thickness of the substrate 2000. According to an embodiment of the present invention, when the thickness of the substrate 100 is ⑽, the depth of the groove 108 may be Designed as 2 0 // m. Then the conductive material (the same material as the conductive line, such as copper 2) is used to fill the groove 108 to form at least one cushion pad 丨 丨 for wire connection to the semiconductor chip 1 〇2. According to an embodiment of the present invention, the selective filling step is to first form a shielding layer 200 on the entire surface of the substrate 2000 or at least the upper half of the substrate 200, specifically, The masking layer 202 is formed on the surface of the substrate 200 with a solder mask 1 2 6 and the solder mask 1 2 β is exposed. On the other parts, only the groove 008 part of the substrate 200 is exposed (as shown in FIG. 2c). According to an embodiment of the present invention, the shielding layer 002 can be directly using an adhesive tape. It is formed by being attached to the substrate 2000. Referring to FIG. 2D, the surface of the shielding layer 202 of the substrate 200 and the inside of the groove i08 is electrolessly plated (electron plating), and the upper layer and the The metal layer 204 of the same material as the conductive line. Specifically, the thermoelectric plating method uses the surface of the shielding layer 200 and the surface of the groove = 8 in the upper half of the substrate 200 and the surface to be used as a core (nuc) Leus. plating), and then contact it with an electrodeless plating solution (eg.

00523. ptc 第11頁 560024 ----隸91116215 _年月 η 修正 五、發明說明（7) -—--- 只轭，係使用無電銅浴（electroless copper bath))接 觸使彳于遮蔽層202之表面以及凹槽108内部之表面係為該鍍 層金屬覆蓋，且該金屬層2〇4與鄰接於凹槽1〇8之導電線^ 11 2〜形成電性連接。接下來，將覆該在基板上半部表面的 遮蔽層202除去之後，便只有在凹槽1〇8内部表面留下一声 金屬層20 6 (如第2e圖所示）。 曰 參^第2f圖，然後形成另一遮蔽層21〇於該基板1〇〇上表 面覆蓋所有從該防銲層丨26裸露出的導電線路部分（例如 接點130處），而僅裸露出該凹槽1〇8。根據本發明之實施 例，該遮蔽層210可利用一膠帶直接貼附於基板2〇〇上而形 成。 接著，利用電鍍（electroplating )在具有金屬層2〇6 之凹槽108處鍍上金屬填滿該凹槽丨〇8形成緩衝墊11〇之 後。最後，除去遮蔽層2 1 0便製得到本發明之具有緩衝墊 110之基板2 0 8 (參見第2g圖）。 另外’為了使銅材質的緩衝墊1 1 0與金材質導線1 1 4具有 良好的接合性’可在除去遮蔽層21 0之前利用電鍍選擇性 地在裸露的緩衝墊110上形成一鎳層以及在鎳層上形成金 層。 / 本發明另提供一種製造半導體晶片封裝之基板的方法， 其主要步驟將參照第3a-3g圖描述於下。首先，參見第^ 圖，提供一個介電層302 (適合之介電材質如 BIXbismaleimide-triazine)樹脂或FR-4破璃纖維強化環 氧樹脂（fiberglass reinforced epoxy resin))。然德衣，00523. ptc p. 11560024 ---- slave 91116215 _ year month η amendment five, description of the invention (7) --- --- only yoke, using an electroless copper bath (electroless copper bath) to make contact with the shielding layer The surface of 202 and the surface inside the groove 108 are covered by the plating metal, and the metal layer 204 is electrically connected to the conductive line ^ 11 2 ~ adjacent to the groove 108. Next, after the shielding layer 202 covering the upper half of the substrate is removed, only a sound metal layer 20 6 is left on the inner surface of the groove 108 (as shown in FIG. 2e). Refer to Figure 2f, and then form another shielding layer 21o on the top surface of the substrate 100 to cover all the conductive circuit parts exposed from the solder mask layer 26 (such as the contact 130), and only expose it. The groove 108. According to an embodiment of the present invention, the shielding layer 210 can be directly formed on the substrate 2000 by using an adhesive tape. Next, electroplating is used to fill the groove 108 with a metal layer 20 to fill the groove 108 to form a cushion pad 110. Finally, the shielding layer 2 10 is removed to obtain a substrate 2 8 with a cushion pad 110 according to the present invention (see FIG. 2g). In addition, 'in order to have good bonding between the copper cushion pad 1 10 and the gold material lead 1 1 4', a nickel layer can be selectively formed on the exposed cushion pad 110 by electroplating before removing the shielding layer 210. A gold layer is formed on the nickel layer. / The present invention further provides a method for manufacturing a substrate for a semiconductor wafer package, the main steps of which are described below with reference to FIGS. 3a-3g. First, referring to FIG. ^, A dielectric layer 302 (suitable dielectric material such as BIXbismaleimide-triazine) resin or FR-4 fiberglass reinforced epoxy resin is provided. Ran Deyi,

560024 月 修正 曰 91116215 五、發明說明（8) 以機械鑽孔或雷射鑽孔等方式在介電層3〇2上預先設定之 位^形成至一凹槽1〇8以及複數個通孔〗16 (如第3b圖所 示 多見第3(：圖，將—金屬層304 (例如銅）以無電電 鍍的方式形成在該介電層302之整個表面（包含凹槽1〇8及 通孔|16内部）。接著，以微影（灿〇忧1丨讣〇^叩^)以及 蝕刻（etching)的方式在介電層3〇2上金屬層3〇4中形成所 要之線路佈局，％第3d圖所示，該電路佈局包含介電層 3 02上表面之導電線路112、通孔内部之金屬層ιΐ8、介電 層302下表面之導電線路12〇以及作為銲墊之金屬墊丨22。 ^主意的是，至少一導電線路〗12之一端係覆蓋於該凹槽 舜w >照第3eK，提供一防銲層（solder mask) 126 後盍於該介電層302與該導電線路〗12 =是，在此步驟中，防鲜層126之外僅裸露K蓋;':主 ^電線路112之-端的凹槽m，但是介電層川上表面預 3定裸露於防録層126外的接墊⑶此時係被防銲層126 r ='圖，利用電鍍（electr〇platlng)在裸露於防 Γ:古且具有金屬層之凹槽108處鍍上金屬（例如銅 )直到填滿該凹槽1 〇8形成緩衝墊110。接著，再除去 電層302上表面預先設定裸露於防銲層126外的接墊 Γ 防銲層1 26而得到本發明具有緩衝塾11 G之基板3〇〇 C如第3 g圖所示）。 另外，為了使銅材質的緩衝墊丨丨〇與金材質導線11 4具有 义好的接合性，第3g圖所示之基板3〇〇可利用電鍍同時在560024 Amended in January 91116215 V. Description of the invention (8) Pre-set positions on the dielectric layer 30 by mechanical drilling or laser drilling ^ are formed to a groove 108 and a plurality of through holes. 16 (As shown in FIG. 3b, the most common 3 (: figure, the metal layer 304 (such as copper) is formed by electroless plating on the entire surface of the dielectric layer 302 (including the groove 108 and the through hole). | 16 内). Next, a desired circuit layout is formed in the dielectric layer 302 and the metal layer 304 by lithography (Cano 1 1 讣 讣 ^^^) and etching,% As shown in FIG. 3d, the circuit layout includes a conductive line 112 on the upper surface of the dielectric layer 302, a metal layer 8 in the through hole, a conductive line 12 on the lower surface of the dielectric layer 302, and a metal pad serving as a solder pad. ^ The idea is that one end of at least one conductive line 12 covers the groove. According to 3eK, a solder mask 126 is provided, and then the dielectric layer 302 and the conductive line are provided. 〖12 = Yes, in this step, only the K cover is exposed outside the anti-frying layer 126; ': the groove m at the-end of the main circuit 112, but the dielectric The pads on the upper surface of the river are scheduled to be exposed outside the anti-recording layer 126. ⑶At this time, the solder resist 126 r = 'picture, using electroplating (electroplating) to expose the grooves of the anti-Γ: ancient and metal layer Metal (such as copper) is plated at 108 until the groove 100 is filled to form the cushion pad 110. Then, the upper surface of the electrical layer 302 is removed and the pads exposed outside the solder resist layer 126 are set in advance Γ solder resist 1 26 The substrate 300C with buffer 塾 11 G of the present invention is obtained as shown in Fig. 3g. In addition, in order to make the copper-made buffer pad 丨 丨 〇 and the gold-made wire 11 4 have a good bonding, the first The substrate 300 shown in 3g can be electroplated at the same time.

I 00523. ptc 第13頁 560024 修正 曰 案號 五、發明說明（9) 裸露於防銲層之外的緩衝墊11〇以及接墊13〇上形成一鎳層 以及在鎳層上形成金層。 本發明之特徵在於提供至少一個厚度大於導電線路的緩 衝墊δ又在用以連接晶片與基板之導線與基板上導電線路的 連接處。藉由該緩衝墊的設計，使從晶片經導線以垂直方 向傳送到基板之導電線路的信號，能在一緩衝區間内被引 導成水平傳遞。為了證明本發明確有助於克服或至少改善 信號反射的現象，本發明另提供利用Ans〇ft公司的高頻結 構模擬（high frequency structure simulator)軟體得 到之電腦模擬結果。詳細言之，先輸入本發明之半導體晶 片封裝（具有增厚之緩衝墊）以及習用之半導體晶片封裝 (僅具有一般厚度之接墊而沒有設置緩衝墊）的立體結 構，再δ又疋^號激發點（e χ c丨t a t丨〇 n p 〇 r七）以及傳送之 信號的頻率範圍，最後進行模擬而得到前述導線與導電線 路在傳送ldB信號時的信號反射量（如第4圖所示）。由第 4圖可清楚看出，本發明具有緩衝墊之半導體晶片封裝， ^測得之信號反射量在不同的頻率範圍皆較沒有設置緩 ^之習用半導體晶片封裝低。因此，本發明提供之具有緩 衝墊的封裝基板結構能有效降低信號反射量。 Z然本發明已以前述較佳實施例揭示，然其並非 4發明，任何熟習此技藝者’纟不脫離本發明之 =内：當可作各種之更動與修改。因此本發明之保護^ 圍田視後附之申清專利範圍所界定者為準。I 00523. ptc Page 13 560024 Amendment No. V. Description of the Invention (9) A nickel layer is formed on the cushion pad 11 and the pad 13 which are exposed outside the solder resist layer, and a gold layer is formed on the nickel layer. The present invention is characterized in that at least one buffer pad δ having a thickness greater than that of the conductive circuit is provided at a connection between a wire for connecting the chip and the substrate and the conductive circuit on the substrate. With the design of the buffer pad, the signal transmitted from the chip to the conductive line of the substrate in a vertical direction through the wire can be guided to be transmitted horizontally in a buffer zone. In order to prove that the present invention does help to overcome or at least improve the phenomenon of signal reflection, the present invention also provides computer simulation results obtained by using high frequency structure simulator software of Ansft. In detail, first enter the three-dimensional structure of the semiconductor wafer package of the present invention (having a thickened cushion pad) and the conventional semiconductor wafer package (having only pads of ordinary thickness without providing a cushion pad), and then δ and ^^ The excitation point (e χ c 丨 tat 丨 〇np 〇rVII) and the frequency range of the transmitted signal, and finally the simulation is performed to obtain the signal reflection of the aforementioned wires and conductive lines when transmitting the ldB signal (as shown in Figure 4) . It can be clearly seen from FIG. 4 that in the semiconductor chip package with a cushion pad of the present invention, the measured signal reflection amount in different frequency ranges is lower than that of a conventional semiconductor chip package without a retarder. Therefore, the package substrate structure provided with the buffer pad of the present invention can effectively reduce the amount of signal reflection. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not an invention. Any person skilled in the art will not depart from the scope of the present invention: various changes and modifications can be made. Therefore, the protection of the present invention ^ is subject to the definition of the scope of the patent application.

圖式簡單說明 【圖示說明】 為了讓本發明之上述和其他目的、特徵、和 顯，下文特舉本發明較佳實施例，並配合I二點能更明 細說明如下。 、圖示，作*羊 第1圖·根據本發明一實施例之半導體封裝構生 圖； k之剖示 第2a-2g圖··根據本發明一實施例，以剖示圖 體晶片封裝基板製造方法的主要步驟； ^ ，第3a-3g圖：根據本發明另一實施例，以剖示圖圖示半 導體晶片封裝基板製造方法的主要步驟；及 第4圖：根據本發明一實施例之半導體封裝構造（具有 增厚之緩衝墊）以及習用半導體封裝構造（僅具有一般厚 度之接墊）在傳送不同頻率彳㊂號時，信號反射之電腦模擬 結果。 【圖號說明] 10 100 半導體封裝構造 基板 102 半導體晶片 104 上表面 106 下表面 108 凹槽 110 緩衝墊 112 導電線路 114 導線 116 通孑L 118 通孔内金屬層 120 導電線路 122 金屬墊 124 鮮錫凸塊 126 防銲層 560024 __案號 91116215_年月日_修正 圖式簡單說明 128 封 膠體 130 接 墊 200 基 板 202 遮 蔽 層 204 金 屬層 206 凹 槽 内金屬層 208 基 板 210 遮 蔽 層 300 基 板 302 介 電 層 304 金 屬層Brief Description of the Drawings [Illustration] In order to make the above and other objects, features, and manifestations of the present invention, the following describes the preferred embodiments of the present invention in combination with the two points I can explain in more detail as follows. Figures are shown as the first figure of the sheep. A semiconductor package structure diagram according to an embodiment of the present invention. Section 2a-2g of k .. According to an embodiment of the present invention, the chip package substrate is shown in section. Main steps of the manufacturing method; ^, Figures 3a-3g: According to another embodiment of the present invention, the main steps of the method for manufacturing a semiconductor wafer package substrate are shown in cross-sectional views; and Figure 4: According to an embodiment of the present invention Computer simulation results of signal reflection when the semiconductor package structure (with thickened cushion pads) and the conventional semiconductor package structure (only pads with general thickness) are transmitted at different frequencies. [Illustration of drawing number] 10 100 semiconductor package structure substrate 102 semiconductor wafer 104 upper surface 106 lower surface 108 groove 110 buffer pad 112 conductive line 114 wire 116 through L 118 metal layer in through hole 120 conductive line 122 metal pad 124 fresh tin Bump 126 Solder mask layer 560024 __Case No. 91116215_Year Month and Day_Revision of the schematic diagram 128 Sealant 130 Pad 200 Substrate 202 Masking layer 204 Metal layer 206 Metal layer in the groove 208 Substrate 210 Masking layer 300 Substrate 302 Dielectric layer 304 metal layer

00523. ptc 第16頁00523.ptc page 16

Claims (1)

560024 _案號91H62j5_年月 a_修正_ 六、申請專利範圍 1、一種半導體封裝構造，其包含： 一基板具有一上表面、一下表面以及至少一凹槽界定於 其中； 該基板之上表面係設有至少一緩衝墊（buf f er pad )於 該至少一凹槽中，以及至少一導電線路連結於該緩衝墊， 其中遠緩衝塾具有一厚度大於該導電線路的厚度； 一半導體晶片設於該基板之上表面；以及 至少一導線電性連接於該半導體晶片與緩衝墊之間。 2、 依申凊專利範圍第1項之半導體封裝構造，其中該基板 之凹槽具有一深度，其為基板厚度的約1/3到約1/5。 3、 依申睛專利範圍第}項之半導體封裝構造，#中該基板 之凹槽具有一深度約為20 //in。 其中該緩衝 V Λ申請專利範圍第1項之半導體封裝構造 墊具有一厚度大致相同於該基板凹槽之深度。 5塾以依及V導專需利：圍第1項之半導體封裝構造，其中該緩衝 墊以及遠導電線路皆由大致相同的材料製成。 裝構造，其另包含一 錄層形成於該緩衝墊 、依申請專利範圍第1項之半導體封 上以及一金層在該鎳層之上560024 _Case No. 91H62j5_ 年月 a_ CORRECTION_ VI. Scope of Patent Application 1. A semiconductor package structure comprising: a substrate having an upper surface, a lower surface and at least one groove defined therein; an upper surface of the substrate At least one buffer pad (buf fer pad) is provided in the at least one groove, and at least one conductive line is connected to the buffer pad, wherein the remote buffer pad has a thickness greater than the thickness of the conductive line; a semiconductor chip design On the upper surface of the substrate; and at least one wire is electrically connected between the semiconductor wafer and the buffer pad. 2. The semiconductor package structure according to item 1 of the patent application, wherein the groove of the substrate has a depth which is about 1/3 to about 1/5 of the thickness of the substrate. 3. According to the semiconductor package structure of item} in the patent scope, the groove of the substrate in # has a depth of about 20 // in. The semiconductor package construction pad of the buffer V Λ application patent scope has a thickness approximately the same as the depth of the substrate groove. (5) In accordance with the special requirements of the V guide: the semiconductor package structure of item 1, in which the cushion pad and the remote conductive line are made of approximately the same material. The mounting structure further includes a recording layer formed on the cushion pad, a semiconductor package according to item 1 of the patent application scope, and a gold layer on the nickel layer. 00523. ptc 第17頁 560024 案號 91116215 六、申請專利範圍 7、依申請專利範圍第丨項之半導體封裝構造，該美 :牙一板以及表面鍍有金屬層之通孔電性連接於該金屬 8、 一種用於封裝一半導體晶片之基板，該基板包含： 至少一凹槽界定於該基板中； 板已3 至少一緩衝塾設於該至少一凹梓φ，兮p ^ ^ ^ ^ ^ ^ 凹槽中，该緩衝墊用以打線 連接於讜+導體晶片；以及 至少一導電線路連接於該緩衝墊， 其中該緩衝墊具有一厚度大於該導電線路之厚度。 9、 依申請專利範圍第8項之用於封裝—半導體晶片的基 板，其中該該基板之凹槽具有一深度，其 約 1 / 3 到約 1 / 5。 i ^ f X ι〇、依申請專利範圍第8項之用於封裝_半導體晶片的基 板，其中該基板之凹槽具有一深度約為2 〇 “爪。 11、依申請專利範圍第8項之用於封裝—半導體晶片的基 板，其中該緩衝墊具有一厚度大致相同於該基板凹槽之深 度。 1 2、依申請專利範圍第8項之用於封裝一半導體晶片的基 00523. ptc00523. ptc p. 17560024 case No. 91116215 6. Patent application scope 7. According to the semiconductor package structure of the patent application item 丨, the beauty: a tooth plate and a through hole with a metal layer on the surface are electrically connected to the metal. 8. A substrate for packaging a semiconductor wafer, the substrate comprising: at least one groove defined in the substrate; the board has 3 at least one buffer provided in the at least one recess φ, p ^ ^ ^ ^ ^ ^ In the groove, the buffer pad is used for wire connection to the 谠 + conductor chip; and at least one conductive line is connected to the buffer pad, wherein the buffer pad has a thickness greater than the thickness of the conductive line. 9. The substrate for a packaging-semiconductor wafer according to item 8 of the scope of the patent application, wherein the groove of the substrate has a depth of about 1/3 to about 1/5. i ^ f X 〇. The substrate for packaging _ semiconductor wafer according to item 8 of the scope of patent application, wherein the groove of the substrate has a depth of about 20 ”claws. 11. According to item 8 of the scope of patent application Ptc For packaging-a semiconductor wafer substrate, wherein the buffer pad has a thickness approximately the same as the depth of the substrate groove. 1 2. According to the scope of the patent application No. 8 for packaging a semiconductor wafer base 05523. ptc 第18頁 __—--- 560024 — -案l_9iil.6215 _,上月 日 修正_ 六、申請專利範圍 板’其中該緩衝墊以及該導電線路皆由大致相同的材料製 成。 1 3、依申請專利範圍第8項之用於封裝一半導體晶片的基 板，其另包含一鎳層形成於該緩衝墊上以及一金層在該鎳 層之上。Page 18 __----- 560024 —-Case l_9iil.6215 _, Last month day Amendment _ VI. Patent application scope Board ′ The buffer pad and the conductive line are made of approximately the same material. 1 3. The substrate for packaging a semiconductor wafer according to item 8 of the scope of patent application, which further comprises a nickel layer formed on the cushion pad and a gold layer on the nickel layer. 14、依申請專利範圍第8項之用於封裝一半導體晶片的基 板，其中該緩衝墊係設於該基板之上表面以及該基板具有 複數個金屬墊在其下表面，其中該導電線路經由複數個貫 $該基板以及表面鍍有金屬層之通孔電性連接於該金屬 15、一種半導體晶片封裝基板製造方法 步驟： 提供一基板，其上具有至少—導雷绩 _ ^ L 表係大致被一防銲層（solder mask)覆罢· 形成至少一凹槽於基板中；以及 選擇性地以導電材料填滿該凹槽以形 以打線連接於該半導俨曰μ甘由兮$广ν 緩衝塾用 於該至少-導電ΐ = θ曰片’其少一緩衝塾係連接 度。ν I電線路且具有一厚纟大於該導電線路之厚 1 6、依申請專利範圍第J 叫乐丨b項之牛V脱日日片封裝基板製造方14. The substrate for packaging a semiconductor wafer according to item 8 of the scope of patent application, wherein the buffer pad is provided on the upper surface of the substrate and the substrate has a plurality of metal pads on its lower surface, wherein the conductive line passes through a plurality of A method for manufacturing a semiconductor wafer package substrate is provided through the substrate and through-holes coated with a metal layer on the surface. A method for manufacturing a semiconductor wafer package substrate: Provide a substrate with at least-lightning performance _ ^ L A solder mask is formed to form at least one groove in the substrate; and the groove is selectively filled with a conductive material to form a wire to be connected to the semiconductor. Buffers are used for this at least-conductive = θ chip, which has one less buffer 塾 connection. ν I electrical circuit with a thickness 纟 greater than the thickness of the conductive circuit 1 6. According to the application of the patent application No. J Jiaole 丨 Niu V off the Japanese chip packaging substrate manufacturer 560024 ------案號W116215_ 年 月 曰 铬,下 _ 六、申請專利範圍 去’其中該至少一凹槽係形成於該基板的上表面，該選擇 性填滿步驟包含： 形成一第一遮蔽層於該基板之整個上表面，僅露出該至 少一凹槽； 〆 以無電電鎮（electroless plating)沈積一層導電材 ’料於該第一遮蔽層以及該凹槽的表面； 在進行该無電電鑛步驟之後，將該第一遮蔽層從基板上 除去； si 形成一第二遮蔽層於該基板上表面所有從該防銲層裸露 出之導電線路上，僅裸露出該至少一凹槽； 猎由電鍍（electroplating)以該導電材料填 凹 僧；以及 、 除去該第二遮蔽層。 晶片封裝基板製造方 鎳層於該緩衝墊上；560024 ------ Case No. W116215_ Year Cr, Bottom_ Sixth, the scope of patent application goes to 'wherein the at least one groove is formed on the upper surface of the substrate, the selective filling step includes: forming a first A shielding layer is on the entire upper surface of the substrate, and only the at least one groove is exposed. (1) A layer of conductive material is deposited on the surface of the first shielding layer and the groove by electroless plating; After the electroless electricity mining step, the first shielding layer is removed from the substrate; si forms a second shielding layer on all the conductive lines exposed from the solder mask layer on the upper surface of the substrate, and only the at least one groove is exposed. ; Filling a recessed monk with the conductive material by electroplating; and, removing the second shielding layer. The chip package substrate manufacturer has a nickel layer on the buffer pad; 17、依申請專利範圍第1 6項之半導體 法’另包含下列步驟： 在除去該第二遮蔽層之前，形成一 以及 形成一金層於鎳層上。 18 法 成 依申請專利範圍第1 5項之半導體晶 其中該導電線路以及緩衝墊皆由大 封裝基板製造方 相同的材料製 00523. ptc 第20頁 560024 3號 91116215 六、申請專利範圍 19、依申請專利範圍第15項之半導體晶片封裝基板製造方 法，其中该遠基板之凹槽具有一深度，其為該基板厚度的 約1 / 3到約1 / 5。 20、 依申請專利範圍第15項之半導體晶片封裝基板製造方 法的方法，其中該基板之凹槽具有一深度約為2 〇从瓜。 21、 依申請專利範圍第丨5項之半導體晶片封裝基板製造方 法，其中該凹槽係由機械鑽孔或雷射鑽孔形成。 2 2、》種 步驟： 形成至 形成複 形成一 及該通孔 選擇性 線路佈局 至少一導 選擇性 衝墊用以 —厚度大 半導體晶片封裝基板製造方法，該方法包含下列 少一凹槽於一介電層； 數個通孔貫穿該介電層； ::層覆蓋該介電層之整個表面、該至少一凹槽 該金屬層而在該介電層上形 電魂技夕！路設於該介電層上表面，其中 地以導電材料填滿 ：槽1，以及 打線連接於—车道亥至V ϋ槽M形成至少-級 於該導電線路之K晶片，▲中該緩衝墊係具有 依申 請專利範圍第22項之半導體晶片封裝基板製造17. The semiconductor method according to item 16 of the scope of patent application 'further includes the following steps: before removing the second shielding layer, forming a and forming a gold layer on the nickel layer. 18 Fa Chengyi applied for the semiconductor crystal of the 15th scope of the patent application, wherein the conductive circuit and the buffer pad are made of the same material as the large package substrate manufacturer 00523. ptc page 20 560024 3 No. 91116215 6. Application scope of the patent 19, according to The method for manufacturing a semiconductor chip package substrate according to item 15 of the patent application, wherein the groove of the far substrate has a depth that is about 1/3 to about 1/5 of the thickness of the substrate. 20. The method of manufacturing a semiconductor wafer package substrate according to item 15 of the patent application, wherein the groove of the substrate has a depth of about 20 mm. 21. The method for manufacturing a semiconductor wafer package substrate according to item 5 of the patent application scope, wherein the groove is formed by mechanical drilling or laser drilling. 2 2. "Kinds of steps: formation to formation and formation of at least one conductive selective pad for the through-hole selective circuit layout for a method for manufacturing a semiconductor wafer package substrate with a large thickness, the method includes the following one less groove in one Dielectric layer; several through holes penetrating the dielectric layer; :: layer covering the entire surface of the dielectric layer, the at least one groove and the metal layer to form an electric spirit on the dielectric layer! The road is located on the upper surface of the dielectric layer, where the ground is filled with conductive material: slot 1, and wire-connected to-lane Hai to V ϋ slot M to form at least-K chip above the conductive line, ▲ the buffer Manufactured with a semiconductor chip package substrate according to item 22 of the scope of patent application 00523.ptc 23 56002400523.ptc 23 560024 法 成 其中該凹槽形成步驟係藉由機械鑽孔或 雷射鑽孔達 24 > 法， 成0 依申請專利範圍第2 2項之半 其中該通孔形成步驟係藉由 導體晶 機械鑽 片封裝基板製造 孔或雷射鑽孔達 方 ：利範圍第22項之半導體晶片封裝基板製造方 擇性填滿步驟包含： 上表面，该選 將一防銲層塗佈於該介電層上表面以及該 上，僅裸露出該至少一凹槽； 电線路表面 藉由電鍵以該導電材料填滿該凹槽；以及 選擇性地除去該防銲層，裸露出部分之該 打線連接於該半導體晶片。 、” 路用以 26、依中請專利範圍第25項之 法，另包含下列步驟： =同時形成一鎳層於該基板上表面 路出之導電線路以及該緩衝塾上；以& 干層稞 利用電鍍形成—金層於鎳層上。 Ϊ : = 2㈣22項之半導體晶片封裝基板製造方 /、 >電線路以及緩衝墊皆由大致相同材料製成。The method of forming the grooves is performed by mechanical drilling or laser drilling up to 24 > method, which is 0 according to half of the 22nd item of the patent application scope, wherein the step of forming the through holes is performed by a conductive crystal mechanical drill Chip package substrate manufacturing hole or laser drilling method: The selective filling step of the semiconductor wafer package substrate manufacturing method of the 22nd item includes: On the upper surface, a solder resist layer is coated on the dielectric layer. Only the at least one groove is exposed on the surface and the surface; the groove is filled with the conductive material by an electric key on the surface of the electrical circuit; and the solder resist is selectively removed, and the exposed portion of the wire is connected to the semiconductor Wafer. ”” For 26. According to the method in the patent application No. 25, it also includes the following steps: = At the same time, a nickel layer is formed on the conductive circuit that is routed on the upper surface of the substrate and the buffer pad; and & dry layer稞 Formed by electroplating—the gold layer is on the nickel layer. Ϊ: = 2㈣22 The semiconductor chip package substrate manufacturer /, > The electrical wiring and the cushion are made of approximately the same material. 00523. ptc 第22頁 560024 _案號91116215_年月日__ 六、申請專利範圍 28、依申請專利範圍第22項之半導體晶片封裝基板製造方 法，其中該該基板之凹槽具有一深度，其為該基板厚度的 約1 / 3到約1 / 5。 2 9、依申請專利範圍第2 2項之半導體晶片封裝基板製造方 法，其中該基板之凹槽具有一深度約為2 0 // m。00523. ptc, page 22, 560024 _Case No. 91116215_ year, month and year__ Six, a method for manufacturing a semiconductor wafer package substrate according to the scope of patent application 28, according to the scope of application for patent 22, wherein the groove of the substrate has a depth, It is about 1/3 to about 1/5 of the thickness of the substrate. 29. The method for manufacturing a semiconductor wafer package substrate according to item 22 of the scope of patent application, wherein the groove of the substrate has a depth of about 20m. 00523. pic 第23頁00523.pic p. 23
TW091116215A 2002-07-18 2002-07-18 Semiconductor package and substrate thereof TW560024B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW091116215A TW560024B (en) 2002-07-18 2002-07-18 Semiconductor package and substrate thereof
US10/394,347 US6770979B2 (en) 2002-07-18 2003-03-24 Semiconductor package and substrate thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091116215A TW560024B (en) 2002-07-18 2002-07-18 Semiconductor package and substrate thereof

Publications (1)

Publication Number Publication Date
TW560024B true TW560024B (en) 2003-11-01

Family

ID=30768943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091116215A TW560024B (en) 2002-07-18 2002-07-18 Semiconductor package and substrate thereof

Country Status (2)

Country Link
US (1) US6770979B2 (en)
TW (1) TW560024B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI393224B (en) * 2009-03-27 2013-04-11 Chipmos Technologies Inc Flip chip package and fabricating method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100423132C (en) * 2006-06-16 2008-10-01 友达光电股份有限公司 Shift register
US8257722B2 (en) 2008-09-15 2012-09-04 Cv Ingenuity Corp. Local delivery of water-soluble or water-insoluble therapeutic agents to the surface of body lumens

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134247A (en) * 1989-02-21 1992-07-28 Cray Research Inc. Reduced capacitance chip carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI393224B (en) * 2009-03-27 2013-04-11 Chipmos Technologies Inc Flip chip package and fabricating method thereof

Also Published As

Publication number Publication date
US20040017007A1 (en) 2004-01-29
US6770979B2 (en) 2004-08-03

Similar Documents

Publication Publication Date Title
US6501168B1 (en) Substrate for an integrated circuit package
TWI293796B (en)
CN106605454B (en) Multi-layer flexible printed circuit board and its manufacturing method
TWI298993B (en) A printed circuit board and its fabrication method
US20080102410A1 (en) Method of manufacturing printed circuit board
JPH11163022A (en) Semiconductor and manufacture of the same and electronic equipment
JPH0936549A (en) Printed board for bare chip mounting use
JP2006287034A (en) Manufacturing method of wiring substrate utilizing electrolytic plating
TWI397358B (en) Wire bonding substrate and fabrication thereof
US7045460B1 (en) Method for fabricating a packaging substrate
US20040124516A1 (en) Circuit device, circuit module, and method for manufacturing circuit device
JP2007335845A (en) Electronic element package printed circuit board and method for manufacturing same
TW560024B (en) Semiconductor package and substrate thereof
US6248612B1 (en) Method for making a substrate for an integrated circuit package
US6896173B2 (en) Method of fabricating circuit substrate
JPH11204699A (en) Semiconductor device, manufacture thereof and electronic apparatus
US7033917B2 (en) Packaging substrate without plating bar and a method of forming the same
KR100780093B1 (en) Manufacturing method for printed circuit board having non-plate pattern
JP2007324568A (en) Manufacturing method of package substrate
JP3770895B2 (en) Manufacturing method of wiring board using electrolytic plating
JP3105437B2 (en) Semiconductor device package and method of manufacturing the same
JP2937111B2 (en) Semiconductor device and manufacturing method thereof
JP2004146757A (en) Wiring board and method for manufacturing the wiring board
CN109041414B (en) Circuit board structure and manufacturing method thereof
CN112533349A (en) Circuit board and manufacturing method thereof

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent