TW552661B - Gettering method of silicon wafer by using very high energy blanket implant - Google Patents

Gettering method of silicon wafer by using very high energy blanket implant Download PDF

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TW552661B
TW552661B TW91117628A TW91117628A TW552661B TW 552661 B TW552661 B TW 552661B TW 91117628 A TW91117628 A TW 91117628A TW 91117628 A TW91117628 A TW 91117628A TW 552661 B TW552661 B TW 552661B
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silicon
wafer
defects
silicon wafer
range
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TW91117628A
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Yu-Cheng Xiao
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Grace Semiconductor Mfg Corp
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Abstract

The present invention provides a gettering method of silicon wafer by using very high energy blanket implant (VHEBI), wherein ions are implanted into the deep layer of silicon wafer with high energy by VHEBI, so that the depth of the surface impurity defects is reduced globally, and the surface impurity defects can diffuse into the damaged region deeper under the silicon wafer surface, thereby effectively reducing the impurity defects and dislocations in the device forming region of the silicon wafer. The present invention utilizes the VHEBI technology to eliminate the surface impurity defects, so as to provide a silicon wafer surface with very low impurity concentration and few dislocations for fabricating integrated circuits on top of it, and to keep good MOS device characteristics and to increase the product yield rate.

Description

552661552661

【發明領域】 本發明係有關一種半導體矽晶圓製程中之去疵方法( getter i ng),特別是關於一種利用高能量全面離子植入法 (Very High Energy Blanket Implant,VHEBI)消除矽曰 / 曰曰 圓表面缺陷的去疵方法。 【發明背景】 按’晶圓加工成形(Μ 〇 d i f i c a t i ο η)指的是將石夕單晶 棒製造成矽晶圓片(Wafer)之製程。晶圓成形製程中所 包含之製造步驟,視不同的晶圓生產廠商而有所增減,主 要係包括有結晶定位(〇rientati〇n)、切片(Slicing) 、晶邊圓磨(Edge Contouring)、晶面研磨(Lapping) 化學餘刻(Etching)、去庇(Gettering),以及各步 驟間所需之潔淨製程(Cleaning)等一連串的處理,最^ 才成成為一片片的晶圓, b也—般以矽晶成長(CZ)法成長之矽晶圓,由於成長的 %境雜質污染及熱應力造成之缺陷均留於晶圓當中,同時 ^續之加工所造成之缺陷亦存於其中,在積體電路製造過 程中’這些缺陷均會影響元件之良率及電性品質,所以必 須去除會造成元件特性不良影響的點缺陷或與其相 陷等。 研 利用晶圓中晶格子缺陷來控制或消除其他缺陷稱之為 疲方法’常見的去疯方法大致可分為三種·· (a)内部去' 疵法(Intrinsic gettering),其係利用CZ長晶過程中 ^飽和氧含篁在熱處理後形成析出物以造成晶格缺陷,在[Field of the Invention] The present invention relates to a method for removing defects (getter i ng) in a semiconductor silicon wafer manufacturing process, and more particularly to a method for eliminating silicon by using a Very High Energy Blanket Implant (VHEBI) method. Defect removal method for round surface defects. [Background of the Invention] According to the ‘wafer processing and forming (M o d i f i c a t i ο η) refers to the process of manufacturing Shi Xi single crystal rods into silicon wafers (Wafer). The manufacturing steps included in the wafer forming process may increase or decrease depending on different wafer manufacturers, and mainly include crystal positioning (〇rientati〇n), slicing (Slicing), and edge contouring (Edge Contouring) , Lapping, chemical etching (Etching), gettering (Gettering), and the cleaning process (Cleaning) required between the steps of a series of processing, the most ^ into a wafer, b also —Since silicon wafers grown by the silicon growth (CZ) method, defects caused by the growing% contamination and thermal stress are all left in the wafer, and defects caused by continuous processing are also stored therein. In the integrated circuit manufacturing process, 'these defects will affect the yield and electrical quality of the device, so the point defects that cause adverse effects on the characteristics of the device must be removed. The research uses crystal lattice defects in the wafer to control or eliminate other defects. It is called a fatigue method. The common methods to go crazy can be divided into three types ... (a) Intrinsic gettering, which uses CZ length During the crystallization process, the saturated oxygen-containing europium forms precipitates after heat treatment to cause lattice defects.

552661 五、發明說明(2) 回火(anneal)過程中,這些缺陷將可提供元件設計區雜 質或金屬等缺陷之吸附(Sink),以消除表面雜質缺 (b)外部去疵法(Extrinsic gettering),其係藉由外在 力量造成晶圓背面受機械應力而形成如差排等各^缺陷來 達成去疵的目的;常見的外部去疵法有機械研磨、喷^或 施以一層多晶矽,但此種方法在機械應力控制上及其‘ 清洗上需仔細處理付當’以免造成晶圓變形或污染。(c )、 化學去疵法(Chemical gettering),此法有別於上述兩 種去疵方法般的提供缺陷的吸附,而是藉由金屬雜質與擴 散之磷離子的化學反應來消除雜質缺陷。 、、 然而,不管為上述何種方法,傳統的去疵方式僅能降 低部份雜質深度’無法全面性的完全降低矽晶圓上的所有 金屬雜質缺陷,使矽晶圓表面仍存有部份雜質缺陷,將使 得製作於該石夕晶圓上的積體電路各元件受到雜質影響而 低元件之良率及電性品質。因此,本發明即在針對上述之 缺失,提出一種利用高能量全面離子植入法之矽晶圓去疵 方法,以有效克服傳統方式之缺失。 [發明目的與概述】 本發明^主要目的係在提供一種矽晶圓去疵方法,i 係利用高能量全面離子植入法(VHEBI)來全面降低雜質、 缺陷之深度:以提供一非常低雜質 '低差排之矽晶圓’ 供積體電路兀件製作於其上,而不會影響元件之特性^電 性品質。 本發明之另一目的係在提供一猶刹用 ^ ^ 禋刊用鬲能量全面離子552661 V. Description of the invention (2) During the annealing process, these defects will provide the adsorption of impurities or metal defects in the design area of the component (Sink) to eliminate the lack of surface impurities. (B) Extrinsic gettering ), Which is achieved by external forces caused by mechanical stress on the back of the wafer to form defects such as differential rows to achieve the purpose of removal; common external removal methods include mechanical grinding, spraying or applying a layer of polycrystalline silicon, However, this method requires careful handling of mechanical stress control and cleaning, so as not to cause wafer deformation or contamination. (C) Chemical gettering. This method is different from the above two methods to provide defect adsorption. Instead, it removes impurity defects through a chemical reaction between metal impurities and diffused phosphorus ions. However, no matter which method is used above, the traditional defect removal method can only reduce the depth of some impurities. 'All metal impurity defects on the silicon wafer cannot be completely reduced, so that there is still a part on the surface of the silicon wafer. Impurity defects will cause the components of the integrated circuit fabricated on the Shixi wafer to be affected by impurities and lower the component yield and electrical quality. Therefore, the present invention proposes a silicon wafer defect removal method using a high-energy comprehensive ion implantation method in order to effectively overcome the shortcomings of the conventional method. [Objective and Summary of the Invention] The main purpose of the present invention is to provide a method for removing defects on silicon wafers. The system i uses high-energy comprehensive ion implantation (VHEBI) to comprehensively reduce the depth of impurities and defects: to provide a very low impurity The 'low-difference silicon wafer' is used to fabricate integrated circuit components without affecting the characteristics and electrical quality of the device. Another object of the present invention is to provide a full energy ion for use in ^ ^

552661 五、發明說明(3) 植入法之矽晶圓去疵方法,其係可有效降低矽晶圓表面之 差排(dislocation)及點缺陷、線缺陷、面缺陷與體缺 陷等之雜質缺陷,以藉此增加產品良率。 本發明之再一目的係在提供一種利用高能量全面離子 植入法之矽晶圓去疵方法,其係可保持良好的金屬氧化半 導體(M0S)元件特性以及較佳之閘極氧化層的完整性 (Gate Oxide Integrity, G0I) 〇 為達到上述之目的,本發明係在一表面具有雜質缺陷 之半導體矽晶圓上進行去疵處理,其主要係利用高能量全 面離子植入技術,將離子以高能量打入矽晶圓中,使表面 雜質缺陷係全面性的降低深度而擴散至矽晶圓表面下方較 深之受損區域,進而使矽晶圓表面的元件形成區域無缺陷 化,以利於元件製作。 底下藉由具體實施例配合所附的圖式詳加說明,當更 容易瞭解本發明之目的、技術内容、特點及其所達成之功 效。 【圖號簡單說明】 10 矽晶圓 12 雜質缺陷 14 元件形成區域 16 受損區域 【詳細說明】 本發明係利用高能量全面離子植入法(VHEBI)來去除 矽晶圓表面會造成元件特性不良影響的雜質、重金屬,或552661 V. Description of the invention (3) Silicon wafer defect removal method of implantation method, which can effectively reduce the dislocation of silicon wafer surface (dislocation) and impurity defects such as point defects, line defects, surface defects and body defects. To increase product yield. Another object of the present invention is to provide a silicon wafer defect removal method using a high-energy full ion implantation method, which can maintain good metal oxide semiconductor (MOS) device characteristics and better integrity of the gate oxide layer. (Gate Oxide Integrity, G0I) 〇 In order to achieve the above purpose, the present invention is a semiconductor silicon wafer with impurity defects on the surface of the defect removal process, which mainly uses high-energy comprehensive ion implantation technology, The energy is injected into the silicon wafer, so that the surface impurity defects are comprehensively reduced in depth and diffused to the deep damaged area below the silicon wafer surface, thereby making the component formation area on the silicon wafer surface defect-free, which is beneficial to the component Production. In the following, detailed descriptions will be made with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features and functions of the present invention. [Simplified description of drawing number] 10 Silicon wafer 12 Impurity defect 14 Element formation area 16 Damaged area [Detailed description] The present invention uses high-energy full ion implantation (VHEBI) to remove the surface of the silicon wafer, which will cause poor device characteristics. Affected impurities, heavy metals, or

第6頁 552661 五、發明說明(4) 嫌 "一''一" ---- 去除和缺陷相關之點缺陷等,以藉此去疵 方法將矽晶圓表面的元件形成區域加以 ’以提升7L件特性及元件製造之產品良率 所、在半導體晶圓成形製程中,由於單晶 = >可染及熱應力造成之缺陷均留於矽晶圓曰 績之加工所造成之雜質缺陷1 2亦存於其中 ,尤其是位於在矽晶圓1 0表面之元件形成 |缺陷12,常會影響半導體中載體(Carri( 響元件之良率及電性品質,因此,為維持 晶、化學與電性等行為與其内層材料之一 在石夕晶圓1 0表面進行去疵處理。 本發明係在一内含有雜質缺陷丨2之石夕 行去疵處理,如第二A圖所示,利用超高食 入(VHEBI)技術,將磷(p)或氣(C1) $高能量進行較深層植入至矽晶圓丨〇内, 深愈佳,參考植入深度係係大於2〇微米( 、金、銅、鎳及鐵等之雜質缺陷1 2係全面 擴政至石夕晶圓1 〇表面下方較深之受損區域 !、6 ’如第二B圖所示,進而使矽晶圓丨〇表f 域1 4無缺陷化,換言之,在距離該石夕晶圓 2〜4微米深度處的元件形成區域丨4將具有 差排之特性,且有利於在該矽晶圓丨〇表面 各元件之後續半導體製程。 其中,上述之高能量全面離子植入法 (gettering) 淨化或無缺陷化 〇 矽成長的環境雜 1 0當中,同時後 ’如第一圖所示 區域14内的雜質 )r)之行為而影 碎晶圓1 0表面結 致性,所以必須 晶圓1 0上直接進 色量全面離子植 離子以MeV以上 且植入之深度愈 V m),使碳、氧 性的降低深度而 (damage area) δ的元件形成區 1 0表面邊界約為 低雜質缺陷、低 上製作積體電路 係可自該矽晶圓 552661 五、發明說明(5) 線子植入:以較適用於目前現存的生產 defect)、:缺陷日日T之缺陷係T為點缺陷(P〇int defect)赤 β 掷(Une defeCt)、面缺陷(area 晶格植s疋體缺陷(volume defect)等,不管為仃插 陷,利用本發明之技 二為何種 之70件形成區域内的张女从价·,啕肩除矽日曰回表面 高之雜質缺陷或差排有、卩曰,而受損區域雖然會存有較 ,所以完全不會對;表=其:於石夕晶圓較為深層之地方 因此,本發明之砂件形成區域產生任何影響。 ^ ^ ^ ^ ^ ( M〇S)\V^ ^ ^ ^ 1 Νι 入法(VHEBI)來全面降罢以利用咼旎1全面離子植 以提供-非常低雜質:/排排之'雜質缺陷之深度’故可 件製作於i μ 二 低差排之♦晶圓表面供積體電路元 藉此增加產品良率不:^響:件之特性”性品質,進而 入法之矽晶圓去疵方法:發明利用高能量全面離子植 體元件特性,t 1 ά不旦可以保持良好的金屬氧化半導 〇Xm 有較佳之間極氧化層的完整性(G“e uxide lntegrity,(j〇i)。 以上所述之實施例僅在& 點,其目的在使熟習此項明本發明之技術思想及特 容並據以實施,當不能人士能夠瞭解本發明之内 凡依本發明所揭示之疋本發明之專利範圍,即大 蓋在本發明之專利範圍β乍之均等變化或修飾,仍應涵Page 6 552661 V. Description of the invention (4) Suspected "quota" "" ----- remove point defects related to defects, etc., and use this method to remove the component formation area on the surface of the silicon wafer ' In order to improve the characteristics of 7L components and the yield of components, in the semiconductor wafer forming process, defects due to single crystal = > dyeable and thermal stress are left in the impurities caused by the processing of silicon wafers. Defect 12 also exists, especially the formation of components on the surface of silicon wafer 10 | Defect 12, often affects the carrier (Carri (the yield and electrical quality of components) in semiconductors, so in order to maintain crystal, chemical One of the behaviors such as electrical properties and its inner layer material is subjected to a defect removal process on the surface of Shixi wafer 10. The present invention is a defect removal process of Shixi line which contains impurity defects in it, as shown in Figure 2A. Using VHEBI technology, deep implantation of phosphorus (p) or gas (C1) $ high energy into silicon wafers, the deeper the better, the reference implantation depth is greater than 20 microns (Impurity defects of gold, copper, nickel and iron, etc. 1 2 The full expansion of the administration to Shi Xi Circle 1 〇 deeper damaged area below the surface !, 6 ′ as shown in the second figure B, and further make the silicon wafer 丨 surface f 14 free of defects, in other words, from the Shixi wafer 2 ~ The element formation area at a depth of 4 micrometers will have the characteristics of differential rows, which will facilitate the subsequent semiconductor process of each element on the surface of the silicon wafer. Among them, the above-mentioned high-energy comprehensive ion implantation (gettering) purification Or defect-free. The silicon growth environment is mixed with 10, and at the same time, the behavior of the impurities in the region 14 as shown in the first figure) r) will affect the surface consistency of the wafer 10, so the wafer 1 must be The direct color input on 0 is full ion implantation ions (above MeV and the depth of implantation is more V m), which reduces the depth of carbon and oxygen, and (damage area) δ element formation area 1 0 surface boundary is about low impurity defects The integrated circuit can be fabricated from the silicon wafer 552661. 5. Description of the invention (5) Wire implantation: It is more suitable for the existing production defect.): The defect day T is the defect point T. (P〇int defect) Une defeCt, area defect (area lattice) s volume defects, etc., regardless of cutting, the use of the second method of the present invention for the formation of 70 pieces of the adjoint woman in the area, the shoulders to remove silicon defects and high impurities on the surface or There is a difference between the two rows, but the damaged area will not exist at all, although there is a comparison; Table = its: in the deeper part of the Shixi wafer. Therefore, the sand piece forming area of the present invention has any impact. ^ ^ ^ ^ ^ (M〇S) \ V ^ ^ ^ ^ 1 Νι entry method (VHEBI) to fully reduce the use of 咼 旎 1 full ion implantation to provide-very low impurity: / the depth of the impurity defect 'Therefore, it can be made on the second low-difference row of i μ. ♦ Wafer surface for integrated circuit elements to increase the product yield rate: ^ Response: the characteristics of the piece ”quality, and then the method of silicon wafer defect removal : The invention utilizes the characteristics of high-energy comprehensive ion implant elements, t 1 can maintain good metal oxide semiconducting OXm with better integrity of the polar oxide layer (G "e uxide lntegrity, (j〇i). The above-mentioned embodiments are only at the & point, the purpose of which is to familiarize themselves with the technical ideas and features of the present invention and implement them accordingly. When those who cannot understand the contents of the present invention disclosed in accordance with the present invention, The patent scope of the present invention, that is, the equivalent changes or modifications that cover the patent scope of the present invention, should still be covered.

552661 圖式簡單說明 第一圖為石夕晶圓未經去疫處理之示意圖。 第二A圖為本發明在進行高能量全面離子植入之矽晶圓示 意圖。 第二B圖為本發明已完成去疵處理後之矽晶圓示意圖。552661 Brief description of the diagram The first diagram is a schematic diagram of Shixi wafer without deepidemic treatment. The second diagram A is a schematic view of a silicon wafer performing high-energy full ion implantation according to the present invention. The second diagram B is a schematic view of the silicon wafer after the defect removal process according to the present invention has been completed.

第9頁Page 9

Claims (1)

552661 六、申請專利範圍 1 · 一種利用 包括下列 先提供一 缺陷; 利用高能 晶圓中 至碎晶 圓表面 2 ·如申請專 ,該植入 3 ·如申請專 ’該碎晶 4 ·如申請專 ,該離子 5 ·如申請專 ,該雜質 6 ·如申請專 ,該缺陷 7 ·如申請專 ,在該矽 碎晶圓表 離子植入法之碎晶圓去庇方法, 圓,在該矽晶圓表面係存有雜質 南能量全面 步驟: 半導體碎晶 以及 量全面離子 ,使該雜質 圓表面下方 的元件形成 利範圍第1 之離子為磷 利範圍第1 圓表面之深 利範圍第1 植入深度係 利範圍第1 係為碳、氧 利範圍第1 係為點缺陷 利範圍第1 晶圓表面去 面上製作積 植入法,將 缺陷係全面 較深之受損 區域無缺陷 項所述之矽 或氣離子。 項所述之矽 度係介於2-項所述之矽 大於2 0微米 項所述之矽 、金、銅、 項所述之矽 、線缺陷、 項所述之矽 除雜質缺陷 體電路各元 離子以高能量植入矽 性的降低深度而擴散 區域,進而使該石夕晶 化。 晶圓去庇方法’其中 晶圓去庇方法,其中 “ 4微米之間。 晶圓去疯方法’其中 〇 晶圓去疲方法,其中 鎳及鐵等。 晶圓去疵方法,其中 面缺陷或體缺陷者。 晶圓去疵方法,其中 之步驟後,即可在該 件之後續半導體製程 8 ·如申請專利範圍第1項所述之矽晶圓去疵方法,其中 ,該高能量全面離子植入法係可自該矽晶圓之背面進552661 VI. Application for patent scope 1 · One use includes the following to provide a defect first; Use of high-energy wafers to break the wafer surface 2 · If applying for the special, the implantation 3 · If applying for the special 'The broken crystal 4 · If applying for the special The ion 5 · If you apply for special, the impurity 6 · If you apply for special, the defect 7 · If you apply for special, in the silicon chip wafer surface ion implantation method of the broken wafer shelter method, round, in the silicon crystal The round surface is full of impurities. The whole process of semiconductor energy and semiconductor ions is to make the element below the round surface of the impurity. The first ion is the phosphorus range. The first round surface is the deep range. The depth range is the first range of carbon and oxygen range. The first range is the point defect range. The wafer surface is made by the implantation method. The defects are comprehensive and deep in the damaged area. Silicon or gas ions. The degree of silicon described in item 2 is between 2 and more than 20 microns in silicon, gold, copper, silicon described in item, wire defects, and silicon impurity removal circuits described in item 2. Elemental ions are implanted into the silicon with a reduced depth and diffuse into the region with high energy, thereby crystallizing the stone. Wafer removal method 'Where the wafer removal method, which is "between 4 micrometers. Wafer removal method" where 0 Wafer removal method, which includes nickel and iron, etc. Wafer removal method, where surface defects or Defective wafer method. After the steps, one of the steps can be used in the subsequent semiconductor process of the piece. • The silicon wafer defect removing method as described in the first patent application scope, wherein the high-energy comprehensive ion The implantation method can be accessed from the back of the silicon wafer. 第10頁 552661 六、申請專利範圍 行高能量離子植入。 9 ·如申請專利範圍第1項所述之矽晶圓去疵方法,其中 ,該矽晶圓去疵方法係應用在金屬氧化半導體(MOS) 之製程中。Page 10 552661 6. Scope of patent application High-energy ion implantation. 9 · The method for removing silicon wafers as described in item 1 of the scope of patent application, wherein the method for removing silicon wafers is applied in the process of metal oxide semiconductor (MOS). 第11頁Page 11
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