TW550800B - Integrated circuit package without solder mask and method for the same - Google Patents
Integrated circuit package without solder mask and method for the same Download PDFInfo
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- TW550800B TW550800B TW091111221A TW91111221A TW550800B TW 550800 B TW550800 B TW 550800B TW 091111221 A TW091111221 A TW 091111221A TW 91111221 A TW91111221 A TW 91111221A TW 550800 B TW550800 B TW 550800B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2081—Compound repelling a metal, e.g. solder
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0315—Oxidising metal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
乃 0800 、發明說明(1) 〜1發明領域 ,特t ^係有關於一種構裝積體電路之結構>5 , 方:L有關於一種不具防銲膜之積體電路 路的可靠度。 電路積集度與構裝積體電 5一2發明背景: 積 四邊扁 結構包 片(Ch 絕緣之 在 術,已 良方法 以百萬 的空間 體電路一般需 平構裝(Quad 含一引腳架, lp )的引線。 堅固塑膠内, 過去,積體電 企圖滿足微小 ’是使其能夠 計的電晶體電 中構裝電路元 要木構於構裝材料之 Fiat Pq , 例如傳統的
Hat package,QFp )。平土曰 在引腳架上有畔多接網认一的構衣 曰Μ姑m壯:觸於積體電路晶 =片:構衣在一有機械支撐及與 而引線主要是焊接在印刷電路板上。 路廠商所發展出來的積體電路構裝技 化的要求。對於微小化的積體電路改 在矽底材上結合包含電路、晶片等數 :::。這些改良的方法導致在有限 件的方法更受到重視。 二,電路藉由一矽晶 及切割等技術,右择触+ j軸刻、摻雜、沈積 在積體電路設備中製造出來。一矽晶圓至
第5頁 inn 550800 五、發明說明(2) —_ 少包含一積體電路晶片,每一晶片代 。 。最後,此晶片可藉由包圍在晶片四周的電路 來,且有多樣化的針腳露出和互相連接 ^吴〃、構裝起 供一相當平坦構裝的M型雙列直插式構例如·提 Line-Package ; M-Dip),其有兩列平 ^ j Dual —In — 孔中,伸出來,接觸並固定於在下面的底部穿, m度積體電路的印刷電路板為單列式構裝:卞。谷
Single-In-Line-Package ; SIP)和小外创 城且
Outline J-leaded ;S0J) ,J:為採用广 卩構裝(SmaU ’ /、馮抹用模型的構裝。 依照構裝中組合的積體電路晶片 的種類大致可分為單晶片構裝(Sing C體電路 曰曰片構衣也包括多晶片模組構裝(M 員夕
)。若依照元件與電路板的接合 lp odule; MCM 分為引腳插入型(Pln_Through_H:e構=電路可區 (Surface Mount TechnQl ’ H)人表面黏著型 元件的引腳為細針狀或是薄:狀=
Socket)或電路板的導孔(Via)中進行銲 。^ 著型的元件則先黏貼於電路彳' 疋。表面黏 日it所接用夕e 土、# 板後再以銲接的方式固定。 目別所抓用之較先進的構裝技
Chip Attach; DCA )構梦,L7政把二片直接黏結(Dlrect 大小,並增加構裝積】J路内::低構裝積體電路之體積的 接黏結的技術為直接將積體路^ =積集度。晶片直 W餸冤路的晶片(Integrated 第6頁 550800 五、發明說明(3) 再進行電路的
Circuit Chip)固定至基板(substrate)上 連結。 參照第一圖所示,此為傳統使用防 基板上之示意圖。首先提供一基板10及一晶曰片::: 基板1 0上包含已佈局好的多數個電路 ^ 銲接墊(solder Pad)2。、防銲膜3。、:25 弟-
PreS〇ldering)1S(可依需要省略 ;千口 ( =固第二銲接墊45與多數個銲接 言多 上。接下來晶片一 =於耀 Η上之多數個第一輝接 平連接於基板 固定於基板10上,其中、十十口18上,以將晶片40 一第一銲接墊20。 、干接凸塊1 5的位置均對應於任 構裝積體電 上的連線電 程中,因銲 在傳統包含 设盍在分佈 之電路25。 W分分佈於 凸塊1 5在後 銲膜必須覆 路結構中 路導線2 5 接凸塊1 5 防鲜膜的 於基板上 為了提供 基板1 0上 續之製程 蓋在部分 ’使用防 受到外來 的溢流而 構裝積體 之電路25 較佳之保 的任一第一銲接墊2 0 中因溢流 分佈於基 在傳統的 為避免基板1 〇 並防止後續製 的短路。因此 防銲膜3 0必須 佈在基板1 〇上 膜3 0更須覆蓋 ,以避免銲接 缺陷。由於防 輝膜3 0的目的 環境的侵害, 造成電路之間 電路結構中, 上,以保護分 護功能,防銲 而造成短路之 板1 0上的任— 第7頁 550800 五、發明說明(4) 第一銲接墊20上,因舳 έ士槎士 斤 此在傳統使用防銲膣的姓趾 …構中,弟一銲接墊20的 、的構裝積體電路 足夠對位誤差容許之f 要預遠頜外的邊界以便有 u >卜 口τ <見度來承載銲接凸姊,1门 上之弟一銲接墊20與第一銲接墊2〇之所处士因此在基板 目將會變少。此現象將造成使用防俨=谷許導線的數 構的體積無法縮小, ,干、之構裝積體電路結 積越來越小的需i。使此技術無法適用於積體電路之體 使用防銲膜 部分之任一第一 一銲接墊上時, 裝積體電路的品 將無法徹底充填 短路的缺陷。當 混合物(Molding 時’或所代替的 防銲膜因結合力 及與基板上之電 膜必須覆蓋在 凸塊連接至第 問題而影響構 路時,防銲膜 電路容易發生 覆蓋的灌膠模 ip Chip; FC) 蓋於電路上的 的構裝可靠性 的構裝積體電路,由於防輝 銲接墊上,因此也會在銲接 發生銲接凸塊定位不準的的 貝。而且當基板有多層之電 至所需充填的位置,而導致 使用的構裝形式為沒有全部 Compound)的覆晶接合(F1 覆晶填充(Underf i 1 1 )與覆 較弱將容易剝落而導致較差 路容易發生短路之缺陷。 5〜3發明目的及概述: 雲於上述之發明背景中,傳統使用防銲膜的構裝積體 〃路無法順利縮小構裝積體電路之體積,並容易發生防銲 第8頁 i 550800 —-—— 五、發明說明(5) 明、括二王俣盍或是防銲膜剝落而導致電敗戈 ^ ^ (、了 一項不具防銲膜之積體電路错壯產生短路,本發 用具銲接沾附性(Solder Wetteh . 1 .羞結構及其方法, 一銲接墊之材質,並在作為電路的之金屬,作為第 形,一不具銲接沾附性之絕緣層,以f f的表面及側表面 構裝積體電路發生短路之缺陷。9 免未包含防銲膜之 本發明的第二個目的為利用呈 為第-銲接墊之材質,並在金工:沾附性之金屬,作 =接沾附性之絕緣[以提;表面形成一 的電路積集度。 衣積體電路在基板上 本發明的第三個目的為利用呈 為第一銲接墊之材質,並在金屬層^而附性之金屬,作 不具銲接沾附性之絕緣層;表面形成一 。 愒衣積體電路的可靠度 本發明的第四個目的為利用具銲 為第一銲接墊之材質,並在金屬層 /寸性之金屬,作 不具銲接沾附性之絕緣層,以提i構裝:::表面形成-yield)。 積體電路的良率( 本發明的第五個目的為条丨I田目 為第一銲接墊之材質,並在金声占附性之金屬,作 至屬層的表面及側表 55〇8〇〇 五、發明說明(6) =^接沾附性之絕緣層,縮減製程以提高構裝積體電路 的生產效率。 士發明的再一個目的為利用具銲接沾附性之金屬,作 一銲接墊之材質,並在金屬層的表面及侧表面形成一 本/。、鋅接沾附性之絕緣層,以降低構裝積體電路的生產成 膜之:上所述之目的,本發明提供了-項未使用防録 路構裝結構及其方法’利用具銲接沾附性之金 形成:ί =接墊之材質,並在金屬層的表面及側表面 膜之構h =附性之絕緣層,以避免未完全覆蓋防銲 上形成二。首先提供一基板並在此基板 。接;來;此:屬:::::大部分採用銅( 定義第-鮮接墊的位置並在;顯影製程,開口 形成一第一光阻層。 弟鲜接墊部分之金屬層上 J屬層:原金屬i上並移除第形成-第:銲接墊 為具銲接沾附性之金屬:、 运#中此第-銲接 以物理/化學沉積的方式 。電:/化學電鍍的方式或是 二光阻層以移除部分之屬。,妾下來在金屬層上形成第 ,之後並移除第二光阻層形成所需之導電線路圖案 :J :銲接墊及導電心圖Ϊ ? : if成多數個銲接界面 接墊與導電線路圖案用來作:任—銲接界面第一銲 一^^^ ,,、、土扳表面之電路。最後在金 苐〗0頁 550800 五、發明說明(7) 側表面形成一不具銲接沾附性之絕❹ 的製作程序。藉由多數個預焊平:連 ;j表面之電路 與多數個第二銲接墊的個銲接凸塊 靖加熱連接至多數個預焊;鲜接凸塊 ,、以使晶片直接固定於基板上。‘後墊上 裝灌膠模混合物(M l 覆盍一層構
Underflll)方式C〇mP〇Und)或植人覆晶填充( 几成未包含防銲膜之構裝積體 t路/、日日片,即可 製程與結構可提高構裝積體電路在芙衣壬。利用本發明之 並增加構裝積體電路路反上的電路積集度, 也可提高構裝積體電路μ率盘^之製程與結構 。利用本發明之製 構袁積體電路的效率 成本。 /、、、,σ構更可降低構裝積體電路的生產 明: 5〜4發明的詳細說 細描ί:明的一些實施例會詳細描述如下。缺而,广 i發明的範圍不受實施例的:定也在施行,且 牟。 八以之後的專利範圍為 本:明提供了-種不需使用防鲜膜之積截電路構裝si 1 … 第11頁 550800 五、發明說明(8) 構與形成方法,利用具銲接让卩 夕从所, , 接/占附性之金屬作為第一銲接墊 之材貝,亚在非第一銲接墊金屬展 不具銲接沾附性之絕緣層,以面及側表面形成-電路發生短路。參昭第:^避免不具防鲜膜之構裝積體 今厪思 Ϊ 一圖所不,此為在基板上表面形成 • L ^ .丄々,, 口丨、、求路結構非本發明之重點因 略。本發明首先必須提供—基板1〇〇並在基板上形 五屬層110。此金屬層110可依產口 所、s a , 1 u」依產口口之需未採用不同之材 貝。通“匕金屬層110所採用的材質為銅。參照第三圖所 =,此為在部分金屬層上形成第一光阻層120之示意圖。 虽此金屬層110上以第-光阻層12〇開口定義所欲在基板 1 0 0上开> 成之第一銲接墊的位置。 芩第四圖所示,此為在任一開口底部1 2 2形成一第 t接墊於金屬層上之示意圖。參照第五圖所示,此為移 除第一光阻層並在部分之金屬層上形成第一銲接墊130之 示意圖。當藉由第一光阻層120在金屬層110上形成多數個 開口 1 22之後,隨即在任一開口丨22之底部形成一第一銲接 塾130於金屬層上110並移除第一光阻層12〇。此第一鲜接 塾=0用以連接後續製程中的第一銲接凸塊,以使晶片能 固定於基板之上。此第一銲接墊丨3 0為一具有較佳銲接沾 附性(Solder Wettability)的金屬材質。此第一銲接墊 1 3 0之厚度可隨產品及製程需求之不同而改變。而第一輝 接塾130的寬度可隨產品及製程需求之不同而改變。任= 第一鋒接墊1 3 0之間的寬度可隨產品及製程需求之不同而
^50800
-ί接2 :右$ 接墊13°為用來連接後續製程中的第 1 30通常以電氣^化::能固定於基板100上,第-銲接墊 成。 〃子電鍍方法或是物理/化學沉積方法形 參照第六圖所示,此為在部分 層140之千音岡 ^ ^ . 土板上幵/成弟一光胆 J夂: 除第一光阻層12〇後,隨即在部分之 SΗ Λ成—第二^阻層14G。&第二光阻層⑷的目之 的為用來佈局基板1⑽±之電路 移除部分之金屬声 一、,、弟七圖所不,此為
a 〃屬s之不忍圖。當在部分的金屬層上形成第 :阻層140之後,隨即移除部分之 一光阻層丨4〇(參照第八圖所示),以在基板上形成 個金屬線路層llGa與多數個銲接界面16(),其中任 界:⑽包含金屬層110b與第,墊13。。、當移除第二妾光 阻層140之後,殘留在基板1〇〇上之多數個金屬層n〇a即為 所A在基板1 〇 〇上所形成之導電線路。在移除部分金屬層 110之過程中,在銲接界面16〇内且在第一銲接墊13〇下方 的=屬層11 〇 b因為有第一銲接墊丨3 〇之保護,因此即使未
在第鲜接墊130上方形成第二光阻層140,在銲接界面内 的金屬層IlOb也不會被移除。 、參照第九圖所示,此為在金屬層之表面上形成一銲接 沾附性絕緣層之示意圖。當在部分之基板丨〇 〇上形成多數 個金屬層11 〇 a與多數個銲接界面後丨6 〇,隨即在金屬層之
第13頁 550800
表面及側表面上形成一銲接沾附性絕緣層丨丨2。此絕緣層 11 2之材質為一不具銲接沾附性之金屬,其的主要的目二 為防1^後續製程中,因為第一銲接凸塊的溢流而導致不 具防紅膜之構裝積體電路發生短路。通常將基板1〇〇進行 =化處S,以在金屬層之表面及侧表面上形成—金屬氧 、層作為絕緣層1 1 2。絕緣層1 1 2的厚度隨著製程與產品 品求之不同而改變。 當在金屬層之表面形成一絕緣層之後’隨即可在基板 、、面上覆蓋一層離形膜(Rel6ase Film)(未於圖中栌 斤、:止基板在運送至後續製程之過程中遭受外部環境 所>可染或表面刮傷。當基板被運送至下一道製程時,= 胰可輕易地被剝離基板的表面。在^ 步驟。二;=所基板隨即可進行下-階段之構裝製程 。-基板m二晶片連接至基板上之示意圖 1〇〇相互連後,隨即可將晶片3⑽與基板 ^ ^ - ^ ^,;320 Λ /Λ'" V ^310 " " 於任-第-銲接凸塊32()ι:=:;ί銲接墊31Q均對應 止晶片在加熱黏結的過程中/〜一保護層,以防 塊320可藉由加熱之ϋ中/到抽毀。多數個第一鮮接凸 接墊130(第—銲接墊)"妾至基板100上之多數個第一銲 -第-焊接凸=二;將易=。㈣ 之第一銲接墊130。由;易對應任一作為第一銲接墊 要墊130由於本發明中並未使用防銲膜而且在 550800 五、發明說明(11) 第-銲接凸塊32 0連接至第一銲接墊13〇的過程 定位=問題,因此本發明可增加積體電路之製程運;效率 ,亚降低生產構裝積體電路所需要之成本。將晶片固 基板上僅為利用本發明之一稽每 , 夕r η 士八叫四 種貝施利,但並不限制本發明 之耗圍。本發明逛可利用在銲接界面上的第一銲_ :導線而連接至其他之電路元件。當晶片3。 曰 100上後,隨即可將晶片30 0及基曰 、土板 裝灌勝模混合物(Package 片的接合處採用構 ,或疋復日日填充物(Underflll)構裝方式固定,並 底β形成緊密填充(參照第十一圖所示)以保 7 ^ 響而降低其運作之效能,並二中;V人又到外界環境的影 電路的製,呈。在基板底部可藉由多 :=f衣積體 多數個第二銲接凸塊510相連接,以使未勺一入干墊5 0 0與 3體電路可再連接其他元件,其中第三匕鲜3方== 為=球墊(Ball Pad)而第二輝接凸塊5 〇 =吊
Solder Ball )。參照第十—圖所示, 吊為广球( 結之多數個第二銲接凸塊510僅為本發明u底部相連 限制本發明之權利範圍。利用本發明所f作之\列而不 的構裝積體電路,仍可採用其他 ^ 不”防輝膜 上。 稱衣形式連接至其他元件 本發明中由於未使用防銲膜,因此第— 不需要額外的邊界,且任兩第一銲接墊之間;佈 第15頁 550800 五、發明說明(12) $ ^ &此現象可使未包含防銲膜之構裝積體電路之體積順 二Τ包含較多之電路,以提高縮小體積後之構裝 積體電路的效能’並可以提高構裝積體電路的穩定度。 未估Γ上Γ述’根據以上所述之目的,本發明提供了 —項 二:防銲朕之積體電路構裝 及其方法接 屬為第一鋒接塾之材質,並在金屬層的表面ί 銲膜之構牡浐::銲接沾附性之絕緣層’以避免未包含防 短路。首先提供一基板並在此基 在Si全^ ί;ί金屬層上定義第一鲜接塾的位置】 包含A上=^::阻:;其中第-光阻層内 成-第-銲接墊於金屬層上並移:=:m形 -銲接墊為具銲接沾附性 :、5F層,其中此第 式或是以物理/化與…社AA屬以電虱/化學電鍍的方 屬層上形成第-光于阻^貝、方式形成。接下來在部分之金 光阻層以分之金屬層,並移除第二 其中任一銲接界^入:數個鈈接界面及多數個金屬層, 屬層用來作為基板::::接金屬層且此多數個金 ,成-不具銲==:絕=在以:;:及側 接凸塊連接到多數個第序;:由多數個銲 個•接凸塊加熱連接至多數::的一塾:直=以 550800 五、發明說明(13) 接固定於基板上。 物或植入覆晶填充 成之電路與晶片, 之製程。利用本發 基板上的電路積集 用本發明之製程輿 產構裝積體電路的 低構裝積體電路的 為鈾所未見之設計 合專利法之要件, 委員詳予審查,並 最後在基板上覆蓋一層 (Underfill)方式,以 即可完成未包含防銲膜 明之製程與結構可提高 度,並增加構裝積體電 結構也可提高構裝積體 效率。利用本發明之製 生產成本,不僅具有實 ,具有功效性與進步性 爰依法具文申請之。為 祈早日賜准專利,至感 構裝灌 保護基 之構裝 構裝積 路的可 電路的 程與結 用功效 之增進 此,謹 德便。 膠模混合 板上所形 積體電路 體電路在 靠度。利 良率與生 構更可降 外,並且 ,故已符 貴 審查 ♦ 定本:ΐΐΐϊ土ί發明之較佳實施例而已,並非用以限 精神;; &其它未脫離本發明所揭示之 專利;Ξ:成之4效改變或修飾’均應包含在下述之申請
550800 圖式簡單說明 圖示的簡單說明: 以上及其餘有關於本發明的目的、特性及優點在發明 的詳細說明及附圖中可得到更完整的說明。 第一圖為傳統使用防銲膜將晶片固定於基板上之示意 圖, 第二圖為在基板上形成金屬層之示意圖; 第三圖為在部分金屬層上形成第一光阻層之示意圖; 第四圖為在任一渠溝之底部形成一第一銲接墊於金屬 層上之示意圖; 第五圖為移除第一先阻層並在部分之金屬層上形成第 一銲接墊之示意圖; 第六圖為在部分之金屬層上形成一第二光阻層之示意 圖; 第七圖為移除部分之金屬層之示意圖; 第八圖為移除第二光阻層以在基板上形成多數個金屬
第18頁 550800 圖式簡單說明 層與多數個銲接界面之示意圖; 第九圖為在金屬層之表面上形成一絕緣層之示意圖; 第十圖為晶片連接至基板上之示意圖;及 弟十一圖為在晶片與基板上形成構裝模具並在基板底 部連結多數個第二銲接凸塊之示意圖。 主要部份的代表符號: 1 〇基板 1 5銲接凸塊 1 8預銲平台 20第一銲接墊 2 5電路導線 3 0防銲膜 40晶片 45第二銲接墊 I 0 0基板 II 0金屬層 11 0 a金屬層 1 1 Ob金屬層 1 1 2絕緣層 1 2 0第一光阻層
第19頁 550800 圖式簡單說明 1 2 2 開口 1 3 0第一銲接墊 1 4 0第二光阻層 1 6 0銲接界面 3 0 0晶片
3 1 0第二銲接墊 3 2 0第一銲接凸塊 40 0構裝灌膠模混合物 5 0 0第三鲜接塾 5 1 0第二銲接凸塊
第20頁
Claims (1)
- 申請專利範圍 Λ θ 修正 6·如申請專利範圍第5項 構,更包含多數個第二#之不具防銲膜之積體電路構裝結 銲接凸塊相互連結。一綷接墊藉以將上述之晶片與多數個 7·如申請專利範圍第6項 構,其中上述之任一#拉不一防薛膜之積體電路構裝結 墊。 ^凸塊均對應至任一該第二銲接 8 ·如申請專利範圍第6項 “ 構,其中上述之多數個r 一防銲膜之積體電路構裝結 互連接而將該晶= = = :該多數個第-薛接塾相 9 ·如申請專利範圍第8項之π θ ^ λ 構,其中上述之任一鮮接^積體電路構裝結 墊。 接凸塊均對應至任一該第一銲接 二如/Λ气利範圍第1項之不具防銲膜之積體電路構〜 構,中上述之不具銲接沾附性絕緣層可衣π 層。 至屬氧化 11 ·如申請專利範圍第5項之不具防銲膜之積體 構,其中上述之晶片及該基板與該晶片的接合产構裝結 膠模混合物(Μ ο 1 d i n g C 〇 m ρ 〇 u n d)構裝方式固定 系採用灌 第22頁 550800 案號9ΙΠ@ϊ 六、申請專利範圍 Θ 修正 1 2 ·如申請專利範圍第& 構,其令上述之晶片及該基板二路構裝結 晶填充(Underfil〗)構裝方式固定^ sa片的接合處係採用覆 1 3 · —種形成不具防 方法包含: ,之構裝積體電 提供一基板; 形成一金屬層於該基板上; 形成一第一光阻層於部分之該金 光阻層内形成多數個開口; 〃 形成多數個具銲接沾附性(s〇lder 塾,其中任-該第-銲接塾位於 亚在該金屬層上; 移除該第一光阻層; 形成二第二光阻層於部分之該金屬 以该第二光阻層及該第一銲接墊為 ί屬層並移除該第:光阻層以在該基板 線路與多數個銲接界面,其中任一導電 屬層且任一銲接界面均由該金屬層與其 所組成;及 形成一不具銲接沾附性之絕緣層於 及一側表面。 路的方法,其中讀 層上,並在該第— Wettability)的第 任一該開口之 底部 層上; 遮罩移除部分之 上形成多數個導^ 線路電路均為該金 上之該第一銲接墊 该金屬層之一表面第23頁 550800 曰 丄 _ti虎 9iiimi 六、申請專利範圍 ___ 積體 如申請專利範圍第13項之形成不且防炉^ 的方法,其中上述之金屬層的材質為干鋼、之構裳 電& / μ 範圍第13項之形成不呈防銲膜> ^路的方法,其中上述之第—熟、方1干艇之構裝積體 鍍的方法形成。 接墊知用-電氣/化學電 •如申凊專利範圍第1 3項之 電路的t^ 成4不具防銲膜之M a 士 :的方法,#中上述之第于膝之構裝積體 積的方法形成。 墊知用一物理/化學沉 J rj 電路如的申Λ專利甘範圍第13項之形成不具防鮮膜之槿壯 方法,其中上述之構裝㈣電路包含、—曰構衣積體 曰白月 〇 j ·如申請專利範圍第17項之形 電路的古、+ 战不具防録腺夕操a士 多| , 更包含多數個第二銲接巷、之構裝積體 夕數個銲接凸塊相互連結。 于接墊糟以將上述晶片# 電路的申:專利範圍第18項之形成不具防銲膜之爐壯 二銲接墊。 边任#接凸塊均對應至任一該驾 2:·牧如申請專利範圍第18項之形成不且防r『 扪方去,其巾上述之多數個 疋構衣積體 接凸塊與該多數個第- 550800 修正 ---SS_9nU221__年月 日 申請專利範圍 ~接塾相互連接而將該晶片固定於該基板上 專利範圍第20項之形成不具防銲膜之構裝… 、方法,其中上述之任一銲接凸塊均對庳至4貝豆 一銲接墊。 J 5了應至任一該第 2^·如申請專利範圍第丨3項之形成不具防 電路的方法,i Λ l、七夕$良左曰杜、w < 構裝積體 屬氧化層。,、中 “妾沾附性絕緣層可為—金 如申請專利範圍第17項之形成不具防銲膜之 電路的方法,其中上述之晶片及該基板與該晶衣積體 係採用灌膠模混合物(Molding Compound)構裝方々接=處 、々式I固定。 2 4 .如巾請專利範目第17項之形成不具防輝 法,…述之晶片及該基板與該晶片的接合處 '、木用復晶填充(Underfill)構裝方式固定。 2 5 4t •如申請專利範圍第13項之形成不具防銲膜 =的方法1中上述之基板之-底部可藉、個積上 墊連結多數個銲球。 夕數個I干球
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